Fixed MTP to work with TWRP

2025-09-09 01:28:05 -04:00 · 2018-06-19 23:16:04 +02:00 · 2018-06-19 23:16:04 +02:00 · f6dfaef42e
commit f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
--- a/arch/m68k/ifpsp060/CHANGES
+++ b/arch/m68k/ifpsp060/CHANGES
@ -0,0 +1,120 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+CHANGES SINCE LAST RELEASE:
+---------------------------
+
+1) "movep" emulation where data was being read from memory
+was reading the intermediate bytes. Emulation now only
+reads the required bytes.
+
+2) "flogn", "flog2", and "flog10" of "1" was setting the
+Inexact FPSR bit. Emulation now does not set Inexact for
+this case.
+
+3) For an opclass three FP instruction where the effective addressing
+mode was pre-decrement or post-increment and the address register
+was A0 or A1, the address register was not being updated as a result
+of the operation. This has been corrected.
+
+4) Beta B.2 version had the following erratum:
+
+	Scenario:
+	---------
+	If {i,d}mem_{read,write}_{byte,word,long}() returns
+	a failing value to the 68060SP, the package ignores
+	this return value and continues with program execution
+	as if it never received a failing value.
+
+	Effect:
+	-------
+	For example, if a user executed "fsin.x ADDR,fp0" where
+	ADDR should cause a "segmentation violation", the memory read
+	requested by the package should return a failing value
+	to the package. Since the package currently ignores this
+	return value, the user program will continue to the
+	next instruction, and the result created in fp0 will be
+	undefined.
+
+	Fix:
+	----
+	This has been fixed in the current release.
+
+	Notes:
+	------
+	Upon receiving a non-zero (failing) return value from
+	a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
+	the package creates a 16-byte access error stack frame
+	from the current exception stack frame and exits
+	through the "call-out" _real_access(). This is the process
+	as described in the MC68060 User's Manual.
+
+	For instruction read access errors, the info stacked is:
+		SR	= SR at time of exception
+		PC	= PC of instruction being emulated
+		VOFF	= $4008 (stack frame format type)
+		ADDRESS	= PC of instruction being emulated
+		FSLW	= FAULT STATUS LONGWORD
+
+	The valid FSLW bits are:
+		bit 27		= 1	(misaligned bit)
+		bit 24		= 1	(read)
+		bit 23		= 0	(write)
+		bit 22:21	= 10	(SIZE = word)
+		bit 20:19	= 00	(TT)
+		bit 18:16	= x10	(TM; x = 1 for supervisor mode)
+		bit 15		= 1	(IO)
+		bit 0		= 1	(Software Emulation Error)
+
+	all other bits are EQUAL TO ZERO and can be set by the _real_access()
+	"call-out" stub by the user as appropriate. The MC68060 User's Manual
+	stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
+	other bits.
+
+	For data read/write access errors, the info stacked is:
+		SR	= SR at time of exception
+		PC	= PC of instruction being emulated
+		VOFF	= $4008 (stack frame format type)
+		ADDRESS	= Address of source or destination operand
+		FSLW	= FAULT STATUS LONGWORD
+
+	The valid FSLW bits are:
+		bit 27		= 0	(misaligned bit)
+		bit 24		= x	(read; 1 if read, 0 if write)
+		bit 23		= x	(write; 1 if write, 0 if read)
+		bit 22:21	= xx	(SIZE; see MC68060 User's Manual)
+		bit 20:19	= 00	(TT)
+		bit 18:16	= x01	(TM; x = 1 for supervisor mode)
+		bit 15		= 0	(IO)
+		bit 0		= 1	(Software Emulation Error)
+
+	all other bits are EQUAL TO ZERO and can be set by the _real_access()
+	"call-out" stub by the user as appropriate. The MC68060 User's Manual
+	stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
+	other bits.
--- a/arch/m68k/ifpsp060/MISC
+++ b/arch/m68k/ifpsp060/MISC
@ -0,0 +1,201 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+RELEASE FILE VERSIONS:
+-----------------------
+
+fpsp.sa
+----------
+freal.s     : 2.4
+hdr.fpu     : 2.4
+x_fovfl.s   : 2.16
+x_funfl.s   : 2.19
+x_funsupp.s : 2.27
+x_effadd.s  : 2.21
+x_foperr.s  : 2.9
+x_fsnan.s   : 2.12
+x_finex.s   : 2.14
+x_fdz.s     : 2.5
+x_fline.s   : 2.5
+x_funimp.s  : 2.27
+fsin.s      : 2.6
+ftan.s      : 2.6
+fatan.s     : 2.3
+fasin.s     : 2.3
+facos.s     : 2.5
+fetox.s     : 2.4
+fgetem.s    : 2.5
+fcosh.s     : 2.4
+fsinh.s     : 2.5
+ftanh.s     : 2.3
+flogn.s     : 2.6
+fatanh.s    : 2.4
+flog2.s     : 2.4
+ftwotox.s   : 2.4
+fmovecr.s   : 2.5
+fscale.s    : 2.5
+frem_mod.s  : 2.6
+fkern.s     : 2.6
+fkern2.s    : 2.5
+fgen_except.s: 2.7
+foptbl.s    : 2.3
+fmul.s      : 2.5
+fin.s       : 2.4
+fdiv.s      : 2.5
+fneg.s      : 2.4
+ftst.s      : 2.3
+fint.s      : 2.3
+fintrz.s    : 2.3
+fabs.s      : 2.4
+fcmp.s      : 2.4
+fsglmul.s   : 2.5
+fsgldiv.s   : 2.8
+fadd.s      : 2.6
+fsub.s      : 2.6
+fsqrt.s     : 2.4
+fmisc.s     : 2.3
+fdbcc.s     : 2.8
+ftrapcc.s   : 2.5
+fscc.s      : 2.6
+fmovm.s     : 2.15
+fctrl.s     : 2.6
+fcalc_ea.s  : 2.7
+fmem.s      : 2.9
+fout.s      : 2.9
+ireg.s      : 2.6
+fdenorm.s   : 2.3
+fround.s    : 2.4
+fnorm.s     : 2.3
+foptag_set.s: 2.4
+fresult.s   : 2.3
+fpack.s     : 2.6
+fdecbin.s   : 2.4
+fbindec.s   : 2.5
+fbinstr.s   : 2.3
+faccess.s   : 2.3
+
+pfpsp.sa
+----------
+freal.s     : 2.4
+hdr.fpu     : 2.4
+x_fovfl.s   : 2.16
+x_funfl.s   : 2.19
+x_funsupp.s : 2.27
+x_effadd.s  : 2.21
+x_foperr.s  : 2.9
+x_fsnan.s   : 2.12
+x_finex.s   : 2.14
+x_fdz.s     : 2.5
+x_fline2.s  : 2.3
+fcalc_ea.s  : 2.7
+foptbl2.s   : 2.4
+fmovm.s     : 2.15
+fctrl.s     : 2.6
+fmisc.s     : 2.3
+fdenorm.s   : 2.3
+fround.s    : 2.4
+fnorm.s     : 2.3
+foptag_set.s: 2.4
+fresult.s   : 2.3
+fout.s      : 2.9
+fmul.s      : 2.5
+fin.s       : 2.4
+fdiv.s      : 2.5
+fneg.s      : 2.4
+ftst.s      : 2.3
+fint.s      : 2.3
+fintrz.s    : 2.3
+fabs.s      : 2.4
+fcmp.s      : 2.4
+fsglmul.s   : 2.5
+fsgldiv.s   : 2.8
+fadd.s      : 2.6
+fsub.s      : 2.6
+fsqrt.s     : 2.4
+ireg.s      : 2.6
+fpack.s     : 2.6
+fdecbin.s   : 2.4
+fbindec.s   : 2.5
+fbinstr.s   : 2.3
+faccess.s   : 2.3
+
+fplsp.sa
+----------
+lfptop.s    : 2.3
+hdr.fpu     : 2.4
+fsin.s      : 2.6
+ftan.s      : 2.6
+fatan.s     : 2.3
+fasin.s     : 2.3
+facos.s     : 2.5
+fetox.s     : 2.4
+fgetem.s    : 2.5
+fcosh.s     : 2.4
+fsinh.s     : 2.5
+ftanh.s     : 2.3
+flogn.s     : 2.6
+fatanh.s    : 2.4
+flog2.s     : 2.4
+ftwotox.s   : 2.4
+fscale.s    : 2.5
+frem_mod.s  : 2.6
+l_support.s : 2.15
+fnorm.s     : 2.3
+
+isp.sa
+----------
+ireal.s     : 2.4
+hdr.int     : 2.4
+x_uieh.s    : 2.13
+icalc_ea.s  : 2.11
+imovep.s    : 2.8
+ichk2cmp2.s : 2.6
+idiv64.s    : 2.10
+imul64.s    :
+icas2.s     : 2.11
+icas.s      : 2.12
+icas2_core.s: 2.6
+icas_core.s : 2.6
+
+ilsp.sa
+----------
+litop.s     : 2.2
+l_idiv64.s  : 2.8
+l_imul64.s  : 2.6
+l_ichk2cmp2.s: 2.5
+
+ex. files
+----------
+wrk/fskeleton.s: 2.2
+wrk/iskeleton.s: 2.2
+wrk/os.s    : 2.1
+
+tests
+----------
+itest.s     : 2.2
+ftest.s     : 2.1
--- a/arch/m68k/ifpsp060/Makefile
+++ b/arch/m68k/ifpsp060/Makefile
@ -0,0 +1,9 @@
+# Makefile for 680x0 Linux 68060 integer/floating point support package
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "README.legal" in the main directory of this archive
+# for more details.
+
+obj-y := fskeleton.o iskeleton.o os.o
+
+EXTRA_LDFLAGS := -x
--- a/arch/m68k/ifpsp060/README
+++ b/arch/m68k/ifpsp060/README
@ -0,0 +1,71 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Files in this directory:
+-------------------------
+
+fpsp.sa		Full FP Kernel Module - hex image
+fpsp.s		Full FP Kernel Module - source code
+fpsp.doc	Full FP Kernel Module - on-line documentation
+
+pfpsp.sa	Partial FP Kernel Module - hex image
+pfpsp.s		Partial FP Kernel Module - source code
+
+fplsp.sa	FP Library Module - hex image
+fplsp.s		FP Library Module - source code
+fplsp.doc	FP Library Module - on-line documentation
+
+isp.sa		Integer Unimplemented Kernel Module - hex image
+isp.s		Integer Unimplemented Kernel Module - source code
+isp.doc		Integer Unimplemented Kernel Module - on-line doc
+
+ilsp.sa		Integer Unimplemented Library Module - hex image
+ilsp.s		Integer Unimplemented Library Module - source code
+ilsp.doc	Integer Unimplemented Library Module - on-line doc
+
+fskeleton.s	Sample Call-outs needed by fpsp.sa and pfpsp.sa
+
+iskeleton.s	Sample Call-outs needed by isp.sa
+
+os.s		Sample Call-outs needed by fpsp.sa, pfpsp.sa, and isp.sa
+
+ftest.sa	Simple test program to test that {p}fpsp.sa
+		was connected properly; hex image
+ftest.s		above test; source code
+
+itest.sa	Simple test program to test that isp.sa was
+		connected properly; hex image
+itest.s		above test; source code
+
+test.doc	on-line documentation for {i,f}test.sa
+
+README		This file
+
+ERRATA		Known errata for this release
+
+MISC		Release file version numbers
--- a/arch/m68k/ifpsp060/TEST.DOC
+++ b/arch/m68k/ifpsp060/TEST.DOC
@ -0,0 +1,208 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+68060 SOFTWARE PACKAGE (Kernel version) SIMPLE TESTS
+-----------------------------------------------------
+
+The files itest.sa and ftest.sa contain simple tests to check
+the state of the 68060ISP and 68060FPSP once they have been installed.
+
+Release file format:
+--------------------
+The release files itest.sa and ftest.sa are essentially
+hexadecimal images of the actual tests. This format is the
+ONLY format that will be supported. The hex images were created
+by assembling the source code and then converting the resulting
+binary output images into ASCII text files. The hexadecimal
+numbers are listed using the Motorola Assembly syntax assembler
+directive "dc.l" (define constant longword). The files can be
+converted to other assembly syntaxes by using any word processor
+with a global search and replace function.
+
+To assist in assembling and linking these modules with other modules,
+the installer should add symbolic labels to the top of the files.
+This will allow the calling routines to access the entry points
+of these packages.
+
+The source code itest.s and ftest.s have been included but only
+for documentation purposes.
+
+Release file structure:
+-----------------------
+
+(top of module)
+	-----------------
+	|		| - 128 byte-sized section
+   (1)  |   Call-Out	| - 4 bytes per entry (user fills these in)
+	|		|
+	-----------------
+	|		| - 8 bytes per entry
+   (2)  | Entry Point	| - user does "bsr" or "jsr" to this address
+	|		|
+	-----------------
+	|		| - code section
+   (3)  ~		~
+	|		|
+	-----------------
+(bottom of module)
+
+The first section of this module is the "Call-out" section. This section
+is NOT INCLUDED in {i,f}test.sa (an example "Call-out" section is provided at
+the end of this file). The purpose of this section is to allow the test
+routines to reference external printing functions that must be provided
+by the host operating system. This section MUST be exactly 128 bytes in
+size. There are 32 fields, each 4 bytes in size. Each field corresponds
+to a function required by the test packages (these functions and their
+location are listed in "68060{ISP,FPSP}-TEST call-outs" below). Each field
+entry should contain the address of the corresponding function RELATIVE to
+the starting address of the "call-out" section. The "Call-out" section must
+sit adjacent to the {i,f}test.sa image in memory. Since itest.sa and ftest.sa
+are individual tests, they each require their own "Call-out" sections.
+
+The second section, the "Entry-point" section, is used by external routines
+to access the test routines. Since the {i,f}test.sa hex files contain
+no symbol names, this section contains function entry points that are fixed
+with respect to the top of the package. The currently defined entry-points
+are listed in section "68060{ISP,FPSP}-TEST entry points" below. A calling
+routine would simply execute a "bsr" or "jsr" that jumped to the selected
+function entry-point.
+
+For example, to run the 060ISP test, write a program that includes the
+itest.sa data and execute something similar to:
+
+	bsr	_060ISP_TEST+128+0
+
+(_060ISP_TEST is the starting address of the "Call-out" section; the "Call-out"
+section is 128 bytes long; and the 68060ISP test entry point is located
+0 bytes from the top of the "Entry-point" section.)
+
+The third section is the code section. After entering through an "Entry-point",
+the entry code jumps to the appropriate test code within the code section.
+
+68060ISP-TEST Call-outs:
+------------------------
+0x0: _print_string()
+0x4: _print_number()
+
+68060FPSP-TEST Call-outs:
+-------------------------
+0x0: _print_string()
+0x4: _print_number()
+
+The test packages call _print_string() and _print_number()
+as subroutines and expect the main program to print a string
+or a number to a file or to the screen.
+In "C"-like fashion, the test program calls:
+
+	print_string("Test passed");
+
+		or
+
+	print_number(20);
+
+For _print_string(), the test programs pass a longword address
+of the string on the stack. For _print_number(), the test programs pass
+a longword number to be printed.
+
+For debugging purposes, after the main program performs a "print"
+for a test package, it should flush the output so that it's not
+buffered. In this way, if the test program crashes, at least the previous
+statements printed will be seen.
+
+68060ISP-TEST Entry-points:
+---------------------------
+0x0: integer test
+
+68060FPSP-TEST Entry-points:
+----------------------------
+0x00: main fp test
+0x08: FP unimplemented test
+0x10: FP enabled snan/operr/ovfl/unfl/dz/inex
+
+The floating-point unit test has 3 entry points which will require
+3 different calls to the package if each of the three following tests
+is desired:
+
+main fp test: tests (1) unimp effective address exception
+		    (2) unsupported data type exceptions
+		    (3) non-maskable overflow/underflow exceptions
+
+FP unimplemented: tests FP unimplemented exception. this one is
+		  separate from the previous tests for systems that don't
+		  want FP unimplemented instructions.
+
+FP enabled: tests enabled snan/operr/ovfl/unfl/dz/inex.
+	    basically, it enables each of these exceptions and forces
+	    each using an implemented FP instruction. this process
+	    exercises _fpsp_{snan,operr,ovfl,unfl,dz,inex}() and
+	    _real_{snan,operr,ovfl,unfl,dz,inex}(). the test expects
+	    _real_XXXX() to do nothing except clear the exception
+	    and "rte". if a system's _real_XXXX() handler creates an
+	    alternate result, the test will print "failed" but this
+	    is acceptable.
+
+Miscellaneous:
+--------------
+Again, itest.sa and ftest.sa are simple tests and do not thoroughly
+test all 68060SP connections. For example, they do not test connections
+to _real_access(), _real_trace(), _real_trap(), etc. because these
+will be system-implemented several different ways and the test packages
+must remain system independent.
+
+Example test package set-up:
+----------------------------
+_print_str:
+	.			# provided by system
+	rts
+
+_print_num:
+	.			# provided by system
+	rts
+
+	.
+	.
+	bsr	_060FPSP_TEST+128+0
+	.
+	.
+	rts
+
+# beginning of "Call-out" section; provided by integrator.
+# MUST be 128 bytes long.
+_060FPSP_TEST:
+	long	_print_str - _060FPSP_TEST
+	long	_print_num - _060FPSP_TEST
+	space	120
+
+# ftest.sa starts here; start of "Entry-point" section.
+	long	0x60ff0000, 0x00002346
+	long	0x60ff0000, 0x00018766
+	long	0x60ff0000, 0x00023338
+	long	0x24377299, 0xab2643ea
+		.
+		.
+		.
--- a/arch/m68k/ifpsp060/fplsp.doc
+++ b/arch/m68k/ifpsp060/fplsp.doc
@ -0,0 +1,231 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+68060 FLOATING-POINT SOFTWARE PACKAGE (Library version)
+--------------------------------------------------------
+
+The file fplsp.sa contains the "Library version" of the
+68060SP Floating-Point Software Package. The routines
+included in this module can be used to emulate the
+FP instructions not implemented in 68060 hardware. These
+instructions normally take exception vector #11
+"FP Unimplemented Instruction".
+
+By re-compiling a program that uses these instructions, and
+making subroutine calls in place of the unimplemented
+instructions, a program can avoid the overhead associated
+with taking the exception.
+
+Release file format:
+--------------------
+The file fplsp.sa is essentially a hexadecimal image of the
+release package. This is the ONLY format which will be supported.
+The hex image was created by assembling the source code and
+then converting the resulting binary output image into an
+ASCII text file. The hexadecimal numbers are listed
+using the Motorola Assembly Syntax assembler directive "dc.l"
+(define constant longword). The file can be converted to other
+assembly syntaxes by using any word processor with a global
+search and replace function.
+
+To assist in assembling and linking this module with other modules,
+the installer should add a symbolic label to the top of the file.
+This will allow calling routines to access the entry points
+of this package.
+
+The source code fplsp.s has also been included but only for
+documentation purposes.
+
+Release file structure:
+-----------------------
+The file fplsp.sa contains an "Entry-Point" section and a
+code section. The FPLSP has no "Call-Out" section. The first section
+is the "Entry-Point" section. In order to access a function in the
+package, a program must "bsr" or "jsr" to the location listed
+below in "68060FPLSP entry points" that corresponds to the desired
+function. A branch instruction located at the selected entry point
+within the package will then enter the correct emulation code routine.
+
+The entry point addresses at the beginning of the package will remain
+fixed so that a program calling the routines will not have to be
+re-compiled with every new 68060FPLSP release.
+
+There are 3 entry-points for each instruction type: single precision,
+double precision, and extended precision.
+
+As an example, the "fsin" library instruction can be passed an
+extended precision operand if program executes:
+
+# fsin.x fp0
+
+	fmovm.x	&0x01,-(%sp)	# pass operand on stack
+	bsr.l	_060FPLSP_TOP+0x1a8 # branch to fsin routine
+	add.l	&0xc,%sp	# clear operand from stack
+
+Upon return, fp0 holds the correct result. The FPSR is
+set correctly. The FPCR is unchanged. The FPIAR is undefined.
+
+Another example. This time, a dyadic operation:
+
+# frem.s %fp1,%fp0
+
+	fmov.s	%fp1,-(%sp)	# pass src operand
+	fmov.s	%fp0,-(%sp)	# pass dst operand
+	bsr.l	_060FPLSP_TOP+0x168 # branch to frem routine
+	addq.l	&0x8,%sp	# clear operands from stack
+
+Again, the result is returned in fp0. Note that BOTH operands
+are passed in single precision format.
+
+Exception reporting:
+--------------------
+The package takes exceptions according to the FPCR value upon subroutine
+entry. If an exception should be reported, then the package forces
+this exception using implemented floating-point instructions.
+For example, if the instruction being emulated should cause a
+floating-point Operand Error exception, then the library routine
+executes an FMUL of a zero and an infinity to force the OPERR
+exception. Although the FPIAR will be undefined for the enabled
+Operand Error exception handler, the user will at least be able
+to record that the event occurred.
+
+Miscellaneous:
+--------------
+The package does not attempt to correctly emulate instructions
+with Signalling NAN inputs. Use of SNANs should be avoided with
+this package.
+
+The fabs/fadd/fdiv/fint/fintrz/fmul/fneg/fsqrt/fsub entry points
+are provided for the convenience of older compilers that make
+subroutine calls for all fp instructions. The code does NOT emulate
+the instruction but rather simply executes it.
+
+68060FPLSP entry points:
+------------------------
+_060FPLSP_TOP:
+0x000:	_060LSP__facoss_
+0x008:	_060LSP__facosd_
+0x010:	_060LSP__facosx_
+0x018:	_060LSP__fasins_
+0x020:	_060LSP__fasind_
+0x028:	_060LSP__fasinx_
+0x030:	_060LSP__fatans_
+0x038:	_060LSP__fatand_
+0x040:	_060LSP__fatanx_
+0x048:	_060LSP__fatanhs_
+0x050:	_060LSP__fatanhd_
+0x058:	_060LSP__fatanhx_
+0x060:	_060LSP__fcoss_
+0x068:	_060LSP__fcosd_
+0x070:	_060LSP__fcosx_
+0x078:	_060LSP__fcoshs_
+0x080:	_060LSP__fcoshd_
+0x088:	_060LSP__fcoshx_
+0x090:	_060LSP__fetoxs_
+0x098:	_060LSP__fetoxd_
+0x0a0:	_060LSP__fetoxx_
+0x0a8:	_060LSP__fetoxm1s_
+0x0b0:	_060LSP__fetoxm1d_
+0x0b8:	_060LSP__fetoxm1x_
+0x0c0:	_060LSP__fgetexps_
+0x0c8:	_060LSP__fgetexpd_
+0x0d0:	_060LSP__fgetexpx_
+0x0d8:	_060LSP__fgetmans_
+0x0e0:	_060LSP__fgetmand_
+0x0e8:	_060LSP__fgetmanx_
+0x0f0:	_060LSP__flog10s_
+0x0f8:	_060LSP__flog10d_
+0x100:	_060LSP__flog10x_
+0x108:	_060LSP__flog2s_
+0x110:	_060LSP__flog2d_
+0x118:	_060LSP__flog2x_
+0x120:	_060LSP__flogns_
+0x128:	_060LSP__flognd_
+0x130:	_060LSP__flognx_
+0x138:	_060LSP__flognp1s_
+0x140:	_060LSP__flognp1d_
+0x148:	_060LSP__flognp1x_
+0x150:	_060LSP__fmods_
+0x158:	_060LSP__fmodd_
+0x160:	_060LSP__fmodx_
+0x168:	_060LSP__frems_
+0x170:	_060LSP__fremd_
+0x178:	_060LSP__fremx_
+0x180:	_060LSP__fscales_
+0x188:	_060LSP__fscaled_
+0x190:	_060LSP__fscalex_
+0x198:	_060LSP__fsins_
+0x1a0:	_060LSP__fsind_
+0x1a8:	_060LSP__fsinx_
+0x1b0:	_060LSP__fsincoss_
+0x1b8:	_060LSP__fsincosd_
+0x1c0:	_060LSP__fsincosx_
+0x1c8:	_060LSP__fsinhs_
+0x1d0:	_060LSP__fsinhd_
+0x1d8:	_060LSP__fsinhx_
+0x1e0:	_060LSP__ftans_
+0x1e8:	_060LSP__ftand_
+0x1f0:	_060LSP__ftanx_
+0x1f8:	_060LSP__ftanhs_
+0x200:	_060LSP__ftanhd_
+0x208:	_060LSP__ftanhx_
+0x210:	_060LSP__ftentoxs_
+0x218:	_060LSP__ftentoxd_
+0x220:	_060LSP__ftentoxx_
+0x228:	_060LSP__ftwotoxs_
+0x230:	_060LSP__ftwotoxd_
+0x238:	_060LSP__ftwotoxx_
+
+0x240:	_060LSP__fabss_
+0x248:	_060LSP__fabsd_
+0x250:	_060LSP__fabsx_
+0x258:	_060LSP__fadds_
+0x260:	_060LSP__faddd_
+0x268:	_060LSP__faddx_
+0x270:	_060LSP__fdivs_
+0x278:	_060LSP__fdivd_
+0x280:	_060LSP__fdivx_
+0x288:	_060LSP__fints_
+0x290:	_060LSP__fintd_
+0x298:	_060LSP__fintx_
+0x2a0:	_060LSP__fintrzs_
+0x2a8:	_060LSP__fintrzd_
+0x2b0:	_060LSP__fintrzx_
+0x2b8:	_060LSP__fmuls_
+0x2c0:	_060LSP__fmuld_
+0x2c8:	_060LSP__fmulx_
+0x2d0:	_060LSP__fnegs_
+0x2d8:	_060LSP__fnegd_
+0x2e0:	_060LSP__fnegx_
+0x2e8:	_060LSP__fsqrts_
+0x2f0:	_060LSP__fsqrtd_
+0x2f8:	_060LSP__fsqrtx_
+0x300:	_060LSP__fsubs_
+0x308:	_060LSP__fsubd_
+0x310:	_060LSP__fsubx_
--- a/arch/m68k/ifpsp060/fplsp.sa
+++ b/arch/m68k/ifpsp060/fplsp.sa
--- a/arch/m68k/ifpsp060/fpsp.doc
+++ b/arch/m68k/ifpsp060/fpsp.doc
@ -0,0 +1,295 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+68060 FLOATING-POINT SOFTWARE PACKAGE (Kernel version)
+-------------------------------------------------------
+
+The file fpsp.sa contains the 68060 Floating-Point Software
+Package. This package is essentially a set of exception handlers
+that can be integrated into an operating system.
+These exception handlers emulate Unimplemented FP instructions,
+instructions using unimplemented data types, and instructions
+using unimplemented addressing modes. In addition, this package
+includes exception handlers to provide full IEEE-754 compliant
+exception handling.
+
+Release file format:
+--------------------
+The file fpsp.sa is essentially a hexadecimal image of the
+release package. This is the ONLY format which will be supported.
+The hex image was created by assembling the source code and
+then converting the resulting binary output image into an
+ASCII text file. The hexadecimal numbers are listed
+using the Motorola Assembly Syntax assembler directive "dc.l"
+(define constant longword). The file can be converted to other
+assembly syntaxes by using any word processor with a global
+search and replace function.
+
+To assist in assembling and linking this module with other modules,
+the installer should add a symbolic label to the top of the file.
+This will allow calling routines to access the entry points
+of this package.
+
+The source code fpsp.s has also been included but only for
+documentation purposes.
+
+Release file structure:
+-----------------------
+
+(top of module)
+	-----------------
+	|		| - 128 byte-sized section
+   (1)  |   Call-Out	| - 4 bytes per entry (user fills these in)
+	|		| - example routines in fskeleton.s
+	-----------------
+	|		| - 8 bytes per entry
+   (2)  | Entry Point	| - user does "bra" or "jmp" to this address
+	|		|
+	-----------------
+	|		| - code section
+   (3)  ~		~
+	|		|
+	-----------------
+(bottom of module)
+
+The first section of this module is the "Call-out" section. This section
+is NOT INCLUDED in fpsp.sa (an example "Call-out" section is provided at
+the end of the file fskeleton.s). The purpose of this section is to allow
+the FPSP routines to reference external functions that must be provided
+by the host operating system. This section MUST be exactly 128 bytes in
+size. There are 32 fields, each 4 bytes in size. Each field corresponds
+to a function required by the FPSP (these functions and their location are
+listed in "68060FPSP call-outs" below). Each field entry should contain
+the address of the corresponding function RELATIVE to the starting address
+of the "call-out" section. The "Call-out" section must sit adjacent to the
+fpsp.sa image in memory.
+
+The second section, the "Entry-point" section, is used by external routines
+to access the functions within the FPSP. Since the fpsp.sa hex file contains
+no symbol names, this section contains function entry points that are fixed
+with respect to the top of the package. The currently defined entry-points
+are listed in section "68060 FPSP entry points" below. A calling routine
+would simply execute a "bra" or "jmp" that jumped to the selected function
+entry-point.
+
+For example, if the 68060 hardware took a "Line-F Emulator" exception
+(vector #11), the operating system should execute something similar to:
+
+	bra	_060FPSP_TOP+128+48
+
+(_060FPSP_TOP is the starting address of the "Call-out" section; the "Call-out"
+section is 128 bytes long; and the F-Line FPSP handler entry point is located
+48 bytes from the top of the "Entry-point" section.)
+
+The third section is the code section. After entering through an "Entry-point",
+the entry code jumps to the appropriate emulation code within the code section.
+
+68060FPSP call-outs: (details in fskeleton.s)
+--------------------
+0x000:	_060_real_bsun
+0x004:	_060_real_snan
+0x008:	_060_real_operr
+0x00c:	_060_real_ovfl
+0x010:	_060_real_unfl
+0x014:	_060_real_dz
+0x018:	_060_real_inex
+0x01c:	_060_real_fline
+0x020:	_060_real_fpu_disabled
+0x024:	_060_real_trap
+0x028:	_060_real_trace
+0x02c:	_060_real_access
+0x030:	_060_fpsp_done
+
+0x034:	(Motorola reserved)
+0x038:	(Motorola reserved)
+0x03c:	(Motorola reserved)
+
+0x040:	_060_imem_read
+0x044:	_060_dmem_read
+0x048:	_060_dmem_write
+0x04c:	_060_imem_read_word
+0x050:	_060_imem_read_long
+0x054:	_060_dmem_read_byte
+0x058:	_060_dmem_read_word
+0x05c:	_060_dmem_read_long
+0x060:	_060_dmem_write_byte
+0x064:	_060_dmem_write_word
+0x068:	_060_dmem_write_long
+
+0x06c:	(Motorola reserved)
+0x070:	(Motorola reserved)
+0x074:	(Motorola reserved)
+0x078:	(Motorola reserved)
+0x07c:	(Motorola reserved)
+
+68060FPSP entry points:
+-----------------------
+0x000:	_060_fpsp_snan
+0x008:	_060_fpsp_operr
+0x010:	_060_fpsp_ovfl
+0x018:	_060_fpsp_unfl
+0x020:	_060_fpsp_dz
+0x028:	_060_fpsp_inex
+0x030:	_060_fpsp_fline
+0x038:	_060_fpsp_unsupp
+0x040:	_060_fpsp_effadd
+
+
+
+Miscellaneous:
+--------------
+
+_060_fpsp_snan:
+----------------
+- documented in 3.5 of 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_snan --|
+						    |
+            always exits through _060_real_snan <----
+
+_060_fpsp_operr:
+----------------
+- documented in 3.5 of 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_operr --|
+						     |
+           always exits through _060_real_operr <-----
+
+_060_fpsp_dz:
+----------------
+- documented in 3.7 of 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_dz   --|
+						    |
+            always exits through _060_real_dz   <----
+
+_060_fpsp_inex:
+----------------
+- documented in 3.6 of 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_inex --|
+						    |
+            always exits through _060_real_inex <----
+
+
+_060_fpsp_ovfl:
+----------------
+- documented in 3.4 of 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_ovfl --|
+						    |
+            may exit through _060_real_inex     <---|
+						 or |
+            may exit through _060_real_ovfl     <---|
+						 or |
+            may exit through _060_fpsp_done     <---|
+
+_060_fpsp_unfl:
+----------------
+- documented in 3.4 of 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_unfl --|
+						    |
+            may exit through _060_real_inex     <---|
+						 or |
+            may exit through _060_real_unfl     <---|
+						 or |
+            may exit through _060_fpsp_done     <---|
+
+
+_060_fpsp_fline:
+-----------------
+- not fully documented in 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_fline --|
+						     |
+            -------------------------------------------
+            |               |                     |
+            v               v                     v
+   (unimplemented   (fpu disabled)       (possible F-line illegal)
+     stack frame)           |                     v
+            |               v               special case "fmovecr"?
+            |         exit through                    |
+            |     _060_real_fpu_disabled        -------------
+            |                                   |           |
+            |               ^                   v           v
+            |               |                 (yes)        (no)
+            |               |                   v           v
+            |               |             fpu disabled?   exit through
+            |               |                   |         _060_real_fline
+            v               |             -------------
+            |               |             |           |
+            |               |             v           v
+            |               |-----------(yes)        (no)
+            |                                         |
+            |----<------------------------------------|
+            |
+            |
+            |----> may exit through _060_real_trace
+            |
+            |----> may exit through _060_real_trap
+            |
+            |----> may exit through _060_real_bsun
+            |
+            |----> may exit through _060_fpsp_done
+
+
+_060_fpsp_unsupp:
+------------------
+- documented in 3.1 of 060SP spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_unsupp --|
+						      |
+						      |
+            may exit through _060_real_snan      <----|
+						  or  |
+            may exit through _060_real_operr     <----|
+						  or  |
+            may exit through _060_real_ovfl      <----|
+						  or  |
+            may exit through _060_real_unfl      <----|
+						  or  |
+            may exit through _060_real_inex      <----|
+						  or  |
+            may exit through _060_real_trace     <----|
+						  or  |
+            may exit through _060_fpsp_done      <----|
+
+
+_060_fpsp_effadd:
+------------------
+- documented in 3.3 of 060 spec.
+- Basic flow:
+	exception taken ---> enter _060_fpsp_effadd --|
+						      |
+						      |
+            may exit through _060_real_trace     <----|
+						  or  |
+     may exit through _060_real_fpu_disabled     <----|
+						  or  |
+            may exit through _060_fpsp_done      <----|
--- a/arch/m68k/ifpsp060/fpsp.sa
+++ b/arch/m68k/ifpsp060/fpsp.sa
--- a/arch/m68k/ifpsp060/fskeleton.S
+++ b/arch/m68k/ifpsp060/fskeleton.S
@ -0,0 +1,342 @@
+|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+|M68000 Hi-Performance Microprocessor Division
+|M68060 Software Package
+|Production Release P1.00 -- October 10, 1994
+|
+|M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+|
+|THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+|To the maximum extent permitted by applicable law,
+|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+|and any warranty against infringement with regard to the SOFTWARE
+|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+|
+|To the maximum extent permitted by applicable law,
+|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+|
+|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+|so long as this entire notice is retained without alteration in any modified and/or
+|redistributed versions, and that such modified versions are clearly identified as such.
+|No licenses are granted by implication, estoppel or otherwise under any patents
+|or trademarks of Motorola, Inc.
+|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+| fskeleton.s
+|
+| This file contains:
+|	(1) example "Call-out"s
+|	(2) example package entry code
+|	(3) example "Call-out" table
+|
+
+#include <linux/linkage.h>
+
+|################################
+| (1) EXAMPLE CALL-OUTS		#
+|				#
+| _060_fpsp_done()		#
+| _060_real_ovfl()		#
+| _060_real_unfl()		#
+| _060_real_operr()		#
+| _060_real_snan()		#
+| _060_real_dz()		#
+| _060_real_inex()		#
+| _060_real_bsun()		#
+| _060_real_fline()		#
+| _060_real_fpu_disabled()	#
+| _060_real_trap()		#
+|################################
+
+|
+| _060_fpsp_done():
+|
+| This is the main exit point for the 68060 Floating-Point
+| Software Package. For a normal exit, all 060FPSP routines call this
+| routine. The operating system can do system dependent clean-up or
+| simply execute an "rte" as with the sample code below.
+|
+	.global		_060_fpsp_done
+_060_fpsp_done:
+	bral	 _060_isp_done	| do the same as isp_done
+
+|
+| _060_real_ovfl():
+|
+| This is the exit point for the 060FPSP when an enabled overflow exception
+| is present. The routine below should point to the operating system handler
+| for enabled overflow conditions. The exception stack frame is an overflow
+| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
+|
+| The sample routine below simply clears the exception status bit and
+| does an "rte".
+|
+	.global		_060_real_ovfl
+_060_real_ovfl:
+	fsave		-(%sp)
+	move.w		#0x6000,0x2(%sp)
+	frestore	(%sp)+
+	bral		trap	| jump to trap handler
+
+
+|
+| _060_real_unfl():
+|
+| This is the exit point for the 060FPSP when an enabled underflow exception
+| is present. The routine below should point to the operating system handler
+| for enabled underflow conditions. The exception stack frame is an underflow
+| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
+|
+| The sample routine below simply clears the exception status bit and
+| does an "rte".
+|
+	.global		_060_real_unfl
+_060_real_unfl:
+	fsave		-(%sp)
+	move.w		#0x6000,0x2(%sp)
+	frestore	(%sp)+
+	bral		trap	| jump to trap handler
+
+|
+| _060_real_operr():
+|
+| This is the exit point for the 060FPSP when an enabled operand error exception
+| is present. The routine below should point to the operating system handler
+| for enabled operand error exceptions. The exception stack frame is an operand error
+| stack frame. The FP state frame holds the source operand of the faulting
+| instruction.
+|
+| The sample routine below simply clears the exception status bit and
+| does an "rte".
+|
+	.global		_060_real_operr
+_060_real_operr:
+	fsave		-(%sp)
+	move.w		#0x6000,0x2(%sp)
+	frestore	(%sp)+
+	bral		trap	| jump to trap handler
+
+|
+| _060_real_snan():
+|
+| This is the exit point for the 060FPSP when an enabled signalling NaN exception
+| is present. The routine below should point to the operating system handler
+| for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN
+| stack frame. The FP state frame holds the source operand of the faulting
+| instruction.
+|
+| The sample routine below simply clears the exception status bit and
+| does an "rte".
+|
+	.global		_060_real_snan
+_060_real_snan:
+	fsave		-(%sp)
+	move.w		#0x6000,0x2(%sp)
+	frestore	(%sp)+
+	bral		trap	| jump to trap handler
+
+|
+| _060_real_dz():
+|
+| This is the exit point for the 060FPSP when an enabled divide-by-zero exception
+| is present. The routine below should point to the operating system handler
+| for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero
+| stack frame. The FP state frame holds the source operand of the faulting
+| instruction.
+|
+| The sample routine below simply clears the exception status bit and
+| does an "rte".
+|
+	.global		_060_real_dz
+_060_real_dz:
+	fsave		-(%sp)
+	move.w		#0x6000,0x2(%sp)
+	frestore	(%sp)+
+	bral		trap	| jump to trap handler
+
+|
+| _060_real_inex():
+|
+| This is the exit point for the 060FPSP when an enabled inexact exception
+| is present. The routine below should point to the operating system handler
+| for enabled inexact exceptions. The exception stack frame is an inexact
+| stack frame. The FP state frame holds the source operand of the faulting
+| instruction.
+|
+| The sample routine below simply clears the exception status bit and
+| does an "rte".
+|
+	.global		_060_real_inex
+_060_real_inex:
+	fsave		-(%sp)
+	move.w		#0x6000,0x2(%sp)
+	frestore	(%sp)+
+	bral		trap	| jump to trap handler
+
+|
+| _060_real_bsun():
+|
+| This is the exit point for the 060FPSP when an enabled bsun exception
+| is present. The routine below should point to the operating system handler
+| for enabled bsun exceptions. The exception stack frame is a bsun
+| stack frame.
+|
+| The sample routine below clears the exception status bit, clears the NaN
+| bit in the FPSR, and does an "rte". The instruction that caused the
+| bsun will now be re-executed but with the NaN FPSR bit cleared.
+|
+	.global		_060_real_bsun
+_060_real_bsun:
+|	fsave		-(%sp)
+
+	fmove.l		%fpsr,-(%sp)
+	andi.b		#0xfe,(%sp)
+	fmove.l		(%sp)+,%fpsr
+
+	bral		trap	| jump to trap handler
+
+|
+| _060_real_fline():
+|
+| This is the exit point for the 060FPSP when an F-Line Illegal exception is
+| encountered. Three different types of exceptions can enter the F-Line exception
+| vector number 11: FP Unimplemented Instructions, FP implemented instructions when
+| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
+| _fpsp_fline() distinguishes between the three and acts appropriately. F-Line
+| Illegals branch here.
+|
+	.global		_060_real_fline
+_060_real_fline:
+	bral		trap	| jump to trap handler
+
+|
+| _060_real_fpu_disabled():
+|
+| This is the exit point for the 060FPSP when an FPU disabled exception is
+| encountered. Three different types of exceptions can enter the F-Line exception
+| vector number 11: FP Unimplemented Instructions, FP implemented instructions when
+| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
+| _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled
+| exceptions branch here.
+|
+| The sample code below enables the FPU, sets the PC field in the exception stack
+| frame to the PC of the instruction causing the exception, and does an "rte".
+| The execution of the instruction then proceeds with an enabled floating-point
+| unit.
+|
+	.global		_060_real_fpu_disabled
+_060_real_fpu_disabled:
+	move.l		%d0,-(%sp)		| enabled the fpu
+	.long	0x4E7A0808			|movec		pcr,%d0
+	bclr		#0x1,%d0
+	.long	0x4E7B0808			|movec		%d0,pcr
+	move.l		(%sp)+,%d0
+
+	move.l		0xc(%sp),0x2(%sp)	| set "Current PC"
+	rte
+
+|
+| _060_real_trap():
+|
+| This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
+| discovers that the trap condition is true and it should branch to the operating
+| system handler for the trap exception vector number 7.
+|
+| The sample code below simply executes an "rte".
+|
+	.global		_060_real_trap
+_060_real_trap:
+	bral		trap	| jump to trap handler
+
+|############################################################################
+
+|#################################
+| (2) EXAMPLE PACKAGE ENTRY CODE #
+|#################################
+
+	.global		_060_fpsp_snan
+_060_fpsp_snan:
+	bra.l		_FP_CALL_TOP+0x80+0x00
+
+	.global		_060_fpsp_operr
+_060_fpsp_operr:
+	bra.l		_FP_CALL_TOP+0x80+0x08
+
+	.global		_060_fpsp_ovfl
+_060_fpsp_ovfl:
+	bra.l		_FP_CALL_TOP+0x80+0x10
+
+	.global		_060_fpsp_unfl
+_060_fpsp_unfl:
+	bra.l		_FP_CALL_TOP+0x80+0x18
+
+	.global		_060_fpsp_dz
+_060_fpsp_dz:
+	bra.l		_FP_CALL_TOP+0x80+0x20
+
+	.global		_060_fpsp_inex
+_060_fpsp_inex:
+	bra.l		_FP_CALL_TOP+0x80+0x28
+
+	.global		_060_fpsp_fline
+_060_fpsp_fline:
+	bra.l		_FP_CALL_TOP+0x80+0x30
+
+	.global		_060_fpsp_unsupp
+_060_fpsp_unsupp:
+	bra.l		_FP_CALL_TOP+0x80+0x38
+
+	.global		_060_fpsp_effadd
+_060_fpsp_effadd:
+	bra.l		_FP_CALL_TOP+0x80+0x40
+
+|############################################################################
+
+|###############################
+| (3) EXAMPLE CALL-OUT SECTION #
+|###############################
+
+| The size of this section MUST be 128 bytes!!!
+
+_FP_CALL_TOP:
+	.long	_060_real_bsun		- _FP_CALL_TOP
+	.long	_060_real_snan		- _FP_CALL_TOP
+	.long	_060_real_operr		- _FP_CALL_TOP
+	.long	_060_real_ovfl		- _FP_CALL_TOP
+	.long	_060_real_unfl		- _FP_CALL_TOP
+	.long	_060_real_dz		- _FP_CALL_TOP
+	.long	_060_real_inex		- _FP_CALL_TOP
+	.long	_060_real_fline		- _FP_CALL_TOP
+	.long	_060_real_fpu_disabled	- _FP_CALL_TOP
+	.long	_060_real_trap		- _FP_CALL_TOP
+	.long	_060_real_trace		- _FP_CALL_TOP
+	.long	_060_real_access	- _FP_CALL_TOP
+	.long	_060_fpsp_done		- _FP_CALL_TOP
+
+	.long	0x00000000, 0x00000000, 0x00000000
+
+	.long	_060_imem_read		- _FP_CALL_TOP
+	.long	_060_dmem_read		- _FP_CALL_TOP
+	.long	_060_dmem_write		- _FP_CALL_TOP
+	.long	_060_imem_read_word	- _FP_CALL_TOP
+	.long	_060_imem_read_long	- _FP_CALL_TOP
+	.long	_060_dmem_read_byte	- _FP_CALL_TOP
+	.long	_060_dmem_read_word	- _FP_CALL_TOP
+	.long	_060_dmem_read_long	- _FP_CALL_TOP
+	.long	_060_dmem_write_byte	- _FP_CALL_TOP
+	.long	_060_dmem_write_word	- _FP_CALL_TOP
+	.long	_060_dmem_write_long	- _FP_CALL_TOP
+
+	.long	0x00000000
+
+	.long	0x00000000, 0x00000000, 0x00000000, 0x00000000
+
+|############################################################################
+
+| 060 FPSP KERNEL PACKAGE NEEDS TO GO HERE!!!
+
+#include "fpsp.sa"
--- a/arch/m68k/ifpsp060/ftest.sa
+++ b/arch/m68k/ifpsp060/ftest.sa
@ -0,0 +1,371 @@
+	dc.l	$60ff0000,$00d40000,$60ff0000,$016c0000
+	dc.l	$60ff0000,$01a80000,$54657374,$696e6720
+	dc.l	$36383036,$30204650,$53502073,$74617274
+	dc.l	$65643a0a,$00546573,$74696e67,$20363830
+	dc.l	$36302046,$50535020,$756e696d,$706c656d
+	dc.l	$656e7465,$6420696e,$73747275,$6374696f
+	dc.l	$6e207374,$61727465,$643a0a00,$54657374
+	dc.l	$696e6720,$36383036,$30204650,$53502065
+	dc.l	$78636570,$74696f6e,$20656e61,$626c6564
+	dc.l	$20737461,$72746564,$3a0a0070,$61737365
+	dc.l	$640a0020,$6661696c,$65640a00,$4a80660e
+	dc.l	$487affe9,$61ff0000,$1642588f,$4e752f01
+	dc.l	$61ff0000,$164c588f,$487affd9,$61ff0000
+	dc.l	$162a588f,$4e754e56,$fe8048e7,$3f3cf227
+	dc.l	$e0ff487a,$ff3461ff,$00001610,$588f42ae
+	dc.l	$fea0487b,$01700000,$058061ff,$000015fc
+	dc.l	$588f61ff,$00000588,$61ffffff,$ffa242ae
+	dc.l	$fea0487b,$01700000,$126c61ff,$000015dc
+	dc.l	$588f61ff,$00001280,$61ffffff,$ff8242ae
+	dc.l	$fea0487b,$01700000,$0b6461ff,$000015bc
+	dc.l	$61ff0000,$0b7261ff,$ffffff64,$42aefea0
+	dc.l	$487b0170,$00000de2,$61ff0000,$159e61ff
+	dc.l	$00000df0,$61ffffff,$ff464cdf,$3cfcf21f
+	dc.l	$d0ff4e5e,$4e754e56,$fe8048e7,$3f3cf227
+	dc.l	$e0ff487a,$feb161ff,$00001570,$588f42ae
+	dc.l	$fea0487b,$01700000,$00fe61ff,$0000155c
+	dc.l	$588f61ff,$00000110,$61ffffff,$ff024cdf
+	dc.l	$3cfcf21f,$d0ff4e5e,$4e754e56,$fe8048e7
+	dc.l	$3f3cf227,$e0ff487a,$fea461ff,$0000152c
+	dc.l	$588f42ae,$fea0487b,$01700000,$0f1461ff
+	dc.l	$00001518,$61ff0000,$0f1a61ff,$fffffec0
+	dc.l	$42aefea0,$487b0170,$00000fd2,$61ff0000
+	dc.l	$14fa61ff,$00000fd8,$61ffffff,$fea242ae
+	dc.l	$fea0487b,$01700000,$0b6061ff,$000014dc
+	dc.l	$61ff0000,$0b6a61ff,$fffffe84,$42aefea0
+	dc.l	$487b0170,$00000c22,$61ff0000,$14be61ff
+	dc.l	$00000c2c,$61ffffff,$fe6642ae,$fea0487b
+	dc.l	$01700000,$105661ff,$000014a0,$61ff0000
+	dc.l	$105a61ff,$fffffe48,$42aefea0,$487b0170
+	dc.l	$00000da2,$61ff0000,$148261ff,$00000da8
+	dc.l	$61ffffff,$fe2a4cdf,$3cfcf21f,$d0ff4e5e
+	dc.l	$4e750955,$6e696d70,$6c656d65,$6e746564
+	dc.l	$20465020,$696e7374,$72756374,$696f6e73
+	dc.l	$2e2e2e00,$52aefea0,$4cfb3fff,$01700000
+	dc.l	$1390f23b,$d0ff0170,$000013c6,$f23b9c00
+	dc.l	$01700000,$141c3d7c,$0000fea6,$48ee7fff
+	dc.l	$ff80f22e,$f0ffff20,$f22ebc00,$feb42d7c
+	dc.l	$40000000,$fe802d7c,$c90fdaa2,$fe842d7c
+	dc.l	$2168c235,$fe8844fc,$0000f22e,$480efe80
+	dc.l	$42eefea4,$48ee7fff,$ffc0f22e,$f0fffec0
+	dc.l	$f22ebc00,$fea82d7c,$bfbf0000,$ff202d7c
+	dc.l	$80000000,$ff242d7c,$00000000,$ff282d7c
+	dc.l	$08000208,$feb841fa,$ffc22d48,$febc61ff
+	dc.l	$00001288,$4a0066ff,$000012ae,$61ff0000
+	dc.l	$12b04a00,$66ff0000,$12a052ae,$fea04cfb
+	dc.l	$3fff0170,$000012da,$f23bd0ff,$01700000
+	dc.l	$1310f23b,$9c000170,$00001366,$3d7c0000
+	dc.l	$fea648ee,$7fffff80,$f22ef0ff,$ff20f22e
+	dc.l	$bc00feb4,$2d7c3ffe,$0000fe80,$2d7cc90f
+	dc.l	$daa2fe84,$2d7c2168,$c235fe88,$44fc0000
+	dc.l	$f22e480f,$fe8042ee,$fea448ee,$7fffffc0
+	dc.l	$f22ef0ff,$fec0f22e,$bc00fea8,$2d7c3fff
+	dc.l	$0000ff20,$2d7c8000,$0000ff24,$2d7c0000
+	dc.l	$0000ff28,$2d7c0000,$0208feb8,$41faffc2
+	dc.l	$2d48febc,$61ff0000,$11d24a00,$66ff0000
+	dc.l	$11f861ff,$000011fa,$4a0066ff,$000011ea
+	dc.l	$52aefea0,$4cfb3fff,$01700000,$1224f23b
+	dc.l	$d0ff0170,$0000125a,$f23b9c00,$01700000
+	dc.l	$12b03d7c,$0000fea6,$48ee7fff,$ff80f22e
+	dc.l	$f0ffff20,$f22ebc00,$feb444fc,$0000f200
+	dc.l	$5c3142ee,$fea448ee,$7fffffc0,$f22ef0ff
+	dc.l	$fec0f22e,$bc00fea8,$2d7c4000,$0000ff20
+	dc.l	$2d7c935d,$8dddff24,$2d7caaa8,$ac17ff28
+	dc.l	$2d7c0000,$0208feb8,$41faffc4,$2d48febc
+	dc.l	$61ff0000,$11364a00,$66ff0000,$115c61ff
+	dc.l	$0000115e,$4a0066ff,$0000114e,$52aefea0
+	dc.l	$4cfb3fff,$01700000,$1188f23b,$d0ff0170
+	dc.l	$000011be,$f23b9c00,$01700000,$1214f23c
+	dc.l	$88000f00,$00007e00,$3d7c0000,$fea648ee
+	dc.l	$7fffff80,$f22ef0ff,$ff20f22e,$bc00feb4
+	dc.l	$44fc0000,$f2470012,$42eefea4,$48ee7fff
+	dc.l	$ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c
+	dc.l	$0f008080,$feb841fa,$ffdc2d48,$febc61ff
+	dc.l	$000010a8,$4a0066ff,$000010ce,$61ff0000
+	dc.l	$10d04a00,$66ff0000,$10c052ae,$fea04cfb
+	dc.l	$3fff0170,$000010fa,$f23bd0ff,$01700000
+	dc.l	$1130f23b,$9c000170,$00001186,$f23c8800
+	dc.l	$0f000000,$7e023d7c,$0000fea6,$48ee7fff
+	dc.l	$ff80f22e,$f0ffff20,$f22ebc00,$feb444fc
+	dc.l	$0000f24f,$0012fffc,$42eefea4,$48ee7fff
+	dc.l	$ffc0f22e,$f0fffec0,$f22ebc00,$fea83d7c
+	dc.l	$ffffff9e,$2d7c0f00,$8080feb8,$41faffd4
+	dc.l	$2d48febc,$61ff0000,$10124a00,$66ff0000
+	dc.l	$103861ff,$0000103a,$4a0066ff,$0000102a
+	dc.l	$52aefea0,$4cfb3fff,$01700000,$1064f23b
+	dc.l	$d0ff0170,$0000109a,$f23b9c00,$01700000
+	dc.l	$10f0f23c,$88000f00,$00003d7c,$0000fea6
+	dc.l	$48ee7fff,$ff80f22e,$f0ffff20,$f22ebc00
+	dc.l	$feb444fc,$0000f27b,$0012abcd,$ef0142ee
+	dc.l	$fea448ee,$7fffffc0,$f22ef0ff,$fec0f22e
+	dc.l	$bc00fea8,$2d7c0f00,$8080feb8,$41faffd8
+	dc.l	$2d48febc,$61ff0000,$0f824a00,$66ff0000
+	dc.l	$0fa861ff,$00000faa,$4a0066ff,$00000f9a
+	dc.l	$42804e75,$09556e69,$6d706c65,$6d656e74
+	dc.l	$6564203c,$65613e2e,$2e2e0000,$52aefea0
+	dc.l	$4cfb3fff,$01700000,$0fb8f23b,$d0ff0170
+	dc.l	$00000fee,$f23b9c00,$01700000,$10443d7c
+	dc.l	$0000fea6,$48ee7fff,$ff80f22e,$f0ffff20
+	dc.l	$f22ebc00,$feb4f23c,$58000002,$44fc0000
+	dc.l	$f23c4823,$c0000000,$80000000,$00000000
+	dc.l	$42eefea4,$48ee7fff,$ffc0f22e,$f0fffec0
+	dc.l	$f22ebc00,$fea82d7c,$c0010000,$ff202d7c
+	dc.l	$80000000,$ff242d7c,$00000000,$ff282d7c
+	dc.l	$08000000,$feb841fa,$ffb82d48,$febc61ff
+	dc.l	$00000eb8,$4a0066ff,$00000ede,$61ff0000
+	dc.l	$0ee04a00,$66ff0000,$0ed052ae,$fea04cfb
+	dc.l	$3fff0170,$00000f0a,$f23bd0ff,$01700000
+	dc.l	$0f40f23b,$9c000170,$00000f96,$3d7c0000
+	dc.l	$fea648ee,$7fffff80,$f22ef0ff,$ff20f22e
+	dc.l	$bc00feb4,$44fc0000,$f23c4c18,$c1230001
+	dc.l	$23456789,$12345678,$42eefea4,$48ee7fff
+	dc.l	$ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c
+	dc.l	$3e660000,$ff202d7c,$d0ed23e8,$ff242d7c
+	dc.l	$d14035bc,$ff282d7c,$00000108,$feb841fa
+	dc.l	$ffb82d48,$febc61ff,$00000e10,$4a0066ff
+	dc.l	$00000e36,$61ff0000,$0e384a00,$66ff0000
+	dc.l	$0e2852ae,$fea04cfb,$3fff0170,$00000e62
+	dc.l	$f23bd0ff,$01700000,$0e98f23b,$9c000170
+	dc.l	$00000eee,$3d7c0000,$fea644fc,$000048ee
+	dc.l	$7fffff80,$f22ef0ff,$ff20f22e,$bc00feb4
+	dc.l	$f23c9800,$ffffffff,$ffffffff,$42eefea4
+	dc.l	$48ee7fff,$ffc0f22e,$f0fffec0,$f22ebc00
+	dc.l	$fea82d7c,$0000fff0,$feb42d7c,$0ffffff8
+	dc.l	$feb861ff,$00000d84,$4a0066ff,$00000daa
+	dc.l	$61ff0000,$0dac4a00,$66ff0000,$0d9c52ae
+	dc.l	$fea04cfb,$3fff0170,$00000dd6,$f23bd0ff
+	dc.l	$01700000,$0e0cf23b,$9c000170,$00000e62
+	dc.l	$3d7c0000,$fea644fc,$000048ee,$7fffff80
+	dc.l	$f22ef0ff,$ff20f22e,$bc00feb4,$f23c9400
+	dc.l	$ffffffff,$ffffffff,$42eefea4,$48ee7fff
+	dc.l	$ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c
+	dc.l	$0000fff0,$feb42d7c,$ffffffff,$febc61ff
+	dc.l	$00000cf8,$4a0066ff,$00000d1e,$61ff0000
+	dc.l	$0d204a00,$66ff0000,$0d1052ae,$fea04cfb
+	dc.l	$3fff0170,$00000d4a,$f23bd0ff,$01700000
+	dc.l	$0d80f23b,$9c000170,$00000dd6,$3d7c0000
+	dc.l	$fea644fc,$000048ee,$7fffff80,$f22ef0ff
+	dc.l	$ff20f22e,$bc00feb4,$f23c8c00,$ffffffff
+	dc.l	$ffffffff,$42eefea4,$48ee7fff,$ffc0f22e
+	dc.l	$f0fffec0,$f22ebc00,$fea82d7c,$0ffffff8
+	dc.l	$feb82d7c,$ffffffff,$febc61ff,$00000c6c
+	dc.l	$4a0066ff,$00000c92,$61ff0000,$0c944a00
+	dc.l	$66ff0000,$0c8452ae,$fea04cfb,$3fff0170
+	dc.l	$00000cbe,$f23bd0ff,$01700000,$0cf4f23b
+	dc.l	$9c000170,$00000d4a,$3d7c0000,$fea644fc
+	dc.l	$000048ee,$7fffff80,$f22ef0ff,$ff20f22e
+	dc.l	$bc00feb4,$f23c9c00,$ffffffff,$ffffffff
+	dc.l	$ffffffff,$42eefea4,$48ee7fff,$ffc0f22e
+	dc.l	$f0fffec0,$f22ebc00,$fea82d7c,$0000fff0
+	dc.l	$feb42d7c,$0ffffff8,$feb82d7c,$ffffffff
+	dc.l	$febc61ff,$00000bd4,$4a0066ff,$00000bfa
+	dc.l	$61ff0000,$0bfc4a00,$66ff0000,$0bec52ae
+	dc.l	$fea04cfb,$3fff0170,$00000c26,$f23bd0ff
+	dc.l	$01700000,$0c5cf23b,$9c000170,$00000cb2
+	dc.l	$f23c5800,$0001f23c,$58800002,$f23c5900
+	dc.l	$0003f23c,$59800004,$f23c5a00,$0005f23c
+	dc.l	$5a800006,$f23c5b00,$0007f23c,$5b800008
+	dc.l	$f23c8400,$00000000,$70aa3d7c,$0000fea6
+	dc.l	$48eeffff,$ff80f22e,$bc00feb4,$f22ef0ff
+	dc.l	$ff2044fc,$0000f227,$e80042ee,$fea4f22e
+	dc.l	$bc00fea8,$f23c4480,$7f800000,$f23c4580
+	dc.l	$7f800000,$f23c4680,$7f800000,$f23c4780
+	dc.l	$7f800000,$f21f4880,$f21f4980,$f21f4a80
+	dc.l	$f21f4b80,$48eeffff,$ffc0f22e,$f0fffec0
+	dc.l	$61ff0000,$0af64a00,$66ff0000,$0b1c61ff
+	dc.l	$00000b1e,$4a0066ff,$00000b0e,$52aefea0
+	dc.l	$4cfb3fff,$01700000,$0b48f23b,$d0ff0170
+	dc.l	$00000b7e,$f23b9c00,$01700000,$0bd4f23c
+	dc.l	$58000001,$f23c5880,$0002f23c,$59000003
+	dc.l	$f23c5980,$0004f23c,$5a000005,$f23c5a80
+	dc.l	$0006f23c,$5b000007,$f23c5b80,$0008f227
+	dc.l	$6b00f227,$6a00f227,$6900f227,$6800f22e
+	dc.l	$f0ffff20,$f23c4700,$7f800000,$f23c4600
+	dc.l	$7f800000,$f23c4500,$7f800000,$f23c4400
+	dc.l	$7f800000,$f23c8400,$00000000,$f23c8800
+	dc.l	$00000000,$70aa3d7c,$0000fea6,$48eeffff
+	dc.l	$ff80f22e,$bc00feb4,$44fc0000,$f21fd800
+	dc.l	$42eefea4,$f22ebc00,$fea848ee,$ffffffc0
+	dc.l	$f22ef0ff,$fec061ff,$00000a10,$4a0066ff
+	dc.l	$00000a36,$61ff0000,$0a384a00,$66ff0000
+	dc.l	$0a2852ae,$fea04cfb,$3fff0170,$00000a62
+	dc.l	$f23bd0ff,$01700000,$0a98f23b,$9c000170
+	dc.l	$00000aee,$f23c5800,$0001f23c,$58800002
+	dc.l	$f23c5900,$0003f23c,$59800004,$f23c5a00
+	dc.l	$0005f23c,$5a800006,$f23c5b00,$0007f23c
+	dc.l	$5b800008,$f23c8400,$00000000,$203cffff
+	dc.l	$ff003d7c,$0000fea6,$48eeffff,$ff80f22e
+	dc.l	$bc00feb4,$f22ef0ff,$ff2044fc,$0000f227
+	dc.l	$e80042ee,$fea4f22e,$bc00fea8,$48eeffff
+	dc.l	$ffc0f22e,$f0fffec0,$61ff0000,$095e4a00
+	dc.l	$66ff0000,$098461ff,$00000986,$4a0066ff
+	dc.l	$00000976,$42804e75,$094e6f6e,$2d6d6173
+	dc.l	$6b61626c,$65206f76,$6572666c,$6f772e2e
+	dc.l	$2e0051fc,$52aefea0,$4cfb3fff,$01700000
+	dc.l	$0990f23b,$d0ff0170,$000009c6,$f23b9c00
+	dc.l	$01700000,$0a1c3d7c,$0000fea6,$48ee7fff
+	dc.l	$ff80f22e,$f0ffff20,$f22ebc00,$feb4f23c
+	dc.l	$58000002,$2d7c7ffe,$0000fe80,$2d7c8000
+	dc.l	$0000fe84,$2d7c0000,$0000fe88,$44fc0000
+	dc.l	$f22e4823,$fe8042ee,$fea448ee,$7fffffc0
+	dc.l	$f22ef0ff,$fec0f22e,$bc00fea8,$2d7c7fff
+	dc.l	$0000ff20,$2d7c0000,$0000ff24,$2d7c0000
+	dc.l	$0000ff28,$2d7c0200,$1048feb8,$41faffc2
+	dc.l	$2d48febc,$61ff0000,$08824a00,$66ff0000
+	dc.l	$08a861ff,$000008aa,$4a0066ff,$0000089a
+	dc.l	$42804e75,$09456e61,$626c6564,$206f7665
+	dc.l	$72666c6f,$772e2e2e,$000051fc,$52aefea0
+	dc.l	$4cfb3fff,$01700000,$08b8f23b,$d0ff0170
+	dc.l	$000008ee,$f23b9c00,$01700000,$09443d7c
+	dc.l	$0000fea6,$48ee7fff,$ff80f22e,$f0ffff20
+	dc.l	$f23c9000,$00001000,$f22ebc00,$feb4f23c
+	dc.l	$58000002,$2d7c7ffe,$0000fe80,$2d7c8000
+	dc.l	$0000fe84,$2d7c0000,$0000fe88,$44fc0000
+	dc.l	$f22e4823,$fe8042ee,$fea448ee,$7fffffc0
+	dc.l	$f22ef0ff,$fec0f22e,$bc00fea8,$2d7c7fff
+	dc.l	$0000ff20,$2d7c0000,$0000ff24,$2d7c0000
+	dc.l	$0000ff28,$2d7c0200,$1048feb8,$41faffc2
+	dc.l	$2d48febc,$61ff0000,$07a24a00,$66ff0000
+	dc.l	$07c861ff,$000007ca,$4a0066ff,$000007ba
+	dc.l	$42804e75,$09456e61,$626c6564,$20756e64
+	dc.l	$6572666c,$6f772e2e,$2e0051fc,$52aefea0
+	dc.l	$4cfb3fff,$01700000,$07d8f23b,$d0ff0170
+	dc.l	$0000080e,$f23b9c00,$01700000,$08643d7c
+	dc.l	$0000fea6,$48ee7fff,$ff80f22e,$f0ffff20
+	dc.l	$f23c9000,$00000800,$f22ebc00,$feb42d7c
+	dc.l	$00000000,$fe802d7c,$80000000,$fe842d7c
+	dc.l	$00000000,$fe88f22e,$d080fe80,$44fc0000
+	dc.l	$f23c5820,$000242ee,$fea448ee,$7fffffc0
+	dc.l	$f22ef0ff,$fec0f22e,$bc00fea8,$2d7c0000
+	dc.l	$0000ff20,$2d7c4000,$0000ff24,$2d7c0000
+	dc.l	$0000ff28,$2d7c0000,$0800feb8,$41faffc2
+	dc.l	$2d48febc,$61ff0000,$06c24a00,$66ff0000
+	dc.l	$06e861ff,$000006ea,$4a0066ff,$000006da
+	dc.l	$42804e75,$094e6f6e,$2d6d6173,$6b61626c
+	dc.l	$6520756e,$64657266,$6c6f772e,$2e2e0000
+	dc.l	$52aefea0,$4cfb3fff,$01700000,$06f4f23b
+	dc.l	$d0ff0170,$0000072a,$f23b9c00,$01700000
+	dc.l	$07803d7c,$0000fea6,$48ee7fff,$ff80f22e
+	dc.l	$f0ffff20,$f22ebc00,$feb42d7c,$00000000
+	dc.l	$fe802d7c,$80000000,$fe842d7c,$00000000
+	dc.l	$fe88f22e,$d080fe80,$44fc0000,$f23c5820
+	dc.l	$000242ee,$fea448ee,$7fffffc0,$f22ef0ff
+	dc.l	$fec0f22e,$bc00fea8,$2d7c0000,$0000ff20
+	dc.l	$2d7c4000,$0000ff24,$2d7c0000,$0000ff28
+	dc.l	$2d7c0000,$0800feb8,$41faffc2,$2d48febc
+	dc.l	$61ff0000,$05e64a00,$66ff0000,$060c61ff
+	dc.l	$0000060e,$4a0066ff,$000005fe,$42804e75
+	dc.l	$09456e61,$626c6564,$20696e65,$78616374
+	dc.l	$2e2e2e00,$52aefea0,$4cfb3fff,$01700000
+	dc.l	$0620f23b,$d0ff0170,$00000656,$f23b9c00
+	dc.l	$01700000,$06ac3d7c,$0000fea6,$48ee7fff
+	dc.l	$ff80f22e,$f0ffff20,$f23c9000,$00000200
+	dc.l	$f22ebc00,$feb42d7c,$50000000,$fe802d7c
+	dc.l	$80000000,$fe842d7c,$00000000,$fe88f22e
+	dc.l	$d080fe80,$44fc0000,$f23c5822,$000242ee
+	dc.l	$fea448ee,$7fffffc0,$f22ef0ff,$fec0f22e
+	dc.l	$bc00fea8,$2d7c5000,$0000ff20,$2d7c8000
+	dc.l	$0000ff24,$2d7c0000,$0000ff28,$2d7c0000
+	dc.l	$0208feb8,$41faffc2,$2d48febc,$61ff0000
+	dc.l	$050a4a00,$66ff0000,$053061ff,$00000532
+	dc.l	$4a0066ff,$00000522,$42804e75,$09456e61
+	dc.l	$626c6564,$20534e41,$4e2e2e2e,$000051fc
+	dc.l	$52aefea0,$4cfb3fff,$01700000,$0544f23b
+	dc.l	$d0ff0170,$0000057a,$f23b9c00,$01700000
+	dc.l	$05d03d7c,$0000fea6,$48ee7fff,$ff80f22e
+	dc.l	$f0ffff20,$f23c9000,$00004000,$f22ebc00
+	dc.l	$feb42d7c,$ffff0000,$fe802d7c,$00000000
+	dc.l	$fe842d7c,$00000001,$fe88f22e,$d080fe80
+	dc.l	$44fc0000,$f23c5822,$000242ee,$fea448ee
+	dc.l	$7fffffc0,$f22ef0ff,$fec0f22e,$bc00fea8
+	dc.l	$2d7cffff,$0000ff20,$2d7c0000,$0000ff24
+	dc.l	$2d7c0000,$0001ff28,$2d7c0900,$4080feb8
+	dc.l	$41faffc2,$2d48febc,$61ff0000,$042e4a00
+	dc.l	$66ff0000,$045461ff,$00000456,$4a0066ff
+	dc.l	$00000446,$42804e75,$09456e61,$626c6564
+	dc.l	$204f5045,$52522e2e,$2e0051fc,$52aefea0
+	dc.l	$4cfb3fff,$01700000,$0468f23b,$d0ff0170
+	dc.l	$0000049e,$f23b9c00,$01700000,$04f43d7c
+	dc.l	$0000fea6,$48ee7fff,$ff80f22e,$f0ffff20
+	dc.l	$f23c9000,$00002000,$f22ebc00,$feb42d7c
+	dc.l	$ffff0000,$fe802d7c,$00000000,$fe842d7c
+	dc.l	$00000000,$fe88f22e,$d080fe80,$44fc0000
+	dc.l	$f23c4422,$7f800000,$42eefea4,$48ee7fff
+	dc.l	$ffc0f22e,$f0fffec0,$f22ebc00,$fea82d7c
+	dc.l	$ffff0000,$ff202d7c,$00000000,$ff242d7c
+	dc.l	$00000000,$ff282d7c,$01002080,$feb841fa
+	dc.l	$ffc02d48,$febc61ff,$00000350,$4a0066ff
+	dc.l	$00000376,$61ff0000,$03784a00,$66ff0000
+	dc.l	$03684280,$4e750945,$6e61626c,$65642044
+	dc.l	$5a2e2e2e,$000051fc,$52aefea0,$4cfb3fff
+	dc.l	$01700000,$038cf23b,$d0ff0170,$000003c2
+	dc.l	$f23b9c00,$01700000,$04183d7c,$0000fea6
+	dc.l	$48ee7fff,$ff80f22e,$f0ffff20,$f23c9000
+	dc.l	$00000400,$f22ebc00,$feb42d7c,$40000000
+	dc.l	$fe802d7c,$80000000,$fe842d7c,$00000000
+	dc.l	$fe88f22e,$d080fe80,$44fc0000,$f23c5820
+	dc.l	$000042ee,$fea448ee,$7fffffc0,$f22ef0ff
+	dc.l	$fec0f22e,$bc00fea8,$2d7c4000,$0000ff20
+	dc.l	$2d7c8000,$0000ff24,$2d7c0000,$0000ff28
+	dc.l	$2d7c0200,$0410feb8,$41faffc2,$2d48febc
+	dc.l	$61ff0000,$02764a00,$66ff0000,$029c61ff
+	dc.l	$0000029e,$4a0066ff,$0000028e,$42804e75
+	dc.l	$09556e69,$6d706c65,$6d656e74,$65642064
+	dc.l	$61746120,$74797065,$2f666f72,$6d61742e
+	dc.l	$2e2e0000,$52aefea0,$4cfb3fff,$01700000
+	dc.l	$02a0f23b,$d0ff0170,$000002d6,$f23b9c00
+	dc.l	$01700000,$032c3d7c,$0000fea6,$48ee7fff
+	dc.l	$ff80f22e,$f0ffff20,$f22ebc00,$feb42d7c
+	dc.l	$c03f0000,$fe802d7c,$00000000,$fe842d7c
+	dc.l	$00000001,$fe88f23c,$58000002,$44fc0000
+	dc.l	$f22e4823,$fe8042ee,$fea448ee,$7fffffc0
+	dc.l	$f22ef0ff,$fec0f22e,$bc00fea8,$2d7cc001
+	dc.l	$0000ff20,$2d7c8000,$0000ff24,$2d7c0000
+	dc.l	$0000ff28,$2d7c0800,$0000feb8,$41faffc2
+	dc.l	$2d48febc,$61ff0000,$01924a00,$66ff0000
+	dc.l	$01b861ff,$000001ba,$4a0066ff,$000001aa
+	dc.l	$52aefea0,$4cfb3fff,$01700000,$01e4f23b
+	dc.l	$d0ff0170,$0000021a,$f23b9c00,$01700000
+	dc.l	$02703d7c,$0000fea6,$48ee7fff,$ff80f22e
+	dc.l	$f0ffff20,$f22ebc00,$feb42d7c,$80000000
+	dc.l	$fe802d7c,$01000000,$fe842d7c,$00000000
+	dc.l	$fe88f23c,$40007fff,$ffff44fc,$0000f22e
+	dc.l	$4823fe80,$42eefea4,$48ee7fff,$ffc0f22e
+	dc.l	$f0fffec0,$f22ebc00,$fea82d7c,$80170000
+	dc.l	$ff202d7c,$fffffffe,$ff242d7c,$00000000
+	dc.l	$ff282d7c,$08000000,$feb841fa,$ffc22d48
+	dc.l	$febc61ff,$000000d4,$4a0066ff,$000000fa
+	dc.l	$61ff0000,$00fc4a00,$66ff0000,$00ec52ae
+	dc.l	$fea04cfb,$3fff0170,$00000126,$f23bd0ff
+	dc.l	$01700000,$015cf23b,$9c000170,$000001b2
+	dc.l	$3d7c0000,$fea648ee,$7fffff80,$f22ef0ff
+	dc.l	$ff20f22e,$bc00feb4,$2d7cc123,$0001fe80
+	dc.l	$2d7c2345,$6789fe84,$2d7c1234,$5678fe88
+	dc.l	$44fc0000,$f22e4c18,$fe8042ee,$fea448ee
+	dc.l	$7fffffc0,$f22ef0ff,$fec0f22e,$bc00fea8
+	dc.l	$2d7c3e66,$0000ff20,$2d7cd0ed,$23e8ff24
+	dc.l	$2d7cd140,$35bcff28,$2d7c0000,$0108feb8
+	dc.l	$41faffc2,$2d48febc,$61ff0000,$001e4a00
+	dc.l	$66ff0000,$004461ff,$00000046,$4a0066ff
+	dc.l	$00000036,$42804e75,$41eeff80,$43eeffc0
+	dc.l	$700eb189,$66ff0000,$001c51c8,$fff6302e
+	dc.l	$fea6322e,$fea4b041,$66ff0000,$00084280
+	dc.l	$4e757001,$4e75222e,$fea07001,$4e7541ee
+	dc.l	$ff2043ee,$fec07017,$b18966ff,$0000002c
+	dc.l	$51c8fff6,$41eefeb4,$43eefea8,$b18966ff
+	dc.l	$00000018,$b18966ff,$00000010,$b18966ff
+	dc.l	$00000008,$42804e75,$70014e75,$acacacac
+	dc.l	$acacacac,$acacacac,$acacacac,$acacacac
+	dc.l	$acacacac,$acacacac,$acacacac,$acacacac
+	dc.l	$acacacac,$acacacac,$acacacac,$acacacac
+	dc.l	$acacacac,$acacacac,$acacacac,$7fff0000
+	dc.l	$ffffffff,$ffffffff,$7fff0000,$ffffffff
+	dc.l	$ffffffff,$7fff0000,$ffffffff,$ffffffff
+	dc.l	$7fff0000,$ffffffff,$ffffffff,$7fff0000
+	dc.l	$ffffffff,$ffffffff,$7fff0000,$ffffffff
+	dc.l	$ffffffff,$7fff0000,$ffffffff,$ffffffff
+	dc.l	$7fff0000,$ffffffff,$ffffffff,$00000000
+	dc.l	$00000000,$00000000,$2f00203a,$e884487b
+	dc.l	$0930ffff,$e880202f,$00044e74,$00042f00
+	dc.l	$203ae872,$487b0930,$ffffe86a,$202f0004
+	dc.l	$4e740004,$00000000,$00000000,$00000000
--- a/arch/m68k/ifpsp060/ilsp.doc
+++ b/arch/m68k/ifpsp060/ilsp.doc
@ -0,0 +1,150 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+68060 INTEGER SOFTWARE PACKAGE (Library version)
+-------------------------------------------------
+
+The file ilsp.s contains the "Library version" of the
+68060 Integer Software Package. Routines included in this
+module can be used to emulate 64-bit divide and multiply,
+and the "cmp2" instruction. These instructions are not
+implemented in hardware on the 68060 and normally take
+exception vector #61 "Unimplemented Integer Instruction".
+
+By re-compiling a program that uses these instructions, and
+making subroutine calls in place of the unimplemented
+instructions, a program can avoid the overhead associated with
+taking the exception.
+
+Release file format:
+--------------------
+The file ilsp.sa is essentially a hexadecimal image of the
+release package. This is the ONLY format which will be supported.
+The hex image was created by assembling the source code and
+then converting the resulting binary output image into an
+ASCII text file. The hexadecimal numbers are listed
+using the Motorola Assembly Syntax assembler directive "dc.l"
+(define constant longword). The file can be converted to other
+assembly syntaxes by using any word processor with a global
+search and replace function.
+
+To assist in assembling and linking this module with other modules,
+the installer should add a symbolic label to the top of the file.
+This will allow calling routines to access the entry points
+of this package.
+
+The source code ilsp.s has also been included but only for
+documentation purposes.
+
+Release file structure:
+-----------------------
+The file ilsp.sa contains an "Entry-Point" section and a
+code section. The ILSP has no "Call-Out" section. The first section
+is the "Entry-Point" section. In order to access a function in the
+package, a program must "bsr" or "jsr" to the location listed
+below in "68060ILSP Entry Points" that corresponds to the desired
+function. A branch instruction located at the selected entry point
+within the package will then enter the correct emulation code routine.
+
+The entry point addresses at the beginning of the package will remain
+fixed so that a program calling the routines will not have to be
+re-compiled with every new 68060ILSP release.
+
+For example, to use a 64-bit multiply instruction,
+do a "bsr" or "jsr" to the entry point defined by
+the 060ILSP entry table. A compiler generated code sequence
+for unsigned multiply could look like:
+
+# mulu.l <ea>,Dh:Dl
+# mulu.l _multiplier,%d1:%d0
+
+	subq.l	&0x8,%sp	# make room for result on stack
+	pea	(%sp)		# pass: result addr on stack
+	mov.l	%d0,-(%sp)	# pass: multiplicand on stack
+	mov.l	_multiplier,-(%sp) # pass: multiplier on stack
+	bsr.l	_060LISP_TOP+0x18 # branch to multiply routine
+	add.l	&0xc,%sp	# clear arguments from stack
+	mov.l	(%sp)+,%d1	# load result[63:32]
+	mov.l	(%sp)+,%d0	# load result[31:0]
+
+For a divide:
+
+# divu.l <ea>,Dr:Dq
+# divu.l _divisor,%d1:%d0
+
+	subq.l	&0x8,%sp	# make room for result on stack
+	pea	(%sp)		# pass: result addr on stack
+	mov.l	%d0,-(%sp)	# pass: dividend hi on stack
+	mov.l	%d1,-(%sp)	# pass: dividend hi on stack
+	mov.l	_divisor,-(%sp) # pass: divisor on stack
+	bsr.l	_060LISP_TOP+0x08 # branch to divide routine
+	add.l	&0xc,%sp	# clear arguments from stack
+	mov.l	(%sp)+,%d1	# load remainder
+	mov.l	(%sp)+,%d0	# load quotient
+
+The library routines also return the correct condition code
+register value. If this is important, then the caller of the library
+routine must make sure that the value isn't lost while popping
+other items off of the stack.
+
+An example of using the "cmp2" instruction is as follows:
+
+# cmp2.l <ea>,Rn
+# cmp2.l _bounds,%d0
+
+	pea	_bounds		# pass ptr to bounds
+	mov.l	%d0,-(%sp)	# pass Rn
+	bsr.l	_060LSP_TOP_+0x48 # branch to "cmp2" routine
+	mov.w	%cc,_tmp	# save off condition codes
+	addq.l	&0x8,%sp	# clear arguments from stack
+
+Exception reporting:
+--------------------
+If the instruction being emulated is a divide and the source
+operand is a zero, then the library routine, as its last
+instruction, executes an implemented divide using a zero
+source operand so that an "Integer Divide-by-Zero" exception
+will be taken. Although the exception stack frame will not
+point to the correct instruction, the user will at least be able
+to record that such an event occurred if desired.
+
+68060ILSP entry points:
+-----------------------
+_060ILSP_TOP:
+0x000:	_060LSP__idivs64_
+0x008:	_060LSP__idivu64_
+
+0x010:	_060LSP__imuls64_
+0x018:	_060LSP__imulu64_
+
+0x020:	_060LSP__cmp2_Ab_
+0x028:	_060LSP__cmp2_Aw_
+0x030:	_060LSP__cmp2_Al_
+0x038:	_060LSP__cmp2_Db_
+0x040:	_060LSP__cmp2_Dw_
+0x048:	_060LSP__cmp2_Dl_
--- a/arch/m68k/ifpsp060/ilsp.sa
+++ b/arch/m68k/ifpsp060/ilsp.sa
@ -0,0 +1,101 @@
+	dc.l	$60ff0000,$01fe0000,$60ff0000,$02080000
+	dc.l	$60ff0000,$04900000,$60ff0000,$04080000
+	dc.l	$60ff0000,$051e0000,$60ff0000,$053c0000
+	dc.l	$60ff0000,$055a0000,$60ff0000,$05740000
+	dc.l	$60ff0000,$05940000,$60ff0000,$05b40000
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$51fc51fc,$51fc51fc,$51fc51fc,$51fc51fc
+	dc.l	$4e56fff0,$48e73f00,$42eefff0,$50eeffff
+	dc.l	$60104e56,$fff048e7,$3f0042ee,$fff051ee
+	dc.l	$ffff2e2e,$00086700,$00ae2a2e,$000c2c2e
+	dc.l	$00104a2e,$ffff671a,$4a875dee,$fffe6a02
+	dc.l	$44874a85,$5deefffd,$6a0844fc,$00004086
+	dc.l	$40854a85,$66164a86,$67000046,$be866306
+	dc.l	$cb466000,$00124c47,$6005600a,$be85634c
+	dc.l	$61ff0000,$00864a2e,$ffff6724,$4a2efffd
+	dc.l	$67024485,$102efffe,$b12efffd,$670c0c86
+	dc.l	$80000000,$62264486,$60060806,$001f661c
+	dc.l	$026e0010,$fff044ee,$fff04a86,$48f60060
+	dc.l	$01610014,$4cdf00fc,$4e5e4e75,$2a2e000c
+	dc.l	$2c2e0010,$026e001c,$fff0006e,$0002fff0
+	dc.l	$44eefff0,$60d62dae,$000c0161,$00142dae
+	dc.l	$00100162,$00140004,$44eefff0,$4cdf00fc
+	dc.l	$4e5e80fc,$00004e75,$0c870000,$ffff621e
+	dc.l	$42814845,$48463a06,$8ac73205,$48463a06
+	dc.l	$8ac74841,$32054245,$48452c01,$4e7542ae
+	dc.l	$fff8422e,$fffc4281,$0807001f,$660e52ae
+	dc.l	$fff8e38f,$e38ee395,$6000ffee,$26072405
+	dc.l	$48424843,$b4436606,$323cffff,$600a2205
+	dc.l	$82c30281,$0000ffff,$2f064246,$48462607
+	dc.l	$2401c4c7,$4843c6c1,$28059883,$48443004
+	dc.l	$38064a40,$6600000a,$b4846304,$538160de
+	dc.l	$2f052c01,$48462a07,$61ff0000,$006a2405
+	dc.l	$26062a1f,$2c1f9c83,$9b8264ff,$0000001a
+	dc.l	$53814282,$26074843,$4243dc83,$db822607
+	dc.l	$42434843,$da834a2e,$fffc6616,$3d41fff4
+	dc.l	$42814845,$48463a06,$424650ee,$fffc6000
+	dc.l	$ff6c3d41,$fff63c05,$48464845,$2e2efff8
+	dc.l	$670a5387,$e28de296,$51cffffa,$2a062c2e
+	dc.l	$fff44e75,$24062606,$28054843,$4844ccc5
+	dc.l	$cac3c4c4,$c6c44284,$4846dc45,$d744dc42
+	dc.l	$d7444846,$42454242,$48454842,$da82da83
+	dc.l	$4e754e56,$fffc48e7,$380042ee,$fffc202e
+	dc.l	$00086700,$005a222e,$000c6700,$00522400
+	dc.l	$26002801,$48434844,$c0c1c2c3,$c4c4c6c4
+	dc.l	$42844840,$d041d784,$d042d784,$48404241
+	dc.l	$42424841,$4842d282,$d283382e,$fffc0204
+	dc.l	$00104a81,$6a040004,$000844c4,$c34048f6
+	dc.l	$00030161,$00104cdf,$001c4e5e,$4e754280
+	dc.l	$4281382e,$fffc0204,$00100004,$000444c4
+	dc.l	$60da4e56,$fffc48e7,$3c0042ee,$fffc202e
+	dc.l	$000867da,$222e000c,$67d44205,$4a806c06
+	dc.l	$44800005,$00014a81,$6c064481,$0a050001
+	dc.l	$24002600,$28014843,$4844c0c1,$c2c3c4c4
+	dc.l	$c6c44284,$4840d041,$d784d042,$d7844840
+	dc.l	$42414242,$48414842,$d282d283,$4a056708
+	dc.l	$46804681,$5280d384,$382efffc,$02040010
+	dc.l	$4a816a04,$00040008,$44c4c340,$48f60003
+	dc.l	$01610010,$4cdf003c,$4e5e4e75,$42804281
+	dc.l	$382efffc,$02040010,$00040004,$44c460da
+	dc.l	$4e56fffc,$48e73800,$42eefffc,$242e0008
+	dc.l	$10360161,$000c1236,$0162000c,$000149c0
+	dc.l	$49c16000,$00b84e56,$fffc48e7,$380042ee
+	dc.l	$fffc242e,$00083036,$0161000c,$32360162
+	dc.l	$000c0002,$48c048c1,$60000092,$4e56fffc
+	dc.l	$48e73800,$42eefffc,$242e0008,$20360161
+	dc.l	$000c2236,$0162000c,$00046000,$00704e56
+	dc.l	$fffc48e7,$380042ee,$fffc242e,$00081036
+	dc.l	$0161000c,$12360162,$000c0001,$49c049c1
+	dc.l	$49c26000,$00484e56,$fffc48e7,$380042ee
+	dc.l	$fffc242e,$00083036,$0161000c,$32360162
+	dc.l	$000c0002,$48c048c1,$48c26000,$00204e56
+	dc.l	$fffc48e7,$380042ee,$fffc242e,$00082036
+	dc.l	$0161000c,$22360162,$000c0004,$948042c3
+	dc.l	$02030004,$9280b282,$42c48604,$02030005
+	dc.l	$382efffc,$0204001a,$880344c4,$4cdf001c
+	dc.l	$4e5e4e75,$00000000,$00000000,$00000000
--- a/arch/m68k/ifpsp060/iskeleton.S
+++ b/arch/m68k/ifpsp060/iskeleton.S
@ -0,0 +1,347 @@
+|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+|M68000 Hi-Performance Microprocessor Division
+|M68060 Software Package
+|Production Release P1.00 -- October 10, 1994
+|
+|M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+|
+|THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+|To the maximum extent permitted by applicable law,
+|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+|and any warranty against infringement with regard to the SOFTWARE
+|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+|
+|To the maximum extent permitted by applicable law,
+|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+|
+|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+|so long as this entire notice is retained without alteration in any modified and/or
+|redistributed versions, and that such modified versions are clearly identified as such.
+|No licenses are granted by implication, estoppel or otherwise under any patents
+|or trademarks of Motorola, Inc.
+|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+| iskeleton.s
+|
+| This file contains:
+|	(1) example "Call-out"s
+|	(2) example package entry code
+|	(3) example "Call-out" table
+|
+
+#include <linux/linkage.h>
+#include <asm/entry.h>
+#include <asm/asm-offsets.h>
+
+
+|################################
+| (1) EXAMPLE CALL-OUTS		#
+|				#
+| _060_isp_done()		#
+| _060_real_chk()		#
+| _060_real_divbyzero()		#
+|				#
+| _060_real_cas()		#
+| _060_real_cas2()		#
+| _060_real_lock_page()		#
+| _060_real_unlock_page()	#
+|################################
+
+|
+| _060_isp_done():
+|
+| This is and example main exit point for the Unimplemented Integer
+| Instruction exception handler. For a normal exit, the
+| _isp_unimp() branches to here so that the operating system
+| can do any clean-up desired. The stack frame is the
+| Unimplemented Integer Instruction stack frame with
+| the PC pointing to the instruction following the instruction
+| just emulated.
+| To simply continue execution at the next instruction, just
+| do an "rte".
+|
+| Linux/68k: If returning to user space, check for needed reselections.
+
+	.global		_060_isp_done
+_060_isp_done:
+	btst	#0x5,%sp@		| supervisor bit set in saved SR?
+	beq	.Lnotkern
+	rte
+.Lnotkern:
+	SAVE_ALL_INT
+	GET_CURRENT(%d0)
+	| deliver signals, reschedule etc..
+	jra	ret_from_exception
+
+|
+| _060_real_chk():
+|
+| This is an alternate exit point for the Unimplemented Integer
+| Instruction exception handler. If the instruction was a "chk2"
+| and the operand was out of bounds, then _isp_unimp() creates
+| a CHK exception stack frame from the Unimplemented Integer Instrcution
+| stack frame and branches to this routine.
+|
+| Linux/68k: commented out test for tracing
+
+	.global		_060_real_chk
+_060_real_chk:
+|	tst.b		(%sp)			| is tracing enabled?
+|	bpls		real_chk_end		| no
+
+|
+|	    CHK FRAME		   TRACE FRAME
+|	*****************	*****************
+|	*   Current PC	*	*   Current PC	*
+|	*****************	*****************
+|	* 0x2 *  0x018	*	* 0x2 *  0x024	*
+|	*****************	*****************
+|	*     Next	*	*     Next	*
+|	*      PC	*	*      PC	*
+|	*****************	*****************
+|	*      SR	*	*      SR	*
+|	*****************	*****************
+|
+|	move.b		#0x24,0x7(%sp)		| set trace vecno
+|	bral		_060_real_trace
+
+real_chk_end:
+	bral		trap			| jump to trap handler
+
+|
+| _060_real_divbyzero:
+|
+| This is an alternate exit point for the Unimplemented Integer
+| Instruction exception handler isp_unimp(). If the instruction is a 64-bit
+| integer divide where the source operand is a zero, then the _isp_unimp()
+| creates a Divide-by-zero exception stack frame from the Unimplemented
+| Integer Instruction stack frame and branches to this routine.
+|
+| Remember that a trace exception may be pending. The code below performs
+| no action associated with the "chk" exception. If tracing is enabled,
+| then it create a Trace exception stack frame from the "chk" exception
+| stack frame and branches to the _real_trace() entry point.
+|
+| Linux/68k: commented out test for tracing
+
+	.global		_060_real_divbyzero
+_060_real_divbyzero:
+|	tst.b		(%sp)			| is tracing enabled?
+|	bpls		real_divbyzero_end	| no
+
+|
+|	 DIVBYZERO FRAME	   TRACE FRAME
+|	*****************	*****************
+|	*   Current PC	*	*   Current PC	*
+|	*****************	*****************
+|	* 0x2 *  0x014	*	* 0x2 *  0x024	*
+|	*****************	*****************
+|	*     Next	*	*     Next	*
+|	*      PC	*	*      PC	*
+|	*****************	*****************
+|	*      SR	*	*      SR	*
+|	*****************	*****************
+|
+|	move.b		#0x24,0x7(%sp)		| set trace vecno
+|	bral		_060_real_trace
+
+real_divbyzero_end:
+	bral		trap			| jump to trap handler
+
+|##########################
+
+|
+| _060_real_cas():
+|
+| Entry point for the selected cas emulation code implementation.
+| If the implementation provided by the 68060ISP is sufficient,
+| then this routine simply re-enters the package through _isp_cas.
+|
+	.global		_060_real_cas
+_060_real_cas:
+	bral		_I_CALL_TOP+0x80+0x08
+
+|
+| _060_real_cas2():
+|
+| Entry point for the selected cas2 emulation code implementation.
+| If the implementation provided by the 68060ISP is sufficient,
+| then this routine simply re-enters the package through _isp_cas2.
+|
+	.global		_060_real_cas2
+_060_real_cas2:
+	bral		_I_CALL_TOP+0x80+0x10
+
+|
+| _060_lock_page():
+|
+| Entry point for the operating system`s routine to "lock" a page
+| from being paged out. This routine is needed by the cas/cas2
+| algorithms so that no page faults occur within the "core" code
+| region. Note: the routine must lock two pages if the operand
+| spans two pages.
+| NOTE: THE ROUTINE SHOULD RETURN AN FSLW VALUE IN D0 ON FAILURE
+| SO THAT THE 060SP CAN CREATE A PROPER ACCESS ERROR FRAME.
+| Arguments:
+|	a0 = operand address
+|	d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user
+|	d1 = `xxxxxxff -> longword; `xxxxxx00 -> word
+| Expected outputs:
+|	d0 = 0 -> success; non-zero -> failure
+|
+| Linux/m68k: Make sure the page is properly paged in, so we use
+| plpaw and handle any exception here. The kernel must not be
+| preempted until _060_unlock_page(), so that the page stays mapped.
+|
+	.global		_060_real_lock_page
+_060_real_lock_page:
+	move.l	%d2,-(%sp)
+	| load sfc/dfc
+	tst.b	%d0
+	jne	1f
+	moveq	#1,%d0
+	jra	2f
+1:	moveq	#5,%d0
+2:	movec.l	%dfc,%d2
+	movec.l	%d0,%dfc
+	movec.l	%d0,%sfc
+
+	clr.l	%d0
+	| prefetch address
+	.chip	68060
+	move.l	%a0,%a1
+1:	plpaw	(%a1)
+	addq.w	#1,%a0
+	tst.b	%d1
+	jeq	2f
+	addq.w	#2,%a0
+2:	plpaw	(%a0)
+3:	.chip	68k
+
+	| restore sfc/dfc
+	movec.l	%d2,%dfc
+	movec.l	%d2,%sfc
+	move.l	(%sp)+,%d2
+	rts
+
+.section __ex_table,"a"
+	.align	4
+	.long	1b,11f
+	.long	2b,21f
+.previous
+.section .fixup,"ax"
+	.even
+11:	move.l	#0x020003c0,%d0
+	or.l	%d2,%d0
+	swap	%d0
+	jra	3b
+21:	move.l	#0x02000bc0,%d0
+	or.l	%d2,%d0
+	swap	%d0
+	jra	3b
+.previous
+
+|
+| _060_unlock_page():
+|
+| Entry point for the operating system`s routine to "unlock" a
+| page that has been "locked" previously with _real_lock_page.
+| Note: the routine must unlock two pages if the operand spans
+| two pages.
+| Arguments:
+|	a0 = operand address
+|	d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user
+|	d1 = `xxxxxxff -> longword; `xxxxxx00 -> word
+|
+| Linux/m68k: perhaps reenable preemption here...
+
+	.global		_060_real_unlock_page
+_060_real_unlock_page:
+	clr.l		%d0
+	rts
+
+|###########################################################################
+
+|#################################
+| (2) EXAMPLE PACKAGE ENTRY CODE #
+|#################################
+
+	.global		_060_isp_unimp
+_060_isp_unimp:
+	bral		_I_CALL_TOP+0x80+0x00
+
+	.global		_060_isp_cas
+_060_isp_cas:
+	bral		_I_CALL_TOP+0x80+0x08
+
+	.global		_060_isp_cas2
+_060_isp_cas2:
+	bral		_I_CALL_TOP+0x80+0x10
+
+	.global		_060_isp_cas_finish
+_060_isp_cas_finish:
+	bra.l		_I_CALL_TOP+0x80+0x18
+
+	.global		_060_isp_cas2_finish
+_060_isp_cas2_finish:
+	bral		_I_CALL_TOP+0x80+0x20
+
+	.global		_060_isp_cas_inrange
+_060_isp_cas_inrange:
+	bral		_I_CALL_TOP+0x80+0x28
+
+	.global		_060_isp_cas_terminate
+_060_isp_cas_terminate:
+	bral		_I_CALL_TOP+0x80+0x30
+
+	.global		_060_isp_cas_restart
+_060_isp_cas_restart:
+	bral		_I_CALL_TOP+0x80+0x38
+
+|###########################################################################
+
+|###############################
+| (3) EXAMPLE CALL-OUT SECTION #
+|###############################
+
+| The size of this section MUST be 128 bytes!!!
+
+_I_CALL_TOP:
+	.long	_060_real_chk		- _I_CALL_TOP
+	.long	_060_real_divbyzero	- _I_CALL_TOP
+	.long	_060_real_trace		- _I_CALL_TOP
+	.long	_060_real_access	- _I_CALL_TOP
+	.long	_060_isp_done		- _I_CALL_TOP
+
+	.long	_060_real_cas		- _I_CALL_TOP
+	.long	_060_real_cas2		- _I_CALL_TOP
+	.long	_060_real_lock_page	- _I_CALL_TOP
+	.long	_060_real_unlock_page	- _I_CALL_TOP
+
+	.long	0x00000000, 0x00000000, 0x00000000, 0x00000000
+	.long	0x00000000, 0x00000000, 0x00000000
+
+	.long	_060_imem_read		- _I_CALL_TOP
+	.long	_060_dmem_read		- _I_CALL_TOP
+	.long	_060_dmem_write		- _I_CALL_TOP
+	.long	_060_imem_read_word	- _I_CALL_TOP
+	.long	_060_imem_read_long	- _I_CALL_TOP
+	.long	_060_dmem_read_byte	- _I_CALL_TOP
+	.long	_060_dmem_read_word	- _I_CALL_TOP
+	.long	_060_dmem_read_long	- _I_CALL_TOP
+	.long	_060_dmem_write_byte	- _I_CALL_TOP
+	.long	_060_dmem_write_word	- _I_CALL_TOP
+	.long	_060_dmem_write_long	- _I_CALL_TOP
+
+	.long	0x00000000
+	.long	0x00000000, 0x00000000, 0x00000000, 0x00000000
+
+|###########################################################################
+
+| 060 INTEGER KERNEL PACKAGE MUST GO HERE!!!
+#include "isp.sa"
--- a/arch/m68k/ifpsp060/isp.doc
+++ b/arch/m68k/ifpsp060/isp.doc
@ -0,0 +1,218 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+68060 INTEGER SOFTWARE PACKAGE (Kernel version)
+------------------------------------------------
+
+The file isp.sa contains the 68060 Integer Software Package.
+This package is essentially an exception handler that can be
+integrated into an operating system to handle the "Unimplemented
+Integer Instruction" exception vector #61.
+This exception is taken when any of the integer instructions
+not hardware implemented on the 68060 are encountered. The
+isp.sa provides full emulation support for these instructions.
+
+The unimplemented integer instructions are:
+	64-bit divide
+	64-bit multiply
+	movep
+	cmp2
+	chk2
+	cas (w/ a misaligned effective address)
+	cas2
+
+Release file format:
+--------------------
+The file isp.sa is essentially a hexadecimal image of the
+release package. This is the ONLY format which will be supported.
+The hex image was created by assembling the source code and
+then converting the resulting binary output image into an
+ASCII text file. The hexadecimal numbers are listed
+using the Motorola Assembly Syntax assembler directive "dc.l"
+(define constant longword). The file can be converted to other
+assembly syntaxes by using any word processor with a global
+search and replace function.
+
+To assist in assembling and linking this module with other modules,
+the installer should add a symbolic label to the top of the file.
+This will allow calling routines to access the entry points
+of this package.
+
+The source code isp.s has also been included but only for
+documentation purposes.
+
+Release file structure:
+-----------------------
+
+(top of module)
+	-----------------
+	|		| - 128 byte-sized section
+   (1)  |   Call-Out    | - 4 bytes per entry (user fills these in)
+	|		| - example routines in iskeleton.s
+	-----------------
+	|		| - 8 bytes per entry
+   (2)  | Entry Point   | - user does a "bra" or "jmp" to this address
+	|               |
+	-----------------
+	|		| - code section
+   (3)  ~		~
+	|		|
+	-----------------
+(bottom of module)
+
+The first section of this module is the "Call-out" section. This section
+is NOT INCLUDED in isp.sa (an example "Call-out" section is provided at
+the end of the file iskeleton.s). The purpose of this section is to allow
+the ISP routines to reference external functions that must be provided
+by the host operating system. This section MUST be exactly 128 bytes in
+size. There are 32 fields, each 4 bytes in size. Each field corresponds
+to a function required by the ISP (these functions and their location are
+listed in "68060ISP call-outs" below). Each field entry should contain
+the address of the corresponding function RELATIVE to the starting address
+of the "call-out" section. The "Call-out" section must sit adjacent to the
+isp.sa image in memory.
+
+The second section, the "Entry-point" section, is used by external routines
+to access the functions within the ISP. Since the isp.sa hex file contains
+no symbol names, this section contains function entry points that are fixed
+with respect to the top of the package. The currently defined entry-points
+are listed in section "68060 ISP entry points" below. A calling routine
+would simply execute a "bra" or "jmp" that jumped to the selected function
+entry-point.
+
+For example, if the 68060 hardware took a "Unimplemented Integer Instruction"
+exception (vector #61), the operating system should execute something
+similar to:
+
+	bra	_060ISP_TOP+128+0
+
+(_060ISP_TOP is the starting address of the "Call-out" section; the "Call-out"
+section is 128 bytes long; and the Unimplemented Integer ISP handler entry
+point is located 0 bytes from the top of the "Entry-point" section.)
+
+The third section is the code section. After entering through an "Entry-point",
+the entry code jumps to the appropriate emulation code within the code section.
+
+68060ISP call-outs: (details in iskeleton.s)
+--------------------
+0x000:	_060_real_chk
+0x004:	_060_real_divbyzero
+0x008:	_060_real_trace
+0x00c:	_060_real_access
+0x010:	_060_isp_done
+
+0x014:	_060_real_cas
+0x018:	_060_real_cas2
+0x01c:	_060_real_lock_page
+0x020:	_060_real_unlock_page
+
+0x024:	(Motorola reserved)
+0x028:	(Motorola reserved)
+0x02c:	(Motorola reserved)
+0x030:	(Motorola reserved)
+0x034:	(Motorola reserved)
+0x038:	(Motorola reserved)
+0x03c:	(Motorola reserved)
+
+0x040:	_060_imem_read
+0x044:	_060_dmem_read
+0x048:	_060_dmem_write
+0x04c:	_060_imem_read_word
+0x050:	_060_imem_read_long
+0x054:	_060_dmem_read_byte
+0x058:	_060_dmem_read_word
+0x05c:	_060_dmem_read_long
+0x060:	_060_dmem_write_byte
+0x064:	_060_dmem_write_word
+0x068:	_060_dmem_write_long
+
+0x06c:	(Motorola reserved)
+0x070:	(Motorola reserved)
+0x074:	(Motorola reserved)
+0x078:	(Motorola reserved)
+0x07c:	(Motorola reserved)
+
+68060ISP entry points:
+-----------------------
+0x000:	_060_isp_unimp
+
+0x008:	_060_isp_cas
+0x010:	_060_isp_cas2
+0x018:	_060_isp_cas_finish
+0x020:	_060_isp_cas2_finish
+0x028:	_060_isp_cas_inrange
+0x030:	_060_isp_cas_terminate
+0x038:	_060_isp_cas_restart
+
+Integrating cas/cas2:
+---------------------
+The instructions "cas2" and "cas" (when used with a misaligned effective
+address) take the Unimplemented Integer Instruction exception. When the
+060ISP is installed properly, these instructions will enter through the
+_060_isp_unimp() entry point of the ISP.
+
+After the 060ISP decodes the instruction type and fetches the appropriate
+data registers, and BEFORE the actual emulated transfers occur, the
+package calls either the "Call-out" _060_real_cas() or _060_real_cas2().
+If the emulation code provided by the 060ISP is sufficient for the
+host system (see isp.s source code), then these "Call-out"s should be
+made, by the system integrator, to point directly back into the package
+through the "Entry-point"s _060_isp_cas() or _060_isp_cas2().
+
+One other necessary action by the integrator is to supply the routines
+_060_real_lock_page() and _060_real_unlock_page(). These functions are
+defined further in iskeleton.s and the 68060 Software Package Specification.
+
+If the "core" emulation routines of either "cas" or "cas2" perform some
+actions which are too system-specific, then the system integrator must
+supply new emulation code. This new emulation code should reside within
+the functions _060_real_cas() or _060_real_cas2(). When this new emulation
+code has completed, then it should re-enter the 060ISP package through the
+"Entry-point" _060_isp_cas_finish() or _060_isp_cas2_finish().
+To see what the register state is upon entering _060_real_cas() or
+_060_real_cas2() and what it should be upon return to the package through
+_060_isp_cas_finish() or _060_isp_cas2_finish(), please refer to the
+source code in isp.s.
+
+Miscellaneous:
+--------------
+
+_060_isp_unimp:
+----------------
+- documented in 2.2 in spec.
+- Basic flow:
+	exception taken ---> enter _060_isp_unimp   --|
+						      |
+						      |
+            may exit through _060_real_itrace    <----|
+						  or  |
+            may exit through _060_real_chk       <----|
+						  or  |
+            may exit through _060_real_divbyzero <----|
+						  or  |
+            may exit through _060_isp_done       <----|
--- a/arch/m68k/ifpsp060/isp.sa
+++ b/arch/m68k/ifpsp060/isp.sa
@ -0,0 +1,392 @@
+	.long	0x60ff0000,0x02360000,0x60ff0000,0x16260000
+	.long	0x60ff0000,0x12dc0000,0x60ff0000,0x11ea0000
+	.long	0x60ff0000,0x10de0000,0x60ff0000,0x12a40000
+	.long	0x60ff0000,0x12560000,0x60ff0000,0x122a0000
+	.long	0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
+	.long	0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
+	.long	0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
+	.long	0x51fc51fc,0x51fc51fc,0x51fc51fc,0x51fc51fc
+	.long	0x2f00203a,0xfefc487b,0x0930ffff,0xfef8202f
+	.long	0x00044e74,0x00042f00,0x203afeea,0x487b0930
+	.long	0xfffffee2,0x202f0004,0x4e740004,0x2f00203a
+	.long	0xfed8487b,0x0930ffff,0xfecc202f,0x00044e74
+	.long	0x00042f00,0x203afec6,0x487b0930,0xfffffeb6
+	.long	0x202f0004,0x4e740004,0x2f00203a,0xfeb4487b
+	.long	0x0930ffff,0xfea0202f,0x00044e74,0x00042f00
+	.long	0x203afea2,0x487b0930,0xfffffe8a,0x202f0004
+	.long	0x4e740004,0x2f00203a,0xfe90487b,0x0930ffff
+	.long	0xfe74202f,0x00044e74,0x00042f00,0x203afe7e
+	.long	0x487b0930,0xfffffe5e,0x202f0004,0x4e740004
+	.long	0x2f00203a,0xfe6c487b,0x0930ffff,0xfe48202f
+	.long	0x00044e74,0x00042f00,0x203afe76,0x487b0930
+	.long	0xfffffe32,0x202f0004,0x4e740004,0x2f00203a
+	.long	0xfe64487b,0x0930ffff,0xfe1c202f,0x00044e74
+	.long	0x00042f00,0x203afe52,0x487b0930,0xfffffe06
+	.long	0x202f0004,0x4e740004,0x2f00203a,0xfe40487b
+	.long	0x0930ffff,0xfdf0202f,0x00044e74,0x00042f00
+	.long	0x203afe2e,0x487b0930,0xfffffdda,0x202f0004
+	.long	0x4e740004,0x2f00203a,0xfe1c487b,0x0930ffff
+	.long	0xfdc4202f,0x00044e74,0x00042f00,0x203afe0a
+	.long	0x487b0930,0xfffffdae,0x202f0004,0x4e740004
+	.long	0x2f00203a,0xfdf8487b,0x0930ffff,0xfd98202f
+	.long	0x00044e74,0x00042f00,0x203afde6,0x487b0930
+	.long	0xfffffd82,0x202f0004,0x4e740004,0x2f00203a
+	.long	0xfdd4487b,0x0930ffff,0xfd6c202f,0x00044e74
+	.long	0x00042f00,0x203afdc2,0x487b0930,0xfffffd56
+	.long	0x202f0004,0x4e740004,0x4e56ffa0,0x48ee3fff
+	.long	0xffc02d56,0xfff8082e,0x00050004,0x66084e68
+	.long	0x2d48fffc,0x600841ee,0x000c2d48,0xfffc422e
+	.long	0xffaa3d6e,0x0004ffa8,0x2d6e0006,0xffa4206e
+	.long	0xffa458ae,0xffa461ff,0xffffff26,0x2d40ffa0
+	.long	0x0800001e,0x67680800,0x00166628,0x61ff0000
+	.long	0x0cb0082e,0x00050004,0x670000ac,0x082e0002
+	.long	0xffaa6700,0x00a2082e,0x00070004,0x66000186
+	.long	0x600001b0,0x61ff0000,0x0a28082e,0x0002ffaa
+	.long	0x660e082e,0x0005ffaa,0x6600010a,0x60000078
+	.long	0x082e0005,0x000467ea,0x082e0005,0xffaa6600
+	.long	0x01264a2e,0x00046b00,0x014c6000,0x01760800
+	.long	0x0018670a,0x61ff0000,0x07ae6000,0x004a0800
+	.long	0x001b6730,0x48400c00,0x00fc670a,0x61ff0000
+	.long	0x0e926000,0x0032206e,0xffa454ae,0xffa461ff
+	.long	0xfffffe68,0x4a816600,0x019861ff,0x00000d20
+	.long	0x60000014,0x61ff0000,0x08c40c2e,0x0010ffaa
+	.long	0x66000004,0x605c1d6e,0xffa90005,0x082e0005
+	.long	0x00046606,0x206efffc,0x4e604cee,0x3fffffc0
+	.long	0x082e0007,0x00046612,0x2d6effa4,0x00062cae
+	.long	0xfff84e5e,0x60ffffff,0xfd622d6e,0xfff8fffc
+	.long	0x3d6e0004,0x00002d6e,0x00060008,0x2d6effa4
+	.long	0x00023d7c,0x20240006,0x598e4e5e,0x60ffffff
+	.long	0xfd0e1d6e,0xffa90005,0x4cee3fff,0xffc03cae
+	.long	0x00042d6e,0x00060008,0x2d6effa4,0x00023d7c
+	.long	0x20180006,0x2c6efff8,0xdffc0000,0x006060ff
+	.long	0xfffffcb0,0x1d6effa9,0x00054cee,0x3fffffc0
+	.long	0x3cae0004,0x2d6e0006,0x00082d6e,0xffa40002
+	.long	0x3d7c2014,0x00062c6e,0xfff8dffc,0x00000060
+	.long	0x60ffffff,0xfc941d6e,0xffa90005,0x4cee3fff
+	.long	0xffc02d6e,0x0006000c,0x3d7c2014,0x000a2d6e
+	.long	0xffa40006,0x2c6efff8,0xdffc0000,0x006460ff
+	.long	0xfffffc66,0x1d6effa9,0x00054cee,0x3fffffc0
+	.long	0x2d6e0006,0x000c3d7c,0x2024000a,0x2d6effa4
+	.long	0x00062c6e,0xfff8dffc,0x00000064,0x60ffffff
+	.long	0xfc4e1d6e,0xffa90005,0x4cee3fff,0xffc03d7c
+	.long	0x00f4000e,0x2d6effa4,0x000a3d6e,0x00040008
+	.long	0x2c6efff8,0xdffc0000,0x006860ff,0xfffffc4c
+	.long	0x2c882d40,0xfffc4fee,0xffc04cdf,0x7fff2f2f
+	.long	0x000c2f6f,0x00040010,0x2f6f000c,0x00042f6f
+	.long	0x0008000c,0x2f5f0004,0x3f7c4008,0x00066028
+	.long	0x4cee3fff,0xffc04e5e,0x514f2eaf,0x00083f6f
+	.long	0x000c0004,0x3f7c4008,0x00062f6f,0x00020008
+	.long	0x2f7c0942,0x8001000c,0x08170005,0x670608ef
+	.long	0x0002000d,0x60ffffff,0xfbcc0c2e,0x0040ffaa
+	.long	0x660c4280,0x102effab,0x2daeffac,0x0ce04e75
+	.long	0x2040302e,0xffa03200,0x0240003f,0x02810000
+	.long	0x0007303b,0x020a4efb,0x00064afc,0x00400000
+	.long	0x00000000,0x00000000,0x00000000,0x00000000
+	.long	0x00000000,0x00000000,0x00000000,0x00000080
+	.long	0x0086008c,0x00920098,0x009e00a4,0x00aa00b0
+	.long	0x00ce00ec,0x010a0128,0x01460164,0x01820196
+	.long	0x01b401d2,0x01f0020e,0x022c024a,0x0268027c
+	.long	0x029a02b8,0x02d602f4,0x03120330,0x034e036c
+	.long	0x036c036c,0x036c036c,0x036c036c,0x036c03d6
+	.long	0x03f0040a,0x042a03ca,0x00000000,0x0000206e
+	.long	0xffe04e75,0x206effe4,0x4e75206e,0xffe84e75
+	.long	0x206effec,0x4e75206e,0xfff04e75,0x206efff4
+	.long	0x4e75206e,0xfff84e75,0x206efffc,0x4e752008
+	.long	0x206effe0,0xd0882d40,0xffe02d48,0xffac1d7c
+	.long	0x0000ffab,0x1d7c0040,0xffaa4e75,0x2008206e
+	.long	0xffe4d088,0x2d40ffe4,0x2d48ffac,0x1d7c0001
+	.long	0xffab1d7c,0x0040ffaa,0x4e752008,0x206effe8
+	.long	0xd0882d40,0xffe82d48,0xffac1d7c,0x0002ffab
+	.long	0x1d7c0040,0xffaa4e75,0x2008206e,0xffecd088
+	.long	0x2d40ffec,0x2d48ffac,0x1d7c0003,0xffab1d7c
+	.long	0x0040ffaa,0x4e752008,0x206efff0,0xd0882d40
+	.long	0xfff02d48,0xffac1d7c,0x0004ffab,0x1d7c0040
+	.long	0xffaa4e75,0x2008206e,0xfff4d088,0x2d40fff4
+	.long	0x2d48ffac,0x1d7c0005,0xffab1d7c,0x0040ffaa
+	.long	0x4e752008,0x206efff8,0xd0882d40,0xfff82d48
+	.long	0xffac1d7c,0x0006ffab,0x1d7c0040,0xffaa4e75
+	.long	0x1d7c0004,0xffaa2008,0x206efffc,0xd0882d40
+	.long	0xfffc4e75,0x202effe0,0x2d40ffac,0x90882d40
+	.long	0xffe02040,0x1d7c0000,0xffab1d7c,0x0040ffaa
+	.long	0x4e75202e,0xffe42d40,0xffac9088,0x2d40ffe4
+	.long	0x20401d7c,0x0001ffab,0x1d7c0040,0xffaa4e75
+	.long	0x202effe8,0x2d40ffac,0x90882d40,0xffe82040
+	.long	0x1d7c0002,0xffab1d7c,0x0040ffaa,0x4e75202e
+	.long	0xffec2d40,0xffac9088,0x2d40ffec,0x20401d7c
+	.long	0x0003ffab,0x1d7c0040,0xffaa4e75,0x202efff0
+	.long	0x2d40ffac,0x90882d40,0xfff02040,0x1d7c0004
+	.long	0xffab1d7c,0x0040ffaa,0x4e75202e,0xfff42d40
+	.long	0xffac9088,0x2d40fff4,0x20401d7c,0x0005ffab
+	.long	0x1d7c0040,0xffaa4e75,0x202efff8,0x2d40ffac
+	.long	0x90882d40,0xfff82040,0x1d7c0006,0xffab1d7c
+	.long	0x0040ffaa,0x4e751d7c,0x0008ffaa,0x202efffc
+	.long	0x90882d40,0xfffc2040,0x4e75206e,0xffa454ae
+	.long	0xffa461ff,0xfffff9d4,0x4a8166ff,0xfffffd04
+	.long	0x3040d1ee,0xffe04e75,0x206effa4,0x54aeffa4
+	.long	0x61ffffff,0xf9b64a81,0x66ffffff,0xfce63040
+	.long	0xd1eeffe4,0x4e75206e,0xffa454ae,0xffa461ff
+	.long	0xfffff998,0x4a8166ff,0xfffffcc8,0x3040d1ee
+	.long	0xffe84e75,0x206effa4,0x54aeffa4,0x61ffffff
+	.long	0xf97a4a81,0x66ffffff,0xfcaa3040,0xd1eeffec
+	.long	0x4e75206e,0xffa454ae,0xffa461ff,0xfffff95c
+	.long	0x4a8166ff,0xfffffc8c,0x3040d1ee,0xfff04e75
+	.long	0x206effa4,0x54aeffa4,0x61ffffff,0xf93e4a81
+	.long	0x66ffffff,0xfc6e3040,0xd1eefff4,0x4e75206e
+	.long	0xffa454ae,0xffa461ff,0xfffff920,0x4a8166ff
+	.long	0xfffffc50,0x3040d1ee,0xfff84e75,0x206effa4
+	.long	0x54aeffa4,0x61ffffff,0xf9024a81,0x66ffffff
+	.long	0xfc323040,0xd1eefffc,0x4e752f01,0x206effa4
+	.long	0x54aeffa4,0x61ffffff,0xf8e24a81,0x66ffffff
+	.long	0xfc12221f,0x207614e0,0x08000008,0x670e48e7
+	.long	0x3c002a00,0x260860ff,0x000000ec,0x2f022200
+	.long	0xe9590241,0x000f2236,0x14c00800,0x000b6602
+	.long	0x48c12400,0xef5a0282,0x00000003,0xe5a949c0
+	.long	0xd081d1c0,0x241f4e75,0x1d7c0080,0xffaa206e
+	.long	0xffa44e75,0x206effa4,0x54aeffa4,0x61ffffff
+	.long	0xf87a4a81,0x66ffffff,0xfbaa3040,0x4e75206e
+	.long	0xffa458ae,0xffa461ff,0xfffff876,0x4a8166ff
+	.long	0xfffffb90,0x20404e75,0x206effa4,0x54aeffa4
+	.long	0x61ffffff,0xf8464a81,0x66ffffff,0xfb763040
+	.long	0xd1eeffa4,0x55884e75,0x206effa4,0x54aeffa4
+	.long	0x61ffffff,0xf8264a81,0x66ffffff,0xfb56206e
+	.long	0xffa45588,0x08000008,0x670e48e7,0x3c002a00
+	.long	0x260860ff,0x00000030,0x2f022200,0xe9590241
+	.long	0x000f2236,0x14c00800,0x000b6602,0x48c12400
+	.long	0xef5a0282,0x00000003,0xe5a949c0,0xd081d1c0
+	.long	0x241f4e75,0x08050006,0x67044282,0x6016e9c5
+	.long	0x24042436,0x24c00805,0x000b6602,0x48c2e9c5
+	.long	0x0542e1aa,0x08050007,0x67024283,0xe9c50682
+	.long	0x0c000002,0x6d346718,0x206effa4,0x58aeffa4
+	.long	0x61ffffff,0xf7ac4a81,0x66ffffff,0xfac66018
+	.long	0x206effa4,0x54aeffa4,0x61ffffff,0xf77e4a81
+	.long	0x66ffffff,0xfaae48c0,0xd680e9c5,0x07826700
+	.long	0x006a0c00,0x00026d34,0x6718206e,0xffa458ae
+	.long	0xffa461ff,0xfffff76a,0x4a8166ff,0xfffffa84
+	.long	0x601c206e,0xffa454ae,0xffa461ff,0xfffff73c
+	.long	0x4a8166ff,0xfffffa6c,0x48c06002,0x42802800
+	.long	0x08050002,0x67122043,0x61ffffff,0xf7764a81
+	.long	0x6624d082,0xd0846016,0xd6822043,0x61ffffff
+	.long	0xf7624a81,0x6610d084,0x6004d682,0x20032040
+	.long	0x4cdf003c,0x4e752043,0x203c0101,0x000160ff
+	.long	0xfffff9f0,0x322effa0,0x10010240,0x00072076
+	.long	0x04e0d0ee,0xffa20801,0x00076700,0x008c3001
+	.long	0xef580240,0x00072036,0x04c00801,0x00066752
+	.long	0x24002448,0xe19a2002,0x61ffffff,0xf71c4a81
+	.long	0x660000fc,0x544a204a,0xe19a2002,0x61ffffff
+	.long	0xf7084a81,0x660000e8,0x544a204a,0xe19a2002
+	.long	0x61ffffff,0xf6f44a81,0x660000d4,0x544a204a
+	.long	0xe19a2002,0x61ffffff,0xf6e04a81,0x660000c0
+	.long	0x4e752400,0x2448e048,0x61ffffff,0xf6cc4a81
+	.long	0x660000ac,0x544a204a,0x200261ff,0xfffff6ba
+	.long	0x4a816600,0x009a4e75,0x08010006,0x675c2448
+	.long	0x61ffffff,0xf6624a81,0x66000092,0x2400544a
+	.long	0x204a61ff,0xfffff650,0x4a816600,0x0080e14a
+	.long	0x1400544a,0x204a61ff,0xfffff63c,0x4a816600
+	.long	0x006ce18a,0x1400544a,0x204a61ff,0xfffff628
+	.long	0x4a816600,0x0058e18a,0x1400122e,0xffa0e209
+	.long	0x02410007,0x2d8214c0,0x4e752448,0x61ffffff
+	.long	0xf6064a81,0x66000036,0x2400544a,0x204a61ff
+	.long	0xfffff5f4,0x4a816600,0x0024e14a,0x1400122e
+	.long	0xffa0e209,0x02410007,0x3d8214c2,0x4e75204a
+	.long	0x203c00a1,0x000160ff,0xfffff8a8,0x204a203c
+	.long	0x01210001,0x60ffffff,0xf89a61ff,0xfffff914
+	.long	0x102effa2,0xe9180240,0x000f2436,0x04c00c2e
+	.long	0x0002ffa0,0x6d506728,0x244861ff,0xfffff5c4
+	.long	0x4a816600,0x009e2600,0x588a204a,0x61ffffff
+	.long	0xf5b24a81,0x6600008c,0x22002003,0x60000048
+	.long	0x244861ff,0xfffff59c,0x4a816600,0x00763200
+	.long	0x484048c0,0x48c1082e,0x0007ffa2,0x66000028
+	.long	0x48c26000,0x00222448,0x61ffffff,0xf5604a81
+	.long	0x6600005e,0x1200e048,0x49c049c1,0x082e0007
+	.long	0xffa26602,0x49c29480,0x42c30203,0x00049280
+	.long	0xb28242c4,0x86040203,0x0005382e,0xffa80204
+	.long	0x001a8803,0x3d44ffa8,0x082e0003,0xffa26602
+	.long	0x4e750804,0x00006602,0x4e751d7c,0x0010ffaa
+	.long	0x4e75204a,0x203c0101,0x000160ff,0xfffff7c4
+	.long	0x204a203c,0x01410001,0x60ffffff,0xf7b6102e
+	.long	0xffa10200,0x00386600,0x0208102e,0xffa10240
+	.long	0x00072e36,0x04c06700,0x00c0102e,0xffa3122e
+	.long	0xffa20240,0x0007e809,0x02410007,0x3d40ffb2
+	.long	0x3d41ffb4,0x2a3604c0,0x2c3614c0,0x082e0003
+	.long	0xffa2671a,0x4a875dee,0xffb06a02,0x44874a85
+	.long	0x5deeffb1,0x6a0844fc,0x00004086,0x40854a85
+	.long	0x66164a86,0x67000048,0xbe866306,0xcb466000
+	.long	0x00124c47,0x6005600a,0xbe85634e,0x61ff0000
+	.long	0x0068082e,0x0003ffa2,0x67244a2e,0xffb16702
+	.long	0x4485102e,0xffb0b12e,0xffb1670c,0x0c868000
+	.long	0x00006226,0x44866006,0x0806001f,0x661c44ee
+	.long	0xffa84a86,0x42eeffa8,0x302effb2,0x322effb4
+	.long	0x2d8504c0,0x2d8614c0,0x4e7508ee,0x0001ffa9
+	.long	0x08ae0000,0xffa94e75,0x022e001e,0xffa9002e
+	.long	0x0020ffaa,0x4e750c87,0x0000ffff,0x621e4281
+	.long	0x48454846,0x3a068ac7,0x32054846,0x3a068ac7
+	.long	0x48413205,0x42454845,0x2c014e75,0x42aeffbc
+	.long	0x422effb6,0x42810807,0x001f660e,0x52aeffbc
+	.long	0xe38fe38e,0xe3956000,0xffee2607,0x24054842
+	.long	0x4843b443,0x6606323c,0xffff600a,0x220582c3
+	.long	0x02810000,0xffff2f06,0x42464846,0x26072401
+	.long	0xc4c74843,0xc6c12805,0x98834844,0x30043806
+	.long	0x4a406600,0x000ab484,0x63045381,0x60de2f05
+	.long	0x2c014846,0x2a0761ff,0x0000006a,0x24052606
+	.long	0x2a1f2c1f,0x9c839b82,0x64ff0000,0x001a5381
+	.long	0x42822607,0x48434243,0xdc83db82,0x26074243
+	.long	0x4843da83,0x4a2effb6,0x66163d41,0xffb84281
+	.long	0x48454846,0x3a064246,0x50eeffb6,0x6000ff6c
+	.long	0x3d41ffba,0x3c054846,0x48452e2e,0xffbc670a
+	.long	0x5387e28d,0xe29651cf,0xfffa2a06,0x2c2effb8
+	.long	0x4e752406,0x26062805,0x48434844,0xccc5cac3
+	.long	0xc4c4c6c4,0x42844846,0xdc45d744,0xdc42d744
+	.long	0x48464245,0x42424845,0x4842da82,0xda834e75
+	.long	0x700461ff,0xfffff61c,0x0c2e0080,0xffaa6712
+	.long	0x244861ff,0xfffff2dc,0x4a81661e,0x2e006000
+	.long	0xfde658ae,0xffa461ff,0xfffff286,0x4a8166ff
+	.long	0xfffff5a0,0x2e006000,0xfdce61ff,0xfffff5ce
+	.long	0x204a203c,0x01010001,0x60ffffff,0xf556102e
+	.long	0xffa10c00,0x00076e00,0x00b40240,0x00072636
+	.long	0x04c0342e,0xffa24241,0x1202e95a,0x02420007
+	.long	0x283624c0,0x4a846700,0x00884a83,0x67000082
+	.long	0x422effb0,0x082e0003,0xffa26718,0x4a836c08
+	.long	0x4483002e,0x0001ffb0,0x4a846c08,0x44840a2e
+	.long	0x0001ffb0,0x2a032c03,0x2e044846,0x4847c6c4
+	.long	0xc8c6cac7,0xccc74287,0x4843d644,0xdd87d645
+	.long	0xdd874843,0x42444245,0x48444845,0xd885d886
+	.long	0x4a2effb0,0x67084683,0x46845283,0xd9872d83
+	.long	0x24c044fc,0x00002d84,0x14c042c7,0x02070008
+	.long	0x1c2effa9,0x02060010,0x8c071d46,0xffa94e75
+	.long	0x42b624c0,0x42b614c0,0x7e0460e4,0x700461ff
+	.long	0xfffff510,0x0c2e0080,0xffaa6714,0x244861ff
+	.long	0xfffff1d0,0x4a816600,0x00202600,0x6000ff34
+	.long	0x58aeffa4,0x61ffffff,0xf1784a81,0x66ffffff
+	.long	0xf4922600,0x6000ff1c,0x61ffffff,0xf4c0204a
+	.long	0x203c0101,0x000160ff,0xfffff448,0x2d40ffb4
+	.long	0x2200e958,0x0240000f,0x227604c0,0x2d49ffb0
+	.long	0x2001ec49,0x02410007,0x2a3614c0,0x02400007
+	.long	0x263604c0,0x3d40ffba,0x302effa2,0x2200e958
+	.long	0x0240000f,0x207604c0,0x2d48ffbc,0x2001ec49
+	.long	0x02410007,0x283614c0,0x02400007,0x243604c0
+	.long	0x3d40ffb8,0x082e0001,0xffa056c7,0x082e0005
+	.long	0x000456c6,0x24482649,0x22072006,0x61ffffff
+	.long	0xf05c204a,0x4a8066ff,0x000001c8,0x22072006
+	.long	0x204b61ff,0xfffff046,0x204b4a80,0x660a204a
+	.long	0x224b60ff,0xfffff020,0x2f002207,0x2006204a
+	.long	0x61ffffff,0xf03e201f,0x204b60ff,0x00000194
+	.long	0x082e0001,0xffa06648,0x44eeffa8,0xb0426602
+	.long	0xb24342ee,0xffa84a04,0x6610362e,0xffba3d81
+	.long	0x34c2342e,0xffb83d80,0x24c2082e,0x00050004
+	.long	0x56c22002,0x51c1206e,0xffbc61ff,0xffffeff4
+	.long	0x200251c1,0x206effb0,0x61ffffff,0xefe64e75
+	.long	0x44eeffa8,0xb0826602,0xb28342ee,0xffa84a04
+	.long	0x6610362e,0xffba2d81,0x34c0342e,0xffb82d80
+	.long	0x24c0082e,0x00050004,0x56c22002,0x50c1206e
+	.long	0xffbc61ff,0xffffefac,0x200250c1,0x206effb0
+	.long	0x61ffffff,0xef9e4e75,0x202effb4,0x6000feae
+	.long	0x082e0001,0xffa06610,0x700261ff,0xfffff364
+	.long	0x2d48ffb4,0x51c7600e,0x700461ff,0xfffff354
+	.long	0x2d48ffb4,0x50c7302e,0xffa22200,0xec480240
+	.long	0x00072436,0x04c00241,0x00072836,0x14c03d41
+	.long	0xffb8082e,0x00050004,0x56c62448,0x22072006
+	.long	0x61ffffff,0xef284a80,0x66000096,0x204a60ff
+	.long	0xffffeeee,0x082e0001,0xffa0662c,0x44eeffa8
+	.long	0xb04442ee,0xffa84a01,0x6608362e,0xffb83d80
+	.long	0x34c2206e,0xffb451c1,0x082e0005,0x000456c0
+	.long	0x61ffffff,0xeefe4e75,0x44eeffa8,0xb08442ee
+	.long	0xffa84a01,0x6608362e,0xffb82d80,0x34c0206e
+	.long	0xffb450c1,0x082e0005,0x000456c0,0x61ffffff
+	.long	0xeed24e75,0x4e7b6000,0x4e7b6001,0x0c2e00fc
+	.long	0xffa167ff,0xffffff24,0x206effb4,0x082e0001
+	.long	0xffa056c7,0x6000ff40,0x4e7b6000,0x4e7b6001
+	.long	0x24482f00,0x61ffffff,0xf264201f,0x588f518f
+	.long	0x518e721a,0x41ef0008,0x43ef0000,0x22d851c9
+	.long	0xfffc3d7c,0x4008000a,0x2d4a000c,0x2d400010
+	.long	0x4cee3fff,0xffc04e5e,0x60ffffff,0xedf84280
+	.long	0x43fb0170,0x000005ae,0xb3c86d0e,0x43fb0170
+	.long	0x00000010,0xb1c96d02,0x4e7570ff,0x4e754a06
+	.long	0x66047001,0x60027005,0x4a076700,0x01e42448
+	.long	0x26492848,0x2a49568c,0x568d220a,0x40c7007c
+	.long	0x07004e7a,0x60004e7b,0x00004e7b,0x0001f58a
+	.long	0xf58cf58b,0xf58df46a,0xf46cf46b,0xf46d2441
+	.long	0x56812841,0xf5caf5cc,0x247c8000,0x0000267c
+	.long	0xa0000000,0x287c0000,0x00002008,0x02000003
+	.long	0x671c0c00,0x00026700,0x00966000,0x010251fc
+	.long	0x4e7ba008,0x0e911000,0x0e900000,0x6002600e
+	.long	0xb082661c,0xb2836618,0x0e915800,0x6002600e
+	.long	0x4e7bb008,0x0e904800,0x4e7bc008,0x6034600e
+	.long	0x4e7bb008,0x0e900800,0x4e7bc008,0x6012600e
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160b0
+	.long	0x4e7b6000,0x4e7b6001,0x46c751c4,0x60ffffff
+	.long	0xfd424e7b,0x60004e7b,0x600146c7,0x50c460ff
+	.long	0xfffffd30,0x51fc51fc,0x51fc51fc,0x51fc51fc
+	.long	0x4e7ba008,0x0e911000,0x0e900000,0x6002600e
+	.long	0xb082662c,0xb2836628,0x0e915800,0x6002600e
+	.long	0x48440e58,0x48004e7b,0xb0084844,0x6002600e
+	.long	0x0e504800,0x4e7bc008,0x6000ffa8,0x4e71600e
+	.long	0x48400e58,0x08004e7b,0xb0084840,0x6002600e
+	.long	0x0e500800,0x4e7bc008,0x6000ff76,0x4e71600e
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090
+	.long	0x4e7ba008,0x0e911000,0x0e900000,0x6002600e
+	.long	0xb082663c,0xb2836638,0x0e915800,0x6002600e
+	.long	0xe19c0e18,0x48004844,0x0e584800,0x6002600e
+	.long	0xe19c4e7b,0xb0080e10,0x48006004,0x4e71600e
+	.long	0x4e7bc008,0x6000ff2c,0x4e714e71,0x4e71600e
+	.long	0xe1980e18,0x08004840,0x0e580800,0x6002600e
+	.long	0xe1984e7b,0xb0080e10,0x08006004,0x4e71600e
+	.long	0x4e7bc008,0x6000feea,0x4e714e71,0x4e71600c
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x6000ff72
+	.long	0x24482649,0x28482a49,0x528c528d,0x220a40c7
+	.long	0x007c0700,0x4e7a6000,0x4e7b0000,0x4e7b0001
+	.long	0xf58af58c,0xf58bf58d,0xf46af46c,0xf46bf46d
+	.long	0x24415681,0x2841f5ca,0xf5cc247c,0x80000000
+	.long	0x267ca000,0x0000287c,0x00000000,0x20080800
+	.long	0x00006600,0x009a6016,0x51fc51fc,0x51fc51fc
+	.long	0x4e7ba008,0x0e511000,0x0e500000,0x6002600e
+	.long	0xb042661c,0xb2436618,0x0e515800,0x6002600e
+	.long	0x4e7bb008,0x0e504800,0x4e7bc008,0x6034600e
+	.long	0x4e7bb008,0x0e500800,0x4e7bc008,0x6012600e
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160b0
+	.long	0x4e7b6000,0x4e7b6001,0x46c751c4,0x60ffffff
+	.long	0xfb624e7b,0x60004e7b,0x600146c7,0x50c460ff
+	.long	0xfffffb50,0x51fc51fc,0x51fc51fc,0x51fc51fc
+	.long	0x4e7ba008,0x0e511000,0x0e500000,0x6002600e
+	.long	0xb042662c,0xb2436628,0x0e515800,0x6002600e
+	.long	0xe09c0e18,0x48004e7b,0xb008e19c,0x6002600e
+	.long	0x0e104800,0x4e7bc008,0x6000ffa8,0x4e71600e
+	.long	0xe0980e18,0x08004e7b,0xb008e198,0x6002600e
+	.long	0x0e100800,0x4e7bc008,0x6000ff76,0x4e71600e
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090
+	.long	0x4a066604,0x70016002,0x70054a07,0x660000c6
+	.long	0x22482448,0x528a2602,0xe04a40c7,0x007c0700
+	.long	0x4e7a6000,0x4e7b0000,0x4e7b0001,0xf589f58a
+	.long	0xf469f46a,0x227c8000,0x0000247c,0xa0000000
+	.long	0x267c0000,0x00006016,0x51fc51fc,0x51fc51fc
+	.long	0x4e7b9008,0x0e500000,0xb0446624,0x6002600e
+	.long	0x0e182800,0x4e7ba008,0x0e103800,0x6002600e
+	.long	0x4e7bb008,0x604c4e71,0x4e714e71,0x4e71600e
+	.long	0xe0980e18,0x08004e7b,0xa008e198,0x6002600e
+	.long	0x0e100800,0x4e7bb008,0x60164e71,0x4e71600e
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160a0
+	.long	0x4e7b6000,0x4e7b6001,0x46c751c1,0x60ffffff
+	.long	0xfb164e7b,0x60004e7b,0x600146c7,0x50c160ff
+	.long	0xfffffb04,0x22482448,0x568a2208,0x08010000
+	.long	0x660000c2,0x26024842,0x40c7007c,0x07004e7a
+	.long	0x60004e7b,0x00004e7b,0x0001f589,0xf58af469
+	.long	0xf46a227c,0x80000000,0x247ca000,0x0000267c
+	.long	0x00000000,0x601851fc,0x51fc51fc,0x51fc51fc
+	.long	0x4e7b9008,0x0e900000,0xb0846624,0x6002600e
+	.long	0x0e582800,0x4e7ba008,0x0e503800,0x6002600e
+	.long	0x4e7bb008,0x604c4e71,0x4e714e71,0x4e71600e
+	.long	0x48400e58,0x08004840,0x4e7ba008,0x6002600e
+	.long	0x0e500800,0x4e7bb008,0x60164e71,0x4e71600e
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x4e7160a0
+	.long	0x4e7b6000,0x4e7b6001,0x46c751c1,0x60ffffff
+	.long	0xfa464e7b,0x60004e7b,0x600146c7,0x50c160ff
+	.long	0xfffffa34,0x2a02e08a,0x26024842,0x40c7007c
+	.long	0x07004e7a,0x60004e7b,0x00004e7b,0x0001f589
+	.long	0xf58af469,0xf46a227c,0x80000000,0x247ca000
+	.long	0x0000267c,0x00000000,0x601451fc,0x51fc51fc
+	.long	0x4e7b9008,0x0e900000,0xb0846624,0x6002600e
+	.long	0x0e182800,0x0e583800,0x4e7ba008,0x6002600e
+	.long	0x0e105800,0x4e7bb008,0x6000ff88,0x4e71600e
+	.long	0xe1980e18,0x08004840,0x0e580800,0x6002600e
+	.long	0xe1984e7b,0xa0080e10,0x08006004,0x4e71600e
+	.long	0x4e7bb008,0x6000ff4a,0x4e714e71,0x4e71600e
+	.long	0x4e714e71,0x4e714e71,0x4e714e71,0x4e716090
--- a/arch/m68k/ifpsp060/itest.sa
+++ b/arch/m68k/ifpsp060/itest.sa
--- a/arch/m68k/ifpsp060/os.S
+++ b/arch/m68k/ifpsp060/os.S
@ -0,0 +1,396 @@
+|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+|M68000 Hi-Performance Microprocessor Division
+|M68060 Software Package
+|Production Release P1.00 -- October 10, 1994
+|
+|M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+|
+|THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+|To the maximum extent permitted by applicable law,
+|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+|and any warranty against infringement with regard to the SOFTWARE
+|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+|
+|To the maximum extent permitted by applicable law,
+|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+|
+|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+|so long as this entire notice is retained without alteration in any modified and/or
+|redistributed versions, and that such modified versions are clearly identified as such.
+|No licenses are granted by implication, estoppel or otherwise under any patents
+|or trademarks of Motorola, Inc.
+|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+| os.s
+|
+| This file contains:
+|	- example "Call-Out"s required by both the ISP and FPSP.
+|
+
+#include <linux/linkage.h>
+
+|################################
+| EXAMPLE CALL-OUTS		#
+|				#
+| _060_dmem_write()		#
+| _060_dmem_read()		#
+| _060_imem_read()		#
+| _060_dmem_read_byte()		#
+| _060_dmem_read_word()		#
+| _060_dmem_read_long()		#
+| _060_imem_read_word()		#
+| _060_imem_read_long()		#
+| _060_dmem_write_byte()	#
+| _060_dmem_write_word()	#
+| _060_dmem_write_long()	#
+|				#
+| _060_real_trace()		#
+| _060_real_access()		#
+|################################
+
+|
+| Each IO routine checks to see if the memory write/read is to/from user
+| or supervisor application space. The examples below use simple "move"
+| instructions for supervisor mode applications and call _copyin()/_copyout()
+| for user mode applications.
+| When installing the 060SP, the _copyin()/_copyout() equivalents for a
+| given operating system should be substituted.
+|
+| The addresses within the 060SP are guaranteed to be on the stack.
+| The result is that Unix processes are allowed to sleep as a consequence
+| of a page fault during a _copyout.
+|
+| Linux/68k: The _060_[id]mem_{read,write}_{byte,word,long} functions
+| (i.e. all the known length <= 4) are implemented by single moves
+| statements instead of (more expensive) copy{in,out} calls, if
+| working in user space
+
+|
+| _060_dmem_write():
+|
+| Writes to data memory while in supervisor mode.
+|
+| INPUTS:
+|	a0 - supervisor source address
+|	a1 - user destination address
+|	d0 - number of bytes to write
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_dmem_write
+_060_dmem_write:
+	subq.l		#1,%d0
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	beqs		user_write
+super_write:
+	move.b		(%a0)+,(%a1)+		| copy 1 byte
+	dbra		%d0,super_write		| quit if --ctr < 0
+	clr.l		%d1			| return success
+	rts
+user_write:
+	move.b		(%a0)+,%d1		| copy 1 byte
+copyoutae:
+	movs.b		%d1,(%a1)+
+	dbra		%d0,user_write		| quit if --ctr < 0
+	clr.l		%d1			| return success
+	rts
+
+|
+| _060_imem_read(), _060_dmem_read():
+|
+| Reads from data/instruction memory while in supervisor mode.
+|
+| INPUTS:
+|	a0 - user source address
+|	a1 - supervisor destination address
+|	d0 - number of bytes to read
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_imem_read
+	.global		_060_dmem_read
+_060_imem_read:
+_060_dmem_read:
+	subq.l		#1,%d0
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	beqs		user_read
+super_read:
+	move.b		(%a0)+,(%a1)+		| copy 1 byte
+	dbra		%d0,super_read		| quit if --ctr < 0
+	clr.l		%d1			| return success
+	rts
+user_read:
+copyinae:
+	movs.b		(%a0)+,%d1
+	move.b		%d1,(%a1)+		| copy 1 byte
+	dbra		%d0,user_read		| quit if --ctr < 0
+	clr.l		%d1			| return success
+	rts
+
+|
+| _060_dmem_read_byte():
+|
+| Read a data byte from user memory.
+|
+| INPUTS:
+|	a0 - user source address
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d0 - data byte in d0
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_dmem_read_byte
+_060_dmem_read_byte:
+	clr.l		%d0			| clear whole longword
+	clr.l		%d1			| assume success
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	bnes		dmrbs			| supervisor
+dmrbuae:movs.b		(%a0),%d0		| fetch user byte
+	rts
+dmrbs:	move.b		(%a0),%d0		| fetch super byte
+	rts
+
+|
+| _060_dmem_read_word():
+|
+| Read a data word from user memory.
+|
+| INPUTS:
+|	a0 - user source address
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d0 - data word in d0
+|	d1 - 0 = success, !0 = failure
+|
+| _060_imem_read_word():
+|
+| Read an instruction word from user memory.
+|
+| INPUTS:
+|	a0 - user source address
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d0 - instruction word in d0
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_dmem_read_word
+	.global		_060_imem_read_word
+_060_dmem_read_word:
+_060_imem_read_word:
+	clr.l		%d1			| assume success
+	clr.l		%d0			| clear whole longword
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	bnes		dmrws			| supervisor
+dmrwuae:movs.w		(%a0), %d0		| fetch user word
+	rts
+dmrws:	move.w		(%a0), %d0		| fetch super word
+	rts
+
+|
+| _060_dmem_read_long():
+|
+
+|
+| INPUTS:
+|	a0 - user source address
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d0 - data longword in d0
+|	d1 - 0 = success, !0 = failure
+|
+| _060_imem_read_long():
+|
+| Read an instruction longword from user memory.
+|
+| INPUTS:
+|	a0 - user source address
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d0 - instruction longword in d0
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_dmem_read_long
+	.global		_060_imem_read_long
+_060_dmem_read_long:
+_060_imem_read_long:
+	clr.l		%d1			| assume success
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	bnes		dmrls			| supervisor
+dmrluae:movs.l		(%a0),%d0		| fetch user longword
+	rts
+dmrls:	move.l		(%a0),%d0		| fetch super longword
+	rts
+
+|
+| _060_dmem_write_byte():
+|
+| Write a data byte to user memory.
+|
+| INPUTS:
+|	a0 - user destination address
+|	d0 - data byte in d0
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_dmem_write_byte
+_060_dmem_write_byte:
+	clr.l		%d1			| assume success
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	bnes		dmwbs			| supervisor
+dmwbuae:movs.b		%d0,(%a0)		| store user byte
+	rts
+dmwbs:	move.b		%d0,(%a0)		| store super byte
+	rts
+
+|
+| _060_dmem_write_word():
+|
+| Write a data word to user memory.
+|
+| INPUTS:
+|	a0 - user destination address
+|	d0 - data word in d0
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_dmem_write_word
+_060_dmem_write_word:
+	clr.l		%d1			| assume success
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	bnes		dmwws			| supervisor
+dmwwu:
+dmwwuae:movs.w		%d0,(%a0)		| store user word
+	bras		dmwwr
+dmwws:	move.w		%d0,(%a0)		| store super word
+dmwwr:	clr.l		%d1			| return success
+	rts
+
+|
+| _060_dmem_write_long():
+|
+| Write a data longword to user memory.
+|
+| INPUTS:
+|	a0 - user destination address
+|	d0 - data longword in d0
+|	0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| OUTPUTS:
+|	d1 - 0 = success, !0 = failure
+|
+	.global		_060_dmem_write_long
+_060_dmem_write_long:
+	clr.l		%d1			| assume success
+	btst		#0x5,0x4(%a6)		| check for supervisor state
+	bnes		dmwls			| supervisor
+dmwluae:movs.l		%d0,(%a0)		| store user longword
+	rts
+dmwls:	move.l		%d0,(%a0)		| store super longword
+	rts
+
+
+#if 0
+|###############################################
+
+|
+| Use these routines if your kernel doesn't have _copyout/_copyin equivalents.
+| Assumes that D0/D1/A0/A1 are scratch registers. The _copyin/_copyout
+| below assume that the SFC/DFC have been set previously.
+|
+| Linux/68k: These are basically non-inlined versions of
+| memcpy_{to,from}fs, but without long-transfer optimization
+| Note: Assumed that SFC/DFC are pointing correctly to user data
+| space... Should be right, or are there any exceptions?
+
+|
+| int _copyout(supervisor_addr, user_addr, nbytes)
+|
+	.global		_copyout
+_copyout:
+	move.l		4(%sp),%a0		| source
+	move.l		8(%sp),%a1		| destination
+	move.l		12(%sp),%d0		| count
+	subq.l		#1,%d0
+moreout:
+	move.b		(%a0)+,%d1		| fetch supervisor byte
+copyoutae:
+	movs.b		%d1,(%a1)+		| store user byte
+	dbra		%d0,moreout		| are we through yet?
+	moveq		#0,%d0			| return success
+	rts
+
+|
+| int _copyin(user_addr, supervisor_addr, nbytes)
+|
+	.global		_copyin
+_copyin:
+	move.l		4(%sp),%a0		| source
+	move.l		8(%sp),%a1		| destination
+	move.l		12(%sp),%d0		| count
+    subq.l      #1,%d0
+morein:
+copyinae:
+	movs.b		(%a0)+,%d1		| fetch user byte
+	move.b		%d1,(%a1)+		| write supervisor byte
+	dbra		%d0,morein		| are we through yet?
+	moveq		#0,%d0			| return success
+	rts
+#endif
+
+|###########################################################################
+
+|
+| _060_real_trace():
+|
+| This is the exit point for the 060FPSP when an instruction is being traced
+| and there are no other higher priority exceptions pending for this instruction
+| or they have already been processed.
+|
+| The sample code below simply executes an "rte".
+|
+	.global		_060_real_trace
+_060_real_trace:
+	bral	trap
+
+|
+| _060_real_access():
+|
+| This is the exit point for the 060FPSP when an access error exception
+| is encountered. The routine below should point to the operating system
+| handler for access error exceptions. The exception stack frame is an
+| 8-word access error frame.
+|
+| The sample routine below simply executes an "rte" instruction which
+| is most likely the incorrect thing to do and could put the system
+| into an infinite loop.
+|
+	.global		_060_real_access
+_060_real_access:
+	bral	buserr
+
+
+
+| Execption handling for movs access to illegal memory
+	.section .fixup,#alloc,#execinstr
+	.even
+1:	moveq		#-1,%d1
+	rts
+.section __ex_table,#alloc
+	.align 4
+	.long	dmrbuae,1b
+	.long	dmrwuae,1b
+	.long	dmrluae,1b
+	.long	dmwbuae,1b
+	.long	dmwwuae,1b
+	.long	dmwluae,1b
+	.long	copyoutae,1b
+	.long	copyinae,1b
+	.text
--- a/arch/m68k/ifpsp060/pfpsp.sa
+++ b/arch/m68k/ifpsp060/pfpsp.sa
--- a/arch/m68k/ifpsp060/src/README-SRC
+++ b/arch/m68k/ifpsp060/src/README-SRC
@ -0,0 +1,12 @@
+This is the original source code from Motorola for the 68060 processor
+support code, providing emulation for rarely used m68k instructions
+not implemented in the 68060 silicon.
+
+The code provided here will not assemble out of the box using the GNU
+assembler, however it is being included in order to comply with the
+GNU General Public License.
+
+You don't need to actually assemble these files in order to compile a
+workin m68k kernel, the precompiled .sa files in arch/m68k/ifpsp060
+are sufficient and were generated from these source files by
+Motorola.
--- a/arch/m68k/ifpsp060/src/fplsp.S
+++ b/arch/m68k/ifpsp060/src/fplsp.S
--- a/arch/m68k/ifpsp060/src/fpsp.S
+++ b/arch/m68k/ifpsp060/src/fpsp.S
--- a/arch/m68k/ifpsp060/src/ftest.S
+++ b/arch/m68k/ifpsp060/src/ftest.S
--- a/arch/m68k/ifpsp060/src/ilsp.S
+++ b/arch/m68k/ifpsp060/src/ilsp.S
@ -0,0 +1,932 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+# litop.s:
+#	This file is appended to the top of the 060FPLSP package
+# and contains the entry points into the package. The user, in
+# effect, branches to one of the branch table entries located here.
+#
+
+	bra.l	_060LSP__idivs64_
+	short	0x0000
+	bra.l	_060LSP__idivu64_
+	short	0x0000
+
+	bra.l	_060LSP__imuls64_
+	short	0x0000
+	bra.l	_060LSP__imulu64_
+	short	0x0000
+
+	bra.l	_060LSP__cmp2_Ab_
+	short	0x0000
+	bra.l	_060LSP__cmp2_Aw_
+	short	0x0000
+	bra.l	_060LSP__cmp2_Al_
+	short	0x0000
+	bra.l	_060LSP__cmp2_Db_
+	short	0x0000
+	bra.l	_060LSP__cmp2_Dw_
+	short	0x0000
+	bra.l	_060LSP__cmp2_Dl_
+	short	0x0000
+
+# leave room for future possible aditions.
+	align	0x200
+
+#########################################################################
+# XDEF ****************************************************************	#
+#	_060LSP__idivu64_(): Emulate 64-bit unsigned div instruction.	#
+#	_060LSP__idivs64_(): Emulate 64-bit signed div instruction.	#
+#									#
+#	This is the library version which is accessed as a subroutine	#
+#	and therefore does not work exactly like the 680X0 div{s,u}.l	#
+#	64-bit divide instruction.					#
+#									#
+# XREF ****************************************************************	#
+#	None.								#
+#									#
+# INPUT ***************************************************************	#
+#	0x4(sp)  = divisor						#
+#	0x8(sp)  = hi(dividend)						#
+#	0xc(sp)  = lo(dividend)						#
+#	0x10(sp) = pointer to location to place quotient/remainder	#
+#									#
+# OUTPUT **************************************************************	#
+#	0x10(sp) = points to location of remainder/quotient.		#
+#		   remainder is in first longword, quotient is in 2nd.	#
+#									#
+# ALGORITHM ***********************************************************	#
+#	If the operands are signed, make them unsigned and save the	#
+# sign info for later. Separate out special cases like divide-by-zero	#
+# or 32-bit divides if possible. Else, use a special math algorithm	#
+# to calculate the result.						#
+#	Restore sign info if signed instruction. Set the condition	#
+# codes before performing the final "rts". If the divisor was equal to	#
+# zero, then perform a divide-by-zero using a 16-bit implemented	#
+# divide instruction. This way, the operating system can record that	#
+# the event occurred even though it may not point to the correct place.	#
+#									#
+#########################################################################
+
+set	POSNEG,		-1
+set	NDIVISOR,	-2
+set	NDIVIDEND,	-3
+set	DDSECOND,	-4
+set	DDNORMAL,	-8
+set	DDQUOTIENT,	-12
+set	DIV64_CC,	-16
+
+##########
+# divs.l #
+##########
+	global		_060LSP__idivs64_
+_060LSP__idivs64_:
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-16
+	movm.l		&0x3f00,-(%sp)		# save d2-d7
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,DIV64_CC(%a6)
+	st		POSNEG(%a6)		# signed operation
+	bra.b		ldiv64_cont
+
+##########
+# divu.l #
+##########
+	global		_060LSP__idivu64_
+_060LSP__idivu64_:
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-16
+	movm.l		&0x3f00,-(%sp)		# save d2-d7
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,DIV64_CC(%a6)
+	sf		POSNEG(%a6)		# unsigned operation
+
+ldiv64_cont:
+	mov.l		0x8(%a6),%d7		# fetch divisor
+
+	beq.w		ldiv64eq0		# divisor is = 0!!!
+
+	mov.l		0xc(%a6), %d5		# get dividend hi
+	mov.l		0x10(%a6), %d6		# get dividend lo
+
+# separate signed and unsigned divide
+	tst.b		POSNEG(%a6)		# signed or unsigned?
+	beq.b		ldspecialcases		# use positive divide
+
+# save the sign of the divisor
+# make divisor unsigned if it's negative
+	tst.l		%d7			# chk sign of divisor
+	slt		NDIVISOR(%a6)		# save sign of divisor
+	bpl.b		ldsgndividend
+	neg.l		%d7			# complement negative divisor
+
+# save the sign of the dividend
+# make dividend unsigned if it's negative
+ldsgndividend:
+	tst.l		%d5			# chk sign of hi(dividend)
+	slt		NDIVIDEND(%a6)		# save sign of dividend
+	bpl.b		ldspecialcases
+
+	mov.w		&0x0, %cc		# clear 'X' cc bit
+	negx.l		%d6			# complement signed dividend
+	negx.l		%d5
+
+# extract some special cases:
+#	- is (dividend == 0) ?
+#	- is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
+ldspecialcases:
+	tst.l		%d5			# is (hi(dividend) == 0)
+	bne.b		ldnormaldivide		# no, so try it the long way
+
+	tst.l		%d6			# is (lo(dividend) == 0), too
+	beq.w		lddone			# yes, so (dividend == 0)
+
+	cmp.l		%d7,%d6			# is (divisor <= lo(dividend))
+	bls.b		ld32bitdivide		# yes, so use 32 bit divide
+
+	exg		%d5,%d6			# q = 0, r = dividend
+	bra.w		ldivfinish		# can't divide, we're done.
+
+ld32bitdivide:
+	tdivu.l		%d7, %d5:%d6		# it's only a 32/32 bit div!
+
+	bra.b		ldivfinish
+
+ldnormaldivide:
+# last special case:
+#	- is hi(dividend) >= divisor ? if yes, then overflow
+	cmp.l		%d7,%d5
+	bls.b		lddovf			# answer won't fit in 32 bits
+
+# perform the divide algorithm:
+	bsr.l		ldclassical		# do int divide
+
+# separate into signed and unsigned finishes.
+ldivfinish:
+	tst.b		POSNEG(%a6)		# do divs, divu separately
+	beq.b		lddone			# divu has no processing!!!
+
+# it was a divs.l, so ccode setting is a little more complicated...
+	tst.b		NDIVIDEND(%a6)		# remainder has same sign
+	beq.b		ldcc			# as dividend.
+	neg.l		%d5			# sgn(rem) = sgn(dividend)
+ldcc:
+	mov.b		NDIVISOR(%a6), %d0
+	eor.b		%d0, NDIVIDEND(%a6)	# chk if quotient is negative
+	beq.b		ldqpos			# branch to quot positive
+
+# 0x80000000 is the largest number representable as a 32-bit negative
+# number. the negative of 0x80000000 is 0x80000000.
+	cmpi.l		%d6, &0x80000000	# will (-quot) fit in 32 bits?
+	bhi.b		lddovf
+
+	neg.l		%d6			# make (-quot) 2's comp
+
+	bra.b		lddone
+
+ldqpos:
+	btst		&0x1f, %d6		# will (+quot) fit in 32 bits?
+	bne.b		lddovf
+
+lddone:
+# if the register numbers are the same, only the quotient gets saved.
+# so, if we always save the quotient second, we save ourselves a cmp&beq
+	andi.w		&0x10,DIV64_CC(%a6)
+	mov.w		DIV64_CC(%a6),%cc
+	tst.l		%d6			# may set 'N' ccode bit
+
+# here, the result is in d1 and d0. the current strategy is to save
+# the values at the location pointed to by a0.
+# use movm here to not disturb the condition codes.
+ldexit:
+	movm.l		&0x0060,([0x14,%a6])	# save result
+
+# EPILOGUE BEGIN ########################################################
+#	fmovm.l		(%sp)+,&0x0		# restore no fpregs
+	movm.l		(%sp)+,&0x00fc		# restore d2-d7
+	unlk		%a6
+# EPILOGUE END ##########################################################
+
+	rts
+
+# the result should be the unchanged dividend
+lddovf:
+	mov.l		0xc(%a6), %d5		# get dividend hi
+	mov.l		0x10(%a6), %d6		# get dividend lo
+
+	andi.w		&0x1c,DIV64_CC(%a6)
+	ori.w		&0x02,DIV64_CC(%a6)	# set 'V' ccode bit
+	mov.w		DIV64_CC(%a6),%cc
+
+	bra.b		ldexit
+
+ldiv64eq0:
+	mov.l		0xc(%a6),([0x14,%a6])
+	mov.l		0x10(%a6),([0x14,%a6],0x4)
+
+	mov.w		DIV64_CC(%a6),%cc
+
+# EPILOGUE BEGIN ########################################################
+#	fmovm.l		(%sp)+,&0x0		# restore no fpregs
+	movm.l		(%sp)+,&0x00fc		# restore d2-d7
+	unlk		%a6
+# EPILOGUE END ##########################################################
+
+	divu.w		&0x0,%d0		# force a divbyzero exception
+	rts
+
+###########################################################################
+#########################################################################
+# This routine uses the 'classical' Algorithm D from Donald Knuth's	#
+# Art of Computer Programming, vol II, Seminumerical Algorithms.	#
+# For this implementation b=2**16, and the target is U1U2U3U4/V1V2,	#
+# where U,V are words of the quadword dividend and longword divisor,	#
+# and U1, V1 are the most significant words.				#
+#									#
+# The most sig. longword of the 64 bit dividend must be in %d5, least	#
+# in %d6. The divisor must be in the variable ddivisor, and the		#
+# signed/unsigned flag ddusign must be set (0=unsigned,1=signed).	#
+# The quotient is returned in %d6, remainder in %d5, unless the		#
+# v (overflow) bit is set in the saved %ccr. If overflow, the dividend	#
+# is unchanged.								#
+#########################################################################
+ldclassical:
+# if the divisor msw is 0, use simpler algorithm then the full blown
+# one at ddknuth:
+
+	cmpi.l		%d7, &0xffff
+	bhi.b		lddknuth		# go use D. Knuth algorithm
+
+# Since the divisor is only a word (and larger than the mslw of the dividend),
+# a simpler algorithm may be used :
+# In the general case, four quotient words would be created by
+# dividing the divisor word into each dividend word. In this case,
+# the first two quotient words must be zero, or overflow would occur.
+# Since we already checked this case above, we can treat the most significant
+# longword of the dividend as (0) remainder (see Knuth) and merely complete
+# the last two divisions to get a quotient longword and word remainder:
+
+	clr.l		%d1
+	swap		%d5			# same as r*b if previous step rqd
+	swap		%d6			# get u3 to lsw position
+	mov.w		%d6, %d5		# rb + u3
+
+	divu.w		%d7, %d5
+
+	mov.w		%d5, %d1		# first quotient word
+	swap		%d6			# get u4
+	mov.w		%d6, %d5		# rb + u4
+
+	divu.w		%d7, %d5
+
+	swap		%d1
+	mov.w		%d5, %d1		# 2nd quotient 'digit'
+	clr.w		%d5
+	swap		%d5			# now remainder
+	mov.l		%d1, %d6		# and quotient
+
+	rts
+
+lddknuth:
+# In this algorithm, the divisor is treated as a 2 digit (word) number
+# which is divided into a 3 digit (word) dividend to get one quotient
+# digit (word). After subtraction, the dividend is shifted and the
+# process repeated. Before beginning, the divisor and quotient are
+# 'normalized' so that the process of estimating the quotient digit
+# will yield verifiably correct results..
+
+	clr.l		DDNORMAL(%a6)		# count of shifts for normalization
+	clr.b		DDSECOND(%a6)		# clear flag for quotient digits
+	clr.l		%d1			# %d1 will hold trial quotient
+lddnchk:
+	btst		&31, %d7		# must we normalize? first word of
+	bne.b		lddnormalized		# divisor (V1) must be >= 65536/2
+	addq.l		&0x1, DDNORMAL(%a6)	# count normalization shifts
+	lsl.l		&0x1, %d7		# shift the divisor
+	lsl.l		&0x1, %d6		# shift u4,u3 with overflow to u2
+	roxl.l		&0x1, %d5		# shift u1,u2
+	bra.w		lddnchk
+lddnormalized:
+
+# Now calculate an estimate of the quotient words (msw first, then lsw).
+# The comments use subscripts for the first quotient digit determination.
+	mov.l		%d7, %d3		# divisor
+	mov.l		%d5, %d2		# dividend mslw
+	swap		%d2
+	swap		%d3
+	cmp.w		%d2, %d3		# V1 = U1 ?
+	bne.b		lddqcalc1
+	mov.w		&0xffff, %d1		# use max trial quotient word
+	bra.b		lddadj0
+lddqcalc1:
+	mov.l		%d5, %d1
+
+	divu.w		%d3, %d1		# use quotient of mslw/msw
+
+	andi.l		&0x0000ffff, %d1	# zero any remainder
+lddadj0:
+
+# now test the trial quotient and adjust. This step plus the
+# normalization assures (according to Knuth) that the trial
+# quotient will be at worst 1 too large.
+	mov.l		%d6, -(%sp)
+	clr.w		%d6			# word u3 left
+	swap		%d6			# in lsw position
+lddadj1: mov.l		%d7, %d3
+	mov.l		%d1, %d2
+	mulu.w		%d7, %d2		# V2q
+	swap		%d3
+	mulu.w		%d1, %d3		# V1q
+	mov.l		%d5, %d4		# U1U2
+	sub.l		%d3, %d4		# U1U2 - V1q
+
+	swap		%d4
+
+	mov.w		%d4,%d0
+	mov.w		%d6,%d4			# insert lower word (U3)
+
+	tst.w		%d0			# is upper word set?
+	bne.w		lddadjd1
+
+#	add.l		%d6, %d4		# (U1U2 - V1q) + U3
+
+	cmp.l		%d2, %d4
+	bls.b		lddadjd1		# is V2q > (U1U2-V1q) + U3 ?
+	subq.l		&0x1, %d1		# yes, decrement and recheck
+	bra.b		lddadj1
+lddadjd1:
+# now test the word by multiplying it by the divisor (V1V2) and comparing
+# the 3 digit (word) result with the current dividend words
+	mov.l		%d5, -(%sp)		# save %d5 (%d6 already saved)
+	mov.l		%d1, %d6
+	swap		%d6			# shift answer to ms 3 words
+	mov.l		%d7, %d5
+	bsr.l		ldmm2
+	mov.l		%d5, %d2		# now %d2,%d3 are trial*divisor
+	mov.l		%d6, %d3
+	mov.l		(%sp)+, %d5		# restore dividend
+	mov.l		(%sp)+, %d6
+	sub.l		%d3, %d6
+	subx.l		%d2, %d5		# subtract double precision
+	bcc		ldd2nd			# no carry, do next quotient digit
+	subq.l		&0x1, %d1		# q is one too large
+# need to add back divisor longword to current ms 3 digits of dividend
+# - according to Knuth, this is done only 2 out of 65536 times for random
+# divisor, dividend selection.
+	clr.l		%d2
+	mov.l		%d7, %d3
+	swap		%d3
+	clr.w		%d3			# %d3 now ls word of divisor
+	add.l		%d3, %d6		# aligned with 3rd word of dividend
+	addx.l		%d2, %d5
+	mov.l		%d7, %d3
+	clr.w		%d3			# %d3 now ms word of divisor
+	swap		%d3			# aligned with 2nd word of dividend
+	add.l		%d3, %d5
+ldd2nd:
+	tst.b		DDSECOND(%a6)	# both q words done?
+	bne.b		lddremain
+# first quotient digit now correct. store digit and shift the
+# (subtracted) dividend
+	mov.w		%d1, DDQUOTIENT(%a6)
+	clr.l		%d1
+	swap		%d5
+	swap		%d6
+	mov.w		%d6, %d5
+	clr.w		%d6
+	st		DDSECOND(%a6)		# second digit
+	bra.w		lddnormalized
+lddremain:
+# add 2nd word to quotient, get the remainder.
+	mov.w		%d1, DDQUOTIENT+2(%a6)
+# shift down one word/digit to renormalize remainder.
+	mov.w		%d5, %d6
+	swap		%d6
+	swap		%d5
+	mov.l		DDNORMAL(%a6), %d7	# get norm shift count
+	beq.b		lddrn
+	subq.l		&0x1, %d7		# set for loop count
+lddnlp:
+	lsr.l		&0x1, %d5		# shift into %d6
+	roxr.l		&0x1, %d6
+	dbf		%d7, lddnlp
+lddrn:
+	mov.l		%d6, %d5		# remainder
+	mov.l		DDQUOTIENT(%a6), %d6	# quotient
+
+	rts
+ldmm2:
+# factors for the 32X32->64 multiplication are in %d5 and %d6.
+# returns 64 bit result in %d5 (hi) %d6(lo).
+# destroys %d2,%d3,%d4.
+
+# multiply hi,lo words of each factor to get 4 intermediate products
+	mov.l		%d6, %d2
+	mov.l		%d6, %d3
+	mov.l		%d5, %d4
+	swap		%d3
+	swap		%d4
+	mulu.w		%d5, %d6		# %d6 <- lsw*lsw
+	mulu.w		%d3, %d5		# %d5 <- msw-dest*lsw-source
+	mulu.w		%d4, %d2		# %d2 <- msw-source*lsw-dest
+	mulu.w		%d4, %d3		# %d3 <- msw*msw
+# now use swap and addx to consolidate to two longwords
+	clr.l		%d4
+	swap		%d6
+	add.w		%d5, %d6		# add msw of l*l to lsw of m*l product
+	addx.w		%d4, %d3		# add any carry to m*m product
+	add.w		%d2, %d6		# add in lsw of other m*l product
+	addx.w		%d4, %d3		# add any carry to m*m product
+	swap		%d6			# %d6 is low 32 bits of final product
+	clr.w		%d5
+	clr.w		%d2			# lsw of two mixed products used,
+	swap		%d5			# now use msws of longwords
+	swap		%d2
+	add.l		%d2, %d5
+	add.l		%d3, %d5	# %d5 now ms 32 bits of final product
+	rts
+
+#########################################################################
+# XDEF ****************************************************************	#
+#	_060LSP__imulu64_(): Emulate 64-bit unsigned mul instruction	#
+#	_060LSP__imuls64_(): Emulate 64-bit signed mul instruction.	#
+#									#
+#	This is the library version which is accessed as a subroutine	#
+#	and therefore does not work exactly like the 680X0 mul{s,u}.l	#
+#	64-bit multiply instruction.					#
+#									#
+# XREF ****************************************************************	#
+#	None								#
+#									#
+# INPUT ***************************************************************	#
+#	0x4(sp) = multiplier						#
+#	0x8(sp) = multiplicand						#
+#	0xc(sp) = pointer to location to place 64-bit result		#
+#									#
+# OUTPUT **************************************************************	#
+#	0xc(sp) = points to location of 64-bit result			#
+#									#
+# ALGORITHM ***********************************************************	#
+#	Perform the multiply in pieces using 16x16->32 unsigned		#
+# multiplies and "add" instructions.					#
+#	Set the condition codes as appropriate before performing an	#
+# "rts".								#
+#									#
+#########################################################################
+
+set MUL64_CC, -4
+
+	global		_060LSP__imulu64_
+_060LSP__imulu64_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3800,-(%sp)		# save d2-d4
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,MUL64_CC(%a6)	# save incoming ccodes
+
+	mov.l		0x8(%a6),%d0		# store multiplier in d0
+	beq.w		mulu64_zero		# handle zero separately
+
+	mov.l		0xc(%a6),%d1		# get multiplicand in d1
+	beq.w		mulu64_zero		# handle zero separately
+
+#########################################################################
+#	63			   32				0	#
+#	----------------------------					#
+#	| hi(mplier) * hi(mplicand)|					#
+#	----------------------------					#
+#		     -----------------------------			#
+#		     | hi(mplier) * lo(mplicand) |			#
+#		     -----------------------------			#
+#		     -----------------------------			#
+#		     | lo(mplier) * hi(mplicand) |			#
+#		     -----------------------------			#
+#	  |			   -----------------------------	#
+#	--|--			   | lo(mplier) * lo(mplicand) |	#
+#	  |			   -----------------------------	#
+#	========================================================	#
+#	--------------------------------------------------------	#
+#	|	hi(result)	   |	    lo(result)         |	#
+#	--------------------------------------------------------	#
+#########################################################################
+mulu64_alg:
+# load temp registers with operands
+	mov.l		%d0,%d2			# mr in d2
+	mov.l		%d0,%d3			# mr in d3
+	mov.l		%d1,%d4			# md in d4
+	swap		%d3			# hi(mr) in lo d3
+	swap		%d4			# hi(md) in lo d4
+
+# complete necessary multiplies:
+	mulu.w		%d1,%d0			# [1] lo(mr) * lo(md)
+	mulu.w		%d3,%d1			# [2] hi(mr) * lo(md)
+	mulu.w		%d4,%d2			# [3] lo(mr) * hi(md)
+	mulu.w		%d4,%d3			# [4] hi(mr) * hi(md)
+
+# add lo portions of [2],[3] to hi portion of [1].
+# add carries produced from these adds to [4].
+# lo([1]) is the final lo 16 bits of the result.
+	clr.l		%d4			# load d4 w/ zero value
+	swap		%d0			# hi([1]) <==> lo([1])
+	add.w		%d1,%d0			# hi([1]) + lo([2])
+	addx.l		%d4,%d3			#    [4]  + carry
+	add.w		%d2,%d0			# hi([1]) + lo([3])
+	addx.l		%d4,%d3			#    [4]  + carry
+	swap		%d0			# lo([1]) <==> hi([1])
+
+# lo portions of [2],[3] have been added in to final result.
+# now, clear lo, put hi in lo reg, and add to [4]
+	clr.w		%d1			# clear lo([2])
+	clr.w		%d2			# clear hi([3])
+	swap		%d1			# hi([2]) in lo d1
+	swap		%d2			# hi([3]) in lo d2
+	add.l		%d2,%d1			#    [4]  + hi([2])
+	add.l		%d3,%d1			#    [4]  + hi([3])
+
+# now, grab the condition codes. only one that can be set is 'N'.
+# 'N' CAN be set if the operation is unsigned if bit 63 is set.
+	mov.w		MUL64_CC(%a6),%d4
+	andi.b		&0x10,%d4		# keep old 'X' bit
+	tst.l		%d1			# may set 'N' bit
+	bpl.b		mulu64_ddone
+	ori.b		&0x8,%d4		# set 'N' bit
+mulu64_ddone:
+	mov.w		%d4,%cc
+
+# here, the result is in d1 and d0. the current strategy is to save
+# the values at the location pointed to by a0.
+# use movm here to not disturb the condition codes.
+mulu64_end:
+	exg		%d1,%d0
+	movm.l		&0x0003,([0x10,%a6])		# save result
+
+# EPILOGUE BEGIN ########################################################
+#	fmovm.l		(%sp)+,&0x0		# restore no fpregs
+	movm.l		(%sp)+,&0x001c		# restore d2-d4
+	unlk		%a6
+# EPILOGUE END ##########################################################
+
+	rts
+
+# one or both of the operands is zero so the result is also zero.
+# save the zero result to the register file and set the 'Z' ccode bit.
+mulu64_zero:
+	clr.l		%d0
+	clr.l		%d1
+
+	mov.w		MUL64_CC(%a6),%d4
+	andi.b		&0x10,%d4
+	ori.b		&0x4,%d4
+	mov.w		%d4,%cc			# set 'Z' ccode bit
+
+	bra.b		mulu64_end
+
+##########
+# muls.l #
+##########
+	global		_060LSP__imuls64_
+_060LSP__imuls64_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3c00,-(%sp)		# save d2-d5
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,MUL64_CC(%a6)	# save incoming ccodes
+
+	mov.l		0x8(%a6),%d0		# store multiplier in d0
+	beq.b		mulu64_zero		# handle zero separately
+
+	mov.l		0xc(%a6),%d1		# get multiplicand in d1
+	beq.b		mulu64_zero		# handle zero separately
+
+	clr.b		%d5			# clear sign tag
+	tst.l		%d0			# is multiplier negative?
+	bge.b		muls64_chk_md_sgn	# no
+	neg.l		%d0			# make multiplier positive
+
+	ori.b		&0x1,%d5		# save multiplier sgn
+
+# the result sign is the exclusive or of the operand sign bits.
+muls64_chk_md_sgn:
+	tst.l		%d1			# is multiplicand negative?
+	bge.b		muls64_alg		# no
+	neg.l		%d1			# make multiplicand positive
+
+	eori.b		&0x1,%d5		# calculate correct sign
+
+#########################################################################
+#	63			   32				0	#
+#	----------------------------					#
+#	| hi(mplier) * hi(mplicand)|					#
+#	----------------------------					#
+#		     -----------------------------			#
+#		     | hi(mplier) * lo(mplicand) |			#
+#		     -----------------------------			#
+#		     -----------------------------			#
+#		     | lo(mplier) * hi(mplicand) |			#
+#		     -----------------------------			#
+#	  |			   -----------------------------	#
+#	--|--			   | lo(mplier) * lo(mplicand) |	#
+#	  |			   -----------------------------	#
+#	========================================================	#
+#	--------------------------------------------------------	#
+#	|	hi(result)	   |	    lo(result)         |	#
+#	--------------------------------------------------------	#
+#########################################################################
+muls64_alg:
+# load temp registers with operands
+	mov.l		%d0,%d2			# mr in d2
+	mov.l		%d0,%d3			# mr in d3
+	mov.l		%d1,%d4			# md in d4
+	swap		%d3			# hi(mr) in lo d3
+	swap		%d4			# hi(md) in lo d4
+
+# complete necessary multiplies:
+	mulu.w		%d1,%d0			# [1] lo(mr) * lo(md)
+	mulu.w		%d3,%d1			# [2] hi(mr) * lo(md)
+	mulu.w		%d4,%d2			# [3] lo(mr) * hi(md)
+	mulu.w		%d4,%d3			# [4] hi(mr) * hi(md)
+
+# add lo portions of [2],[3] to hi portion of [1].
+# add carries produced from these adds to [4].
+# lo([1]) is the final lo 16 bits of the result.
+	clr.l		%d4			# load d4 w/ zero value
+	swap		%d0			# hi([1]) <==> lo([1])
+	add.w		%d1,%d0			# hi([1]) + lo([2])
+	addx.l		%d4,%d3			#    [4]  + carry
+	add.w		%d2,%d0			# hi([1]) + lo([3])
+	addx.l		%d4,%d3			#    [4]  + carry
+	swap		%d0			# lo([1]) <==> hi([1])
+
+# lo portions of [2],[3] have been added in to final result.
+# now, clear lo, put hi in lo reg, and add to [4]
+	clr.w		%d1			# clear lo([2])
+	clr.w		%d2			# clear hi([3])
+	swap		%d1			# hi([2]) in lo d1
+	swap		%d2			# hi([3]) in lo d2
+	add.l		%d2,%d1			#    [4]  + hi([2])
+	add.l		%d3,%d1			#    [4]  + hi([3])
+
+	tst.b		%d5			# should result be signed?
+	beq.b		muls64_done		# no
+
+# result should be a signed negative number.
+# compute 2's complement of the unsigned number:
+#   -negate all bits and add 1
+muls64_neg:
+	not.l		%d0			# negate lo(result) bits
+	not.l		%d1			# negate hi(result) bits
+	addq.l		&1,%d0			# add 1 to lo(result)
+	addx.l		%d4,%d1			# add carry to hi(result)
+
+muls64_done:
+	mov.w		MUL64_CC(%a6),%d4
+	andi.b		&0x10,%d4		# keep old 'X' bit
+	tst.l		%d1			# may set 'N' bit
+	bpl.b		muls64_ddone
+	ori.b		&0x8,%d4		# set 'N' bit
+muls64_ddone:
+	mov.w		%d4,%cc
+
+# here, the result is in d1 and d0. the current strategy is to save
+# the values at the location pointed to by a0.
+# use movm here to not disturb the condition codes.
+muls64_end:
+	exg		%d1,%d0
+	movm.l		&0x0003,([0x10,%a6])	# save result at (a0)
+
+# EPILOGUE BEGIN ########################################################
+#	fmovm.l		(%sp)+,&0x0		# restore no fpregs
+	movm.l		(%sp)+,&0x003c		# restore d2-d5
+	unlk		%a6
+# EPILOGUE END ##########################################################
+
+	rts
+
+# one or both of the operands is zero so the result is also zero.
+# save the zero result to the register file and set the 'Z' ccode bit.
+muls64_zero:
+	clr.l		%d0
+	clr.l		%d1
+
+	mov.w		MUL64_CC(%a6),%d4
+	andi.b		&0x10,%d4
+	ori.b		&0x4,%d4
+	mov.w		%d4,%cc			# set 'Z' ccode bit
+
+	bra.b		muls64_end
+
+#########################################################################
+# XDEF ****************************************************************	#
+#	_060LSP__cmp2_Ab_(): Emulate "cmp2.b An,<ea>".			#
+#	_060LSP__cmp2_Aw_(): Emulate "cmp2.w An,<ea>".			#
+#	_060LSP__cmp2_Al_(): Emulate "cmp2.l An,<ea>".			#
+#	_060LSP__cmp2_Db_(): Emulate "cmp2.b Dn,<ea>".			#
+#	_060LSP__cmp2_Dw_(): Emulate "cmp2.w Dn,<ea>".			#
+#	_060LSP__cmp2_Dl_(): Emulate "cmp2.l Dn,<ea>".			#
+#									#
+#	This is the library version which is accessed as a subroutine	#
+#	and therefore does not work exactly like the 680X0 "cmp2"	#
+#	instruction.							#
+#									#
+# XREF ****************************************************************	#
+#	None								#
+#									#
+# INPUT ***************************************************************	#
+#	0x4(sp) = Rn							#
+#	0x8(sp) = pointer to boundary pair				#
+#									#
+# OUTPUT **************************************************************	#
+#	cc = condition codes are set correctly				#
+#									#
+# ALGORITHM ***********************************************************	#
+#	In the interest of simplicity, all operands are converted to	#
+# longword size whether the operation is byte, word, or long. The	#
+# bounds are sign extended accordingly. If Rn is a data regsiter, Rn is #
+# also sign extended. If Rn is an address register, it need not be sign #
+# extended since the full register is always used.			#
+#	The condition codes are set correctly before the final "rts".	#
+#									#
+#########################################################################
+
+set	CMP2_CC,	-4
+
+	global		_060LSP__cmp2_Ab_
+_060LSP__cmp2_Ab_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3800,-(%sp)		# save d2-d4
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,CMP2_CC(%a6)
+	mov.l		0x8(%a6), %d2		# get regval
+
+	mov.b		([0xc,%a6],0x0),%d0
+	mov.b		([0xc,%a6],0x1),%d1
+
+	extb.l		%d0			# sign extend lo bnd
+	extb.l		%d1			# sign extend hi bnd
+	bra.w		l_cmp2_cmp		# go do the compare emulation
+
+	global		_060LSP__cmp2_Aw_
+_060LSP__cmp2_Aw_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3800,-(%sp)		# save d2-d4
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,CMP2_CC(%a6)
+	mov.l		0x8(%a6), %d2		# get regval
+
+	mov.w		([0xc,%a6],0x0),%d0
+	mov.w		([0xc,%a6],0x2),%d1
+
+	ext.l		%d0			# sign extend lo bnd
+	ext.l		%d1			# sign extend hi bnd
+	bra.w		l_cmp2_cmp		# go do the compare emulation
+
+	global		_060LSP__cmp2_Al_
+_060LSP__cmp2_Al_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3800,-(%sp)		# save d2-d4
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,CMP2_CC(%a6)
+	mov.l		0x8(%a6), %d2		# get regval
+
+	mov.l		([0xc,%a6],0x0),%d0
+	mov.l		([0xc,%a6],0x4),%d1
+	bra.w		l_cmp2_cmp		# go do the compare emulation
+
+	global		_060LSP__cmp2_Db_
+_060LSP__cmp2_Db_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3800,-(%sp)		# save d2-d4
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,CMP2_CC(%a6)
+	mov.l		0x8(%a6), %d2		# get regval
+
+	mov.b		([0xc,%a6],0x0),%d0
+	mov.b		([0xc,%a6],0x1),%d1
+
+	extb.l		%d0			# sign extend lo bnd
+	extb.l		%d1			# sign extend hi bnd
+
+# operation is a data register compare.
+# sign extend byte to long so we can do simple longword compares.
+	extb.l		%d2			# sign extend data byte
+	bra.w		l_cmp2_cmp		# go do the compare emulation
+
+	global		_060LSP__cmp2_Dw_
+_060LSP__cmp2_Dw_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3800,-(%sp)		# save d2-d4
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,CMP2_CC(%a6)
+	mov.l		0x8(%a6), %d2		# get regval
+
+	mov.w		([0xc,%a6],0x0),%d0
+	mov.w		([0xc,%a6],0x2),%d1
+
+	ext.l		%d0			# sign extend lo bnd
+	ext.l		%d1			# sign extend hi bnd
+
+# operation is a data register compare.
+# sign extend word to long so we can do simple longword compares.
+	ext.l		%d2			# sign extend data word
+	bra.w		l_cmp2_cmp		# go emulate compare
+
+	global		_060LSP__cmp2_Dl_
+_060LSP__cmp2_Dl_:
+
+# PROLOGUE BEGIN ########################################################
+	link.w		%a6,&-4
+	movm.l		&0x3800,-(%sp)		# save d2-d4
+#	fmovm.l		&0x0,-(%sp)		# save no fpregs
+# PROLOGUE END ##########################################################
+
+	mov.w		%cc,CMP2_CC(%a6)
+	mov.l		0x8(%a6), %d2		# get regval
+
+	mov.l		([0xc,%a6],0x0),%d0
+	mov.l		([0xc,%a6],0x4),%d1
+
+#
+# To set the ccodes correctly:
+#	(1) save 'Z' bit from (Rn - lo)
+#	(2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
+#	(3) keep 'X', 'N', and 'V' from before instruction
+#	(4) combine ccodes
+#
+l_cmp2_cmp:
+	sub.l		%d0, %d2		# (Rn - lo)
+	mov.w		%cc, %d3		# fetch resulting ccodes
+	andi.b		&0x4, %d3		# keep 'Z' bit
+	sub.l		%d0, %d1		# (hi - lo)
+	cmp.l		%d1,%d2			# ((hi - lo) - (Rn - hi))
+
+	mov.w		%cc, %d4		# fetch resulting ccodes
+	or.b		%d4, %d3		# combine w/ earlier ccodes
+	andi.b		&0x5, %d3		# keep 'Z' and 'N'
+
+	mov.w		CMP2_CC(%a6), %d4	# fetch old ccodes
+	andi.b		&0x1a, %d4		# keep 'X','N','V' bits
+	or.b		%d3, %d4		# insert new ccodes
+	mov.w		%d4,%cc			# save new ccodes
+
+# EPILOGUE BEGIN ########################################################
+#	fmovm.l		(%sp)+,&0x0		# restore no fpregs
+	movm.l		(%sp)+,&0x001c		# restore d2-d4
+	unlk		%a6
+# EPILOGUE END ##########################################################
+
+	rts
--- a/arch/m68k/ifpsp060/src/isp.S
+++ b/arch/m68k/ifpsp060/src/isp.S
--- a/arch/m68k/ifpsp060/src/itest.S
+++ b/arch/m68k/ifpsp060/src/itest.S
--- a/arch/m68k/ifpsp060/src/pfpsp.S
+++ b/arch/m68k/ifpsp060/src/pfpsp.S