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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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37
arch/m68k/include/asm/Kbuild Normal file
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generic-y += barrier.h
generic-y += bitsperlong.h
generic-y += clkdev.h
generic-y += cputime.h
generic-y += device.h
generic-y += emergency-restart.h
generic-y += errno.h
generic-y += exec.h
generic-y += hash.h
generic-y += hw_irq.h
generic-y += ioctl.h
generic-y += ipcbuf.h
generic-y += irq_regs.h
generic-y += irq_work.h
generic-y += kdebug.h
generic-y += kmap_types.h
generic-y += kvm_para.h
generic-y += local.h
generic-y += local64.h
generic-y += mcs_spinlock.h
generic-y += mman.h
generic-y += mutex.h
generic-y += percpu.h
generic-y += preempt.h
generic-y += resource.h
generic-y += scatterlist.h
generic-y += sections.h
generic-y += shmparam.h
generic-y += siginfo.h
generic-y += spinlock.h
generic-y += statfs.h
generic-y += termios.h
generic-y += topology.h
generic-y += trace_clock.h
generic-y += types.h
generic-y += word-at-a-time.h
generic-y += xor.h

1266
arch/m68k/include/asm/MC68328.h Normal file
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1253
arch/m68k/include/asm/MC68EZ328.h Normal file
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1349
arch/m68k/include/asm/MC68VZ328.h Normal file
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67
arch/m68k/include/asm/a.out-core.h Normal file
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/* a.out coredump register dumper
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_A_OUT_CORE_H
#define _ASM_A_OUT_CORE_H
#ifdef __KERNEL__
#include <linux/user.h>
#include <linux/elfcore.h>
/*
* fill in the user structure for an a.out core dump
*/
static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
{
struct switch_stack *sw;
/* changed the size calculations - should hopefully work better. lbt */
dump->magic = CMAGIC;
dump->start_code = 0;
dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
dump->u_dsize = ((unsigned long) (current->mm->brk +
(PAGE_SIZE-1))) >> PAGE_SHIFT;
dump->u_dsize -= dump->u_tsize;
dump->u_ssize = 0;
if (dump->start_stack < TASK_SIZE)
dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
dump->u_ar0 = offsetof(struct user, regs);
sw = ((struct switch_stack *)regs) - 1;
dump->regs.d1 = regs->d1;
dump->regs.d2 = regs->d2;
dump->regs.d3 = regs->d3;
dump->regs.d4 = regs->d4;
dump->regs.d5 = regs->d5;
dump->regs.d6 = sw->d6;
dump->regs.d7 = sw->d7;
dump->regs.a0 = regs->a0;
dump->regs.a1 = regs->a1;
dump->regs.a2 = regs->a2;
dump->regs.a3 = sw->a3;
dump->regs.a4 = sw->a4;
dump->regs.a5 = sw->a5;
dump->regs.a6 = sw->a6;
dump->regs.d0 = regs->d0;
dump->regs.orig_d0 = regs->orig_d0;
dump->regs.stkadj = regs->stkadj;
dump->regs.sr = regs->sr;
dump->regs.pc = regs->pc;
dump->regs.fmtvec = (regs->format << 12) | regs->vector;
/* dump floating point stuff */
dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp);
}
#endif /* __KERNEL__ */
#endif /* _ASM_A_OUT_CORE_H */

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arch/m68k/include/asm/adb_iop.h Normal file
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/*
* ADB through the IOP
* Written by Joshua M. Thompson
*/
/* IOP number and channel number for ADB */
#define ADB_IOP IOP_NUM_ISM
#define ADB_CHAN 2
/* From the A/UX headers...maybe important, maybe not */
#define ADB_IOP_LISTEN 0x01
#define ADB_IOP_TALK 0x02
#define ADB_IOP_EXISTS 0x04
#define ADB_IOP_FLUSH 0x08
#define ADB_IOP_RESET 0x10
#define ADB_IOP_INT 0x20
#define ADB_IOP_POLL 0x40
#define ADB_IOP_UNINT 0x80
#define AIF_RESET 0x00
#define AIF_FLUSH 0x01
#define AIF_LISTEN 0x08
#define AIF_TALK 0x0C
/* Flag bits in struct adb_iopmsg */
#define ADB_IOP_EXPLICIT 0x80 /* nonzero if explicit command */
#define ADB_IOP_AUTOPOLL 0x40 /* auto/SRQ polling enabled */
#define ADB_IOP_SRQ 0x04 /* SRQ detected */
#define ADB_IOP_TIMEOUT 0x02 /* nonzero if timeout */
#ifndef __ASSEMBLY__
struct adb_iopmsg {
__u8 flags; /* ADB flags */
__u8 count; /* no. of data bytes */
__u8 cmd; /* ADB command */
__u8 data[8]; /* ADB data */
__u8 spare[21]; /* spare */
};
#endif /* __ASSEMBLY__ */

325
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/*
** asm-m68k/amigahw.h -- This header defines some macros and pointers for
** the various Amiga custom hardware registers.
** The naming conventions used here conform to those
** used in the Amiga Hardware Reference Manual, 3rd Edition
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 9/24/92 by Greg Harp
*/
#ifndef _M68K_AMIGAHW_H
#define _M68K_AMIGAHW_H
#include <linux/ioport.h>
#include <asm/bootinfo-amiga.h>
/*
* Chipsets
*/
extern unsigned long amiga_chipset;
/*
* Miscellaneous
*/
extern unsigned long amiga_eclock; /* 700 kHz E Peripheral Clock */
extern unsigned long amiga_colorclock; /* 3.5 MHz Color Clock */
extern unsigned long amiga_chip_size; /* Chip RAM Size (bytes) */
extern unsigned char amiga_vblank; /* VBLANK Frequency */
#define AMIGAHW_DECLARE(name) unsigned name : 1
#define AMIGAHW_SET(name) (amiga_hw_present.name = 1)
#define AMIGAHW_PRESENT(name) (amiga_hw_present.name)
struct amiga_hw_present {
/* video hardware */
AMIGAHW_DECLARE(AMI_VIDEO); /* Amiga Video */
AMIGAHW_DECLARE(AMI_BLITTER); /* Amiga Blitter */
AMIGAHW_DECLARE(AMBER_FF); /* Amber Flicker Fixer */
/* sound hardware */
AMIGAHW_DECLARE(AMI_AUDIO); /* Amiga Audio */
/* disk storage interfaces */
AMIGAHW_DECLARE(AMI_FLOPPY); /* Amiga Floppy */
AMIGAHW_DECLARE(A3000_SCSI); /* SCSI (wd33c93, A3000 alike) */
AMIGAHW_DECLARE(A4000_SCSI); /* SCSI (ncr53c710, A4000T alike) */
AMIGAHW_DECLARE(A1200_IDE); /* IDE (A1200 alike) */
AMIGAHW_DECLARE(A4000_IDE); /* IDE (A4000 alike) */
AMIGAHW_DECLARE(CD_ROM); /* CD ROM drive */
/* other I/O hardware */
AMIGAHW_DECLARE(AMI_KEYBOARD); /* Amiga Keyboard */
AMIGAHW_DECLARE(AMI_MOUSE); /* Amiga Mouse */
AMIGAHW_DECLARE(AMI_SERIAL); /* Amiga Serial */
AMIGAHW_DECLARE(AMI_PARALLEL); /* Amiga Parallel */
/* real time clocks */
AMIGAHW_DECLARE(A2000_CLK); /* Hardware Clock (A2000 alike) */
AMIGAHW_DECLARE(A3000_CLK); /* Hardware Clock (A3000 alike) */
/* supporting hardware */
AMIGAHW_DECLARE(CHIP_RAM); /* Chip RAM */
AMIGAHW_DECLARE(PAULA); /* Paula (8364) */
AMIGAHW_DECLARE(DENISE); /* Denise (8362) */
AMIGAHW_DECLARE(DENISE_HR); /* Denise (8373) */
AMIGAHW_DECLARE(LISA); /* Lisa (8375) */
AMIGAHW_DECLARE(AGNUS_PAL); /* Normal/Fat PAL Agnus (8367/8371) */
AMIGAHW_DECLARE(AGNUS_NTSC); /* Normal/Fat NTSC Agnus (8361/8370) */
AMIGAHW_DECLARE(AGNUS_HR_PAL); /* Fat Hires PAL Agnus (8372) */
AMIGAHW_DECLARE(AGNUS_HR_NTSC); /* Fat Hires NTSC Agnus (8372) */
AMIGAHW_DECLARE(ALICE_PAL); /* PAL Alice (8374) */
AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */
AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */
AMIGAHW_DECLARE(PCMCIA); /* PCMCIA Slot */
AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */
AMIGAHW_DECLARE(ZORRO3); /* Zorro III */
};
extern struct amiga_hw_present amiga_hw_present;
struct CUSTOM {
unsigned short bltddat;
unsigned short dmaconr;
unsigned short vposr;
unsigned short vhposr;
unsigned short dskdatr;
unsigned short joy0dat;
unsigned short joy1dat;
unsigned short clxdat;
unsigned short adkconr;
unsigned short pot0dat;
unsigned short pot1dat;
unsigned short potgor;
unsigned short serdatr;
unsigned short dskbytr;
unsigned short intenar;
unsigned short intreqr;
unsigned char *dskptr;
unsigned short dsklen;
unsigned short dskdat;
unsigned short refptr;
unsigned short vposw;
unsigned short vhposw;
unsigned short copcon;
unsigned short serdat;
unsigned short serper;
unsigned short potgo;
unsigned short joytest;
unsigned short strequ;
unsigned short strvbl;
unsigned short strhor;
unsigned short strlong;
unsigned short bltcon0;
unsigned short bltcon1;
unsigned short bltafwm;
unsigned short bltalwm;
unsigned char *bltcpt;
unsigned char *bltbpt;
unsigned char *bltapt;
unsigned char *bltdpt;
unsigned short bltsize;
unsigned char pad2d;
unsigned char bltcon0l;
unsigned short bltsizv;
unsigned short bltsizh;
unsigned short bltcmod;
unsigned short bltbmod;
unsigned short bltamod;
unsigned short bltdmod;
unsigned short spare2[4];
unsigned short bltcdat;
unsigned short bltbdat;
unsigned short bltadat;
unsigned short spare3[3];
unsigned short deniseid;
unsigned short dsksync;
unsigned short *cop1lc;
unsigned short *cop2lc;
unsigned short copjmp1;
unsigned short copjmp2;
unsigned short copins;
unsigned short diwstrt;
unsigned short diwstop;
unsigned short ddfstrt;
unsigned short ddfstop;
unsigned short dmacon;
unsigned short clxcon;
unsigned short intena;
unsigned short intreq;
unsigned short adkcon;
struct {
unsigned short *audlc;
unsigned short audlen;
unsigned short audper;
unsigned short audvol;
unsigned short auddat;
unsigned short audspare[2];
} aud[4];
unsigned char *bplpt[8];
unsigned short bplcon0;
unsigned short bplcon1;
unsigned short bplcon2;
unsigned short bplcon3;
unsigned short bpl1mod;
unsigned short bpl2mod;
unsigned short bplcon4;
unsigned short clxcon2;
unsigned short bpldat[8];
unsigned char *sprpt[8];
struct {
unsigned short pos;
unsigned short ctl;
unsigned short dataa;
unsigned short datab;
} spr[8];
unsigned short color[32];
unsigned short htotal;
unsigned short hsstop;
unsigned short hbstrt;
unsigned short hbstop;
unsigned short vtotal;
unsigned short vsstop;
unsigned short vbstrt;
unsigned short vbstop;
unsigned short sprhstrt;
unsigned short sprhstop;
unsigned short bplhstrt;
unsigned short bplhstop;
unsigned short hhposw;
unsigned short hhposr;
unsigned short beamcon0;
unsigned short hsstrt;
unsigned short vsstrt;
unsigned short hcenter;
unsigned short diwhigh;
unsigned short spare4[11];
unsigned short fmode;
};
/*
* DMA register bits
*/
#define DMAF_SETCLR (0x8000)
#define DMAF_AUD0 (0x0001)
#define DMAF_AUD1 (0x0002)
#define DMAF_AUD2 (0x0004)
#define DMAF_AUD3 (0x0008)
#define DMAF_DISK (0x0010)
#define DMAF_SPRITE (0x0020)
#define DMAF_BLITTER (0x0040)
#define DMAF_COPPER (0x0080)
#define DMAF_RASTER (0x0100)
#define DMAF_MASTER (0x0200)
#define DMAF_BLITHOG (0x0400)
#define DMAF_BLTNZERO (0x2000)
#define DMAF_BLTDONE (0x4000)
#define DMAF_ALL (0x01FF)
struct CIA {
unsigned char pra; char pad0[0xff];
unsigned char prb; char pad1[0xff];
unsigned char ddra; char pad2[0xff];
unsigned char ddrb; char pad3[0xff];
unsigned char talo; char pad4[0xff];
unsigned char tahi; char pad5[0xff];
unsigned char tblo; char pad6[0xff];
unsigned char tbhi; char pad7[0xff];
unsigned char todlo; char pad8[0xff];
unsigned char todmid; char pad9[0xff];
unsigned char todhi; char pada[0x1ff];
unsigned char sdr; char padb[0xff];
unsigned char icr; char padc[0xff];
unsigned char cra; char padd[0xff];
unsigned char crb; char pade[0xff];
};
#define zTwoBase (0x80000000)
#define ZTWO_PADDR(x) (((unsigned long)(x))-zTwoBase)
#define ZTWO_VADDR(x) ((void __iomem *)(((unsigned long)(x))+zTwoBase))
#define CUSTOM_PHYSADDR (0xdff000)
#define amiga_custom ((*(volatile struct CUSTOM *)(zTwoBase+CUSTOM_PHYSADDR)))
#define CIAA_PHYSADDR (0xbfe001)
#define CIAB_PHYSADDR (0xbfd000)
#define ciaa ((*(volatile struct CIA *)(zTwoBase + CIAA_PHYSADDR)))
#define ciab ((*(volatile struct CIA *)(zTwoBase + CIAB_PHYSADDR)))
#define CHIP_PHYSADDR (0x000000)
void amiga_chip_init (void);
void *amiga_chip_alloc(unsigned long size, const char *name);
void *amiga_chip_alloc_res(unsigned long size, struct resource *res);
void amiga_chip_free(void *ptr);
unsigned long amiga_chip_avail( void ); /*MILAN*/
extern volatile unsigned short amiga_audio_min_period;
static inline void amifb_video_off(void)
{
if (amiga_chipset == CS_ECS || amiga_chipset == CS_AGA) {
/* program Denise/Lisa for a higher maximum play rate */
amiga_custom.htotal = 113; /* 31 kHz */
amiga_custom.vtotal = 223; /* 70 Hz */
amiga_custom.beamcon0 = 0x4390; /* HARDDIS, VAR{BEAM,VSY,HSY,CSY}EN */
/* suspend the monitor */
amiga_custom.hsstrt = amiga_custom.hsstop = 116;
amiga_custom.vsstrt = amiga_custom.vsstop = 226;
amiga_audio_min_period = 57;
}
}
struct tod3000 {
unsigned int :28, second2:4; /* lower digit */
unsigned int :28, second1:4; /* upper digit */
unsigned int :28, minute2:4; /* lower digit */
unsigned int :28, minute1:4; /* upper digit */
unsigned int :28, hour2:4; /* lower digit */
unsigned int :28, hour1:4; /* upper digit */
unsigned int :28, weekday:4;
unsigned int :28, day2:4; /* lower digit */
unsigned int :28, day1:4; /* upper digit */
unsigned int :28, month2:4; /* lower digit */
unsigned int :28, month1:4; /* upper digit */
unsigned int :28, year2:4; /* lower digit */
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, cntrl1:4; /* control-byte 1 */
unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
#define TOD3000_CNTRL1_HOLD 0
#define TOD3000_CNTRL1_FREE 9
#define tod_3000 ((*(volatile struct tod3000 *)(zTwoBase+0xDC0000)))
struct tod2000 {
unsigned int :28, second2:4; /* lower digit */
unsigned int :28, second1:4; /* upper digit */
unsigned int :28, minute2:4; /* lower digit */
unsigned int :28, minute1:4; /* upper digit */
unsigned int :28, hour2:4; /* lower digit */
unsigned int :28, hour1:4; /* upper digit */
unsigned int :28, day2:4; /* lower digit */
unsigned int :28, day1:4; /* upper digit */
unsigned int :28, month2:4; /* lower digit */
unsigned int :28, month1:4; /* upper digit */
unsigned int :28, year2:4; /* lower digit */
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, weekday:4;
unsigned int :28, cntrl1:4; /* control-byte 1 */
unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
#define TOD2000_CNTRL1_HOLD (1<<0)
#define TOD2000_CNTRL1_BUSY (1<<1)
#define TOD2000_CNTRL3_24HMODE (1<<2)
#define TOD2000_HOUR1_PM (1<<2)
#define tod_2000 ((*(volatile struct tod2000 *)(zTwoBase+0xDC0000)))
#endif /* _M68K_AMIGAHW_H */

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/*
** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created 10/2/92 by Greg Harp
*/
#ifndef _ASMm68k_AMIGAINTS_H_
#define _ASMm68k_AMIGAINTS_H_
#include <asm/irq.h>
/*
** Amiga Interrupt sources.
**
*/
#define AUTO_IRQS (8)
#define AMI_STD_IRQS (14)
#define CIA_IRQS (5)
#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */
/* builtin serial port interrupts */
#define IRQ_AMIGA_TBE (IRQ_USER+0)
#define IRQ_AMIGA_RBF (IRQ_USER+11)
/* floppy disk interrupts */
#define IRQ_AMIGA_DSKBLK (IRQ_USER+1)
#define IRQ_AMIGA_DSKSYN (IRQ_USER+12)
/* software interrupts */
#define IRQ_AMIGA_SOFT (IRQ_USER+2)
/* interrupts from external hardware */
#define IRQ_AMIGA_PORTS IRQ_AUTO_2
#define IRQ_AMIGA_EXTER IRQ_AUTO_6
/* copper interrupt */
#define IRQ_AMIGA_COPPER (IRQ_USER+4)
/* vertical blanking interrupt */
#define IRQ_AMIGA_VERTB (IRQ_USER+5)
/* Blitter done interrupt */
#define IRQ_AMIGA_BLIT (IRQ_USER+6)
/* Audio interrupts */
#define IRQ_AMIGA_AUD0 (IRQ_USER+7)
#define IRQ_AMIGA_AUD1 (IRQ_USER+8)
#define IRQ_AMIGA_AUD2 (IRQ_USER+9)
#define IRQ_AMIGA_AUD3 (IRQ_USER+10)
/* CIA interrupt sources */
#define IRQ_AMIGA_CIAA (IRQ_USER+14)
#define IRQ_AMIGA_CIAA_TA (IRQ_USER+14)
#define IRQ_AMIGA_CIAA_TB (IRQ_USER+15)
#define IRQ_AMIGA_CIAA_ALRM (IRQ_USER+16)
#define IRQ_AMIGA_CIAA_SP (IRQ_USER+17)
#define IRQ_AMIGA_CIAA_FLG (IRQ_USER+18)
#define IRQ_AMIGA_CIAB (IRQ_USER+19)
#define IRQ_AMIGA_CIAB_TA (IRQ_USER+19)
#define IRQ_AMIGA_CIAB_TB (IRQ_USER+20)
#define IRQ_AMIGA_CIAB_ALRM (IRQ_USER+21)
#define IRQ_AMIGA_CIAB_SP (IRQ_USER+22)
#define IRQ_AMIGA_CIAB_FLG (IRQ_USER+23)
/* INTREQR masks */
#define IF_SETCLR 0x8000 /* set/clr bit */
#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */
#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */
#define IF_DSKSYN 0x1000 /* disk sync interrupt */
#define IF_RBF 0x0800 /* serial receive buffer full interrupt */
#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */
#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */
#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */
#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */
#define IF_BLIT 0x0040 /* blitter done interrupt */
#define IF_VERTB 0x0020 /* vertical blanking interrupt */
#define IF_COPER 0x0010 /* copper interrupt */
#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */
#define IF_SOFT 0x0004 /* software initiated interrupt */
#define IF_DSKBLK 0x0002 /* diskblock DMA finished */
#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */
/* CIA interrupt control register bits */
#define CIA_ICR_TA 0x01
#define CIA_ICR_TB 0x02
#define CIA_ICR_ALRM 0x04
#define CIA_ICR_SP 0x08
#define CIA_ICR_FLG 0x10
#define CIA_ICR_ALL 0x1f
#define CIA_ICR_SETCLR 0x80
extern void amiga_init_IRQ(void);
/* to access the interrupt control registers of CIA's use only
** these functions, they behave exactly like the amiga os routines
*/
extern struct ciabase ciaa_base, ciab_base;
extern void cia_init_IRQ(struct ciabase *base);
extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask);
extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask);
#endif /* asm-m68k/amigaints.h */

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/*
** asm-m68k/amigayle.h -- This header defines the registers of the gayle chip
** found on the Amiga 1200
** This information was found by disassembling card.resource,
** so the definitions may not be 100% correct
** anyone has an official doc ?
**
** Copyright 1997 by Alain Malek
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 11/28/97 by Alain Malek
*/
#ifndef _M68K_AMIGAYLE_H_
#define _M68K_AMIGAYLE_H_
#include <linux/types.h>
#include <asm/amigahw.h>
/* memory layout */
#define GAYLE_RAM (0x600000+zTwoBase)
#define GAYLE_RAMSIZE (0x400000)
#define GAYLE_ATTRIBUTE (0xa00000+zTwoBase)
#define GAYLE_ATTRIBUTESIZE (0x020000)
#define GAYLE_IO (0xa20000+zTwoBase) /* 16bit and even 8bit registers */
#define GAYLE_IOSIZE (0x010000)
#define GAYLE_IO_8BITODD (0xa30000+zTwoBase) /* odd 8bit registers */
/* offset for accessing odd IO registers */
#define GAYLE_ODD (GAYLE_IO_8BITODD-GAYLE_IO-1)
/* GAYLE registers */
struct GAYLE {
u_char cardstatus;
u_char pad0[0x1000-1];
u_char intreq;
u_char pad1[0x1000-1];
u_char inten;
u_char pad2[0x1000-1];
u_char config;
u_char pad3[0x1000-1];
};
#define GAYLE_ADDRESS (0xda8000) /* gayle main registers base address */
#define GAYLE_RESET (0xa40000) /* write 0x00 to start reset,
read 1 byte to stop reset */
#define gayle (*(volatile struct GAYLE *)(zTwoBase+GAYLE_ADDRESS))
#define gayle_reset (*(volatile u_char *)(zTwoBase+GAYLE_RESET))
#define gayle_attribute ((volatile u_char *)(GAYLE_ATTRIBUTE))
#if 0
#define gayle_inb(a) readb( GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
#define gayle_outb(v,a) writeb( v, GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
#define gayle_inw(a) readw( GAYLE_IO+(a) )
#define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
#endif
/* GAYLE_CARDSTATUS bit def */
#define GAYLE_CS_CCDET 0x40 /* credit card detect */
#define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */
#define GAYLE_CS_SC 0x20 /* credit card status change */
#define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */
#define GAYLE_CS_DA 0x10 /* digital audio */
#define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */
#define GAYLE_CS_BSY 0x04 /* credit card busy */
#define GAYLE_CS_IRQ 0x04 /* interrupt request */
/* GAYLE_IRQ bit def */
#define GAYLE_IRQ_IDE 0x80
#define GAYLE_IRQ_CCDET 0x40
#define GAYLE_IRQ_BVD1 0x20
#define GAYLE_IRQ_SC 0x20
#define GAYLE_IRQ_BVD2 0x10
#define GAYLE_IRQ_DA 0x10
#define GAYLE_IRQ_WR 0x08
#define GAYLE_IRQ_BSY 0x04
#define GAYLE_IRQ_IRQ 0x04
#define GAYLE_IRQ_IDEACK1 0x02
#define GAYLE_IRQ_IDEACK0 0x01
/* GAYLE_CONFIG bit def
(bit 0-1 for program voltage, bit 2-3 for access speed */
#define GAYLE_CFG_0V 0x00
#define GAYLE_CFG_5V 0x01
#define GAYLE_CFG_12V 0x02
#define GAYLE_CFG_100NS 0x08
#define GAYLE_CFG_150NS 0x04
#define GAYLE_CFG_250NS 0x00
#define GAYLE_CFG_720NS 0x0c
struct gayle_ide_platform_data {
unsigned long base;
unsigned long irqport;
int explicit_ack; /* A1200 IDE needs explicit ack */
};
#endif /* asm-m68k/amigayle.h */

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/*
** asm-m68k/pcmcia.h -- Amiga Linux PCMCIA Definitions
**
** Copyright 1997 by Alain Malek
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 12/10/97 by Alain Malek
*/
#ifndef __AMIGA_PCMCIA_H__
#define __AMIGA_PCMCIA_H__
#include <asm/amigayle.h>
/* prototypes */
void pcmcia_reset(void);
int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len);
void pcmcia_program_voltage(int voltage);
void pcmcia_access_speed(int speed);
void pcmcia_write_enable(void);
void pcmcia_write_disable(void);
static inline u_char pcmcia_read_status(void)
{
return (gayle.cardstatus & 0x7c);
}
static inline u_char pcmcia_get_intreq(void)
{
return (gayle.intreq);
}
static inline void pcmcia_ack_int(u_char intreq)
{
gayle.intreq = 0xf8;
}
static inline void pcmcia_enable_irq(void)
{
gayle.inten |= GAYLE_IRQ_IRQ;
}
static inline void pcmcia_disable_irq(void)
{
gayle.inten &= ~GAYLE_IRQ_IRQ;
}
#define PCMCIA_INSERTED (gayle.cardstatus & GAYLE_CS_CCDET)
/* valid voltages for pcmcia_ProgramVoltage */
#define PCMCIA_0V 0
#define PCMCIA_5V 5
#define PCMCIA_12V 12
/* valid speeds for pcmcia_AccessSpeed */
#define PCMCIA_SPEED_100NS 100
#define PCMCIA_SPEED_150NS 150
#define PCMCIA_SPEED_250NS 250
#define PCMCIA_SPEED_720NS 720
/* PCMCIA Tuple codes */
#define CISTPL_NULL 0x00
#define CISTPL_DEVICE 0x01
#define CISTPL_LONGLINK_CB 0x02
#define CISTPL_CONFIG_CB 0x04
#define CISTPL_CFTABLE_ENTRY_CB 0x05
#define CISTPL_LONGLINK_MFC 0x06
#define CISTPL_BAR 0x07
#define CISTPL_CHECKSUM 0x10
#define CISTPL_LONGLINK_A 0x11
#define CISTPL_LONGLINK_C 0x12
#define CISTPL_LINKTARGET 0x13
#define CISTPL_NO_LINK 0x14
#define CISTPL_VERS_1 0x15
#define CISTPL_ALTSTR 0x16
#define CISTPL_DEVICE_A 0x17
#define CISTPL_JEDEC_C 0x18
#define CISTPL_JEDEC_A 0x19
#define CISTPL_CONFIG 0x1a
#define CISTPL_CFTABLE_ENTRY 0x1b
#define CISTPL_DEVICE_OC 0x1c
#define CISTPL_DEVICE_OA 0x1d
#define CISTPL_DEVICE_GEO 0x1e
#define CISTPL_DEVICE_GEO_A 0x1f
#define CISTPL_MANFID 0x20
#define CISTPL_FUNCID 0x21
#define CISTPL_FUNCE 0x22
#define CISTPL_SWIL 0x23
#define CISTPL_END 0xff
/* FUNCID */
#define CISTPL_FUNCID_MULTI 0x00
#define CISTPL_FUNCID_MEMORY 0x01
#define CISTPL_FUNCID_SERIAL 0x02
#define CISTPL_FUNCID_PARALLEL 0x03
#define CISTPL_FUNCID_FIXED 0x04
#define CISTPL_FUNCID_VIDEO 0x05
#define CISTPL_FUNCID_NETWORK 0x06
#define CISTPL_FUNCID_AIMS 0x07
#define CISTPL_FUNCID_SCSI 0x08
#endif

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/* apollohw.h : some structures to access apollo HW */
#ifndef _ASMm68k_APOLLOHW_H_
#define _ASMm68k_APOLLOHW_H_
#include <linux/types.h>
#include <asm/bootinfo-apollo.h>
extern u_long apollo_model;
/*
see scn2681 data sheet for more info.
member names are read_write.
*/
#define DECLARE_2681_FIELD(x) unsigned char x; unsigned char dummy##x
struct SCN2681 {
DECLARE_2681_FIELD(mra);
DECLARE_2681_FIELD(sra_csra);
DECLARE_2681_FIELD(BRGtest_cra);
DECLARE_2681_FIELD(rhra_thra);
DECLARE_2681_FIELD(ipcr_acr);
DECLARE_2681_FIELD(isr_imr);
DECLARE_2681_FIELD(ctu_ctur);
DECLARE_2681_FIELD(ctl_ctlr);
DECLARE_2681_FIELD(mrb);
DECLARE_2681_FIELD(srb_csrb);
DECLARE_2681_FIELD(tst_crb);
DECLARE_2681_FIELD(rhrb_thrb);
DECLARE_2681_FIELD(reserved);
DECLARE_2681_FIELD(ip_opcr);
DECLARE_2681_FIELD(startCnt_setOutBit);
DECLARE_2681_FIELD(stopCnt_resetOutBit);
};
struct mc146818 {
unsigned char second, alarm_second;
unsigned char minute, alarm_minute;
unsigned char hours, alarm_hours;
unsigned char day_of_week, day_of_month;
unsigned char month, year;
};
#define IO_BASE 0x80000000
extern u_long sio01_physaddr;
extern u_long sio23_physaddr;
extern u_long rtc_physaddr;
extern u_long pica_physaddr;
extern u_long picb_physaddr;
extern u_long cpuctrl_physaddr;
extern u_long timer_physaddr;
#define SAU7_SIO01_PHYSADDR 0x10400
#define SAU7_SIO23_PHYSADDR 0x10500
#define SAU7_RTC_PHYSADDR 0x10900
#define SAU7_PICA 0x11000
#define SAU7_PICB 0x11100
#define SAU7_CPUCTRL 0x10100
#define SAU7_TIMER 0x010800
#define SAU8_SIO01_PHYSADDR 0x8400
#define SAU8_RTC_PHYSADDR 0x8900
#define SAU8_PICA 0x9400
#define SAU8_PICB 0x9500
#define SAU8_CPUCTRL 0x8100
#define SAU8_TIMER 0x8800
#define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr)))
#define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr)))
#define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr)))
#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
#define pica (IO_BASE + pica_physaddr)
#define picb (IO_BASE + picb_physaddr)
#define apollo_timer (IO_BASE + timer_physaddr)
#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
#define IRQ_APOLLO IRQ_USER
#endif

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#include <generated/asm-offsets.h>

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#ifndef _ASM_M68K_FD_H
#define _ASM_M68K_FD_H
/* Definitions for the Atari Floppy driver */
struct atari_format_descr {
int track; /* to be formatted */
int head; /* "" "" */
int sect_offset; /* offset of first sector */
};
#endif

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#ifndef _LINUX_FDREG_H
#define _LINUX_FDREG_H
/*
** WD1772 stuff
*/
/* register codes */
#define FDCSELREG_STP (0x80) /* command/status register */
#define FDCSELREG_TRA (0x82) /* track register */
#define FDCSELREG_SEC (0x84) /* sector register */
#define FDCSELREG_DTA (0x86) /* data register */
/* register names for FDC_READ/WRITE macros */
#define FDCREG_CMD 0
#define FDCREG_STATUS 0
#define FDCREG_TRACK 2
#define FDCREG_SECTOR 4
#define FDCREG_DATA 6
/* command opcodes */
#define FDCCMD_RESTORE (0x00) /* - */
#define FDCCMD_SEEK (0x10) /* | */
#define FDCCMD_STEP (0x20) /* | TYP 1 Commands */
#define FDCCMD_STIN (0x40) /* | */
#define FDCCMD_STOT (0x60) /* - */
#define FDCCMD_RDSEC (0x80) /* - TYP 2 Commands */
#define FDCCMD_WRSEC (0xa0) /* - " */
#define FDCCMD_RDADR (0xc0) /* - */
#define FDCCMD_RDTRA (0xe0) /* | TYP 3 Commands */
#define FDCCMD_WRTRA (0xf0) /* - */
#define FDCCMD_FORCI (0xd0) /* - TYP 4 Command */
/* command modifier bits */
#define FDCCMDADD_SR6 (0x00) /* step rate settings */
#define FDCCMDADD_SR12 (0x01)
#define FDCCMDADD_SR2 (0x02)
#define FDCCMDADD_SR3 (0x03)
#define FDCCMDADD_V (0x04) /* verify */
#define FDCCMDADD_H (0x08) /* wait for spin-up */
#define FDCCMDADD_U (0x10) /* update track register */
#define FDCCMDADD_M (0x10) /* multiple sector access */
#define FDCCMDADD_E (0x04) /* head settling flag */
#define FDCCMDADD_P (0x02) /* precompensation off */
#define FDCCMDADD_A0 (0x01) /* DAM flag */
/* status register bits */
#define FDCSTAT_MOTORON (0x80) /* motor on */
#define FDCSTAT_WPROT (0x40) /* write protected (FDCCMD_WR*) */
#define FDCSTAT_SPINUP (0x20) /* motor speed stable (Type I) */
#define FDCSTAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */
#define FDCSTAT_RECNF (0x10) /* record not found */
#define FDCSTAT_CRC (0x08) /* CRC error */
#define FDCSTAT_TR00 (0x04) /* Track 00 flag (Type I) */
#define FDCSTAT_LOST (0x04) /* Lost Data (Type II+III) */
#define FDCSTAT_IDX (0x02) /* Index status (Type I) */
#define FDCSTAT_DRQ (0x02) /* DRQ status (Type II+III) */
#define FDCSTAT_BUSY (0x01) /* FDC is busy */
/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
#define DSKSIDE (0x01)
#define DSKDRVNONE (0x06)
#define DSKDRV0 (0x02)
#define DSKDRV1 (0x04)
/* step rates */
#define FDCSTEP_6 0x00
#define FDCSTEP_12 0x01
#define FDCSTEP_2 0x02
#define FDCSTEP_3 0x03
#endif

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#ifndef _LINUX_ATARI_JOYSTICK_H
#define _LINUX_ATARI_JOYSTICK_H
/*
* linux/include/linux/atari_joystick.h
* header file for Atari Joystick driver
* by Robert de Vries (robert@and.nl) on 19Jul93
*/
void atari_joystick_interrupt(char*);
int atari_joystick_init(void);
extern int atari_mouse_buttons;
struct joystick_status {
char fire;
char dir;
int ready;
int active;
wait_queue_head_t wait;
};
#endif

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#ifndef _atari_stdma_h
#define _atari_stdma_h
#include <linux/interrupt.h>
/***************************** Prototypes *****************************/
void stdma_lock(irq_handler_t handler, void *data);
void stdma_release( void );
int stdma_others_waiting( void );
int stdma_islocked( void );
void *stdma_locked_by( void );
void stdma_init( void );
/************************* End of Prototypes **************************/
#endif /* _atari_stdma_h */

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#ifndef _M68K_ATARI_STRAM_H
#define _M68K_ATARI_STRAM_H
/*
* Functions for Atari ST-RAM management
*/
/* public interface */
void *atari_stram_alloc(unsigned long size, const char *owner);
void atari_stram_free(void *);
void *atari_stram_to_virt(unsigned long phys);
unsigned long atari_stram_to_phys(void *);
/* functions called internally by other parts of the kernel */
void atari_stram_init(void);
void atari_stram_reserve_pages(void *start_mem);
#endif /*_M68K_ATARI_STRAM_H */

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/*
** linux/atarihw.h -- This header defines some macros and pointers for
** the various Atari custom hardware registers.
**
** Copyright 1994 by Björn Brauel
**
** 5/1/94 Roman Hodek:
** Added definitions for TT specific chips.
**
** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
** Finally added definitions for the matrix/codec and the DSP56001 host
** interface.
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _LINUX_ATARIHW_H_
#define _LINUX_ATARIHW_H_
#include <linux/types.h>
#include <asm/bootinfo-atari.h>
#include <asm/raw_io.h>
extern u_long atari_mch_cookie;
extern u_long atari_mch_type;
extern u_long atari_switches;
extern int atari_rtc_year_offset;
extern int atari_dont_touch_floppy_select;
extern int atari_SCC_reset_done;
/* convenience macros for testing machine type */
#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
(atari_mch_cookie & 0xffff) == 0)
#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
(atari_mch_cookie & 0xffff) == 0x10)
#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
/* values for atari_switches */
#define ATARI_SWITCH_IKBD 0x01
#define ATARI_SWITCH_MIDI 0x02
#define ATARI_SWITCH_SND6 0x04
#define ATARI_SWITCH_SND7 0x08
#define ATARI_SWITCH_OVSC_SHIFT 16
#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_MASK 0xffff0000
/*
* Define several Hardware-Chips for indication so that for the ATARI we do
* no longer decide whether it is a Falcon or other machine . It's just
* important what hardware the machine uses
*/
/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
#define ATARIHW_DECLARE(name) unsigned name : 1
#define ATARIHW_SET(name) (atari_hw_present.name = 1)
#define ATARIHW_PRESENT(name) (atari_hw_present.name)
struct atari_hw_present {
/* video hardware */
ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
/* sound hardware */
ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
/* disk storage interfaces */
ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
ATARIHW_DECLARE(IDE); /* IDE Interface */
ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
/* other I/O hardware */
ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari
without it... but who knows?) */
ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
and Falcon */
ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
/* DMA */
ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
/* real time clocks */
ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
/* supporting hardware */
ATARIHW_DECLARE(SCU); /* System Control Unit */
ATARIHW_DECLARE(BLITTER); /* Blitter */
ATARIHW_DECLARE(VME); /* VME Bus */
ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */
};
extern struct atari_hw_present atari_hw_present;
/* Reading the MFP port register gives a machine independent delay, since the
* MFP always has a 8 MHz clock. This avoids problems with the varying length
* of nops on various machines. Somebody claimed that the tstb takes 600 ns.
*/
#define MFPDELAY() \
__asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" );
/* Do cache push/invalidate for DMA read/write. This function obeys the
* snooping on some machines (Medusa) and processors: The Medusa itself can
* snoop, but only the '040 can source data from its cache to DMA writes i.e.,
* reads from memory). Both '040 and '060 invalidate cache entries on snooped
* DMA reads (i.e., writes to memory).
*/
#define atari_readb raw_inb
#define atari_writeb raw_outb
#define atari_inb_p raw_inb
#define atari_outb_p raw_outb
#include <linux/mm.h>
#include <asm/cacheflush.h>
static inline void dma_cache_maintenance( unsigned long paddr,
unsigned long len,
int writeflag )
{
if (writeflag) {
if (!MACH_IS_MEDUSA || CPU_IS_060)
cache_push( paddr, len );
}
else {
if (!MACH_IS_MEDUSA)
cache_clear( paddr, len );
}
}
/*
** Shifter
*/
#define ST_LOW 0
#define ST_MID 1
#define ST_HIGH 2
#define TT_LOW 7
#define TT_MID 4
#define TT_HIGH 6
#define SHF_BAS (0xffff8200)
struct SHIFTER
{
u_char pad1;
u_char bas_hi;
u_char pad2;
u_char bas_md;
u_char pad3;
u_char volatile vcounthi;
u_char pad4;
u_char volatile vcountmid;
u_char pad5;
u_char volatile vcountlow;
u_char volatile syncmode;
u_char pad6;
u_char pad7;
u_char bas_lo;
};
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
#define SHF_FBAS (0xffff820e)
struct SHIFTER_F030
{
u_short off_next;
u_short scn_width;
};
# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
#define SHF_TBAS (0xffff8200)
struct SHIFTER_TT {
u_char char_dummy0;
u_char bas_hi; /* video mem base addr, high and mid byte */
u_char char_dummy1;
u_char bas_md;
u_char char_dummy2;
u_char vcount_hi; /* pointer to currently displayed byte */
u_char char_dummy3;
u_char vcount_md;
u_char char_dummy4;
u_char vcount_lo;
u_short st_sync; /* ST compatible sync mode register, unused */
u_char char_dummy5;
u_char bas_lo; /* video mem addr, low byte */
u_char char_dummy6[2+3*16];
/* $ffff8240: */
u_short color_reg[16]; /* 16 color registers */
u_char st_shiftmode; /* ST compatible shift mode register, unused */
u_char char_dummy7;
u_short tt_shiftmode; /* TT shift mode register */
};
#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
/* values for shifter_tt->tt_shiftmode */
#define TT_SHIFTER_STLOW 0x0000
#define TT_SHIFTER_STMID 0x0100
#define TT_SHIFTER_STHIGH 0x0200
#define TT_SHIFTER_TTLOW 0x0700
#define TT_SHIFTER_TTMID 0x0400
#define TT_SHIFTER_TTHIGH 0x0600
#define TT_SHIFTER_MODEMASK 0x0700
#define TT_SHIFTER_NUMMODE 0x0008
#define TT_SHIFTER_PALETTE_MASK 0x000f
#define TT_SHIFTER_GRAYMODE 0x1000
/* 256 TT palette registers */
#define TT_PALETTE_BASE (0xffff8400)
#define tt_palette ((volatile u_short *)TT_PALETTE_BASE)
#define TT_PALETTE_RED_MASK 0x0f00
#define TT_PALETTE_GREEN_MASK 0x00f0
#define TT_PALETTE_BLUE_MASK 0x000f
/*
** Falcon030 VIDEL Video Controller
** for description see File 'linux\tools\atari\hardware.txt
*/
#define f030_col ((u_long *) 0xffff9800)
#define f030_xreg ((u_short*) 0xffff8282)
#define f030_yreg ((u_short*) 0xffff82a2)
#define f030_creg ((u_short*) 0xffff82c0)
#define f030_sreg ((u_short*) 0xffff8260)
#define f030_mreg ((u_short*) 0xffff820a)
#define f030_linewidth ((u_short*) 0xffff820e)
#define f030_hscroll ((u_char*) 0xffff8265)
#define VIDEL_BAS (0xffff8260)
struct VIDEL {
u_short st_shift;
u_short pad1;
u_char xoffset_s;
u_char xoffset;
u_short f_shift;
u_char pad2[0x1a];
u_short hht;
u_short hbb;
u_short hbe;
u_short hdb;
u_short hde;
u_short hss;
u_char pad3[0x14];
u_short vft;
u_short vbb;
u_short vbe;
u_short vdb;
u_short vde;
u_short vss;
u_char pad4[0x12];
u_short control;
u_short mode;
};
#define videl ((*(volatile struct VIDEL *)VIDEL_BAS))
/*
** DMA/WD1772 Disk Controller
*/
#define FWD_BAS (0xffff8604)
struct DMA_WD
{
u_short fdc_acces_seccount;
u_short dma_mode_status;
u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */
u_char dma_hi;
u_char char_dummy2;
u_char dma_md;
u_char char_dummy3;
u_char dma_lo;
u_short fdc_speed;
};
# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
/* alias */
#define st_dma dma_wd
/* The two highest bytes of an extended DMA as a short; this is a must
* for the Medusa.
*/
#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
/*
** YM2149 Sound Chip
** access in bytes
*/
#define YM_BAS (0xffff8800)
struct SOUND_YM
{
u_char rd_data_reg_sel;
u_char char_dummy1;
u_char wd_data;
};
#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
/* TT SCSI DMA */
#define TT_SCSI_DMA_BAS (0xffff8700)
struct TT_DMA {
u_char char_dummy0;
u_char dma_addr_hi;
u_char char_dummy1;
u_char dma_addr_hmd;
u_char char_dummy2;
u_char dma_addr_lmd;
u_char char_dummy3;
u_char dma_addr_lo;
u_char char_dummy4;
u_char dma_cnt_hi;
u_char char_dummy5;
u_char dma_cnt_hmd;
u_char char_dummy6;
u_char dma_cnt_lmd;
u_char char_dummy7;
u_char dma_cnt_lo;
u_long dma_restdata;
u_short dma_ctrl;
};
#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
/* TT SCSI Controller 5380 */
#define TT_5380_BAS (0xffff8781)
struct TT_5380 {
u_char scsi_data;
u_char char_dummy1;
u_char scsi_icr;
u_char char_dummy2;
u_char scsi_mode;
u_char char_dummy3;
u_char scsi_tcr;
u_char char_dummy4;
u_char scsi_idstat;
u_char char_dummy5;
u_char scsi_dmastat;
u_char char_dummy6;
u_char scsi_targrcv;
u_char char_dummy7;
u_char scsi_inircv;
};
#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS))
#define tt_scsi_regp ((volatile char *)TT_5380_BAS)
/*
** Falcon DMA Sound Subsystem
*/
#define MATRIX_BASE (0xffff8930)
struct MATRIX
{
u_short source;
u_short destination;
u_char external_frequency_divider;
u_char internal_frequency_divider;
};
#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE)
#define CODEC_BASE (0xffff8936)
struct CODEC
{
u_char tracks;
u_char input_source;
#define CODEC_SOURCE_ADC 1
#define CODEC_SOURCE_MATRIX 2
u_char adc_source;
#define ADC_SOURCE_RIGHT_PSG 1
#define ADC_SOURCE_LEFT_PSG 2
u_char gain;
#define CODEC_GAIN_RIGHT 0x0f
#define CODEC_GAIN_LEFT 0xf0
u_char attenuation;
#define CODEC_ATTENUATION_RIGHT 0x0f
#define CODEC_ATTENUATION_LEFT 0xf0
u_char unused1;
u_char status;
#define CODEC_OVERFLOW_RIGHT 1
#define CODEC_OVERFLOW_LEFT 2
u_char unused2, unused3, unused4, unused5;
u_char gpio_directions;
#define CODEC_GPIO_IN 0
#define CODEC_GPIO_OUT 1
u_char unused6;
u_char gpio_data;
};
#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE)
/*
** Falcon Blitter
*/
#define BLT_BAS (0xffff8a00)
struct BLITTER
{
u_short halftone[16];
u_short src_x_inc;
u_short src_y_inc;
u_long src_address;
u_short endmask1;
u_short endmask2;
u_short endmask3;
u_short dst_x_inc;
u_short dst_y_inc;
u_long dst_address;
u_short wd_per_line;
u_short ln_per_bb;
u_short hlf_op_reg;
u_short log_op_reg;
u_short lin_nm_reg;
u_short skew_reg;
};
# define blitter ((*(volatile struct BLITTER *)BLT_BAS))
/*
** SCC Z8530
*/
#define SCC_BAS (0xffff8c81)
struct SCC
{
u_char cha_a_ctrl;
u_char char_dummy1;
u_char cha_a_data;
u_char char_dummy2;
u_char cha_b_ctrl;
u_char char_dummy3;
u_char cha_b_data;
};
# define atari_scc ((*(volatile struct SCC*)SCC_BAS))
/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
# define st_escc ((*(volatile struct SCC*)0xfffffa31))
# define st_escc_dsr ((*(volatile char *)0xfffffa39))
/* TT SCC DMA Controller (same chip as SCSI DMA) */
#define TT_SCC_DMA_BAS (0xffff8c00)
#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
/*
** VIDEL Palette Register
*/
#define FPL_BAS (0xffff9800)
struct VIDEL_PALETTE
{
u_long reg[256];
};
# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
/*
** Falcon DSP Host Interface
*/
#define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
struct DSP56K_HOST_INTERFACE {
u_char icr;
#define DSP56K_ICR_RREQ 0x01
#define DSP56K_ICR_TREQ 0x02
#define DSP56K_ICR_HF0 0x08
#define DSP56K_ICR_HF1 0x10
#define DSP56K_ICR_HM0 0x20
#define DSP56K_ICR_HM1 0x40
#define DSP56K_ICR_INIT 0x80
u_char cvr;
#define DSP56K_CVR_HV_MASK 0x1f
#define DSP56K_CVR_HC 0x80
u_char isr;
#define DSP56K_ISR_RXDF 0x01
#define DSP56K_ISR_TXDE 0x02
#define DSP56K_ISR_TRDY 0x04
#define DSP56K_ISR_HF2 0x08
#define DSP56K_ISR_HF3 0x10
#define DSP56K_ISR_DMA 0x40
#define DSP56K_ISR_HREQ 0x80
u_char ivr;
union {
u_char b[4];
u_short w[2];
u_long l;
} data;
};
#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
/*
** MFP 68901
*/
#define MFP_BAS (0xfffffa01)
struct MFP
{
u_char par_dt_reg;
u_char char_dummy1;
u_char active_edge;
u_char char_dummy2;
u_char data_dir;
u_char char_dummy3;
u_char int_en_a;
u_char char_dummy4;
u_char int_en_b;
u_char char_dummy5;
u_char int_pn_a;
u_char char_dummy6;
u_char int_pn_b;
u_char char_dummy7;
u_char int_sv_a;
u_char char_dummy8;
u_char int_sv_b;
u_char char_dummy9;
u_char int_mk_a;
u_char char_dummy10;
u_char int_mk_b;
u_char char_dummy11;
u_char vec_adr;
u_char char_dummy12;
u_char tim_ct_a;
u_char char_dummy13;
u_char tim_ct_b;
u_char char_dummy14;
u_char tim_ct_cd;
u_char char_dummy15;
u_char tim_dt_a;
u_char char_dummy16;
u_char tim_dt_b;
u_char char_dummy17;
u_char tim_dt_c;
u_char char_dummy18;
u_char tim_dt_d;
u_char char_dummy19;
u_char sync_char;
u_char char_dummy20;
u_char usart_ctr;
u_char char_dummy21;
u_char rcv_stat;
u_char char_dummy22;
u_char trn_stat;
u_char char_dummy23;
u_char usart_dta;
};
# define st_mfp ((*(volatile struct MFP*)MFP_BAS))
/* TT's second MFP */
#define TT_MFP_BAS (0xfffffa81)
# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
/* TT System Control Unit */
#define TT_SCU_BAS (0xffff8e01)
struct TT_SCU {
u_char sys_mask;
u_char char_dummy1;
u_char sys_stat;
u_char char_dummy2;
u_char softint;
u_char char_dummy3;
u_char vmeint;
u_char char_dummy4;
u_char gp_reg1;
u_char char_dummy5;
u_char gp_reg2;
u_char char_dummy6;
u_char vme_mask;
u_char char_dummy7;
u_char vme_stat;
};
#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS))
/* TT real time clock */
#define TT_RTC_BAS (0xffff8961)
struct TT_RTC {
u_char regsel;
u_char dummy;
u_char data;
};
#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS))
/*
** ACIA 6850
*/
/* constants for the ACIA registers */
/* baudrate selection and reset (Baudrate = clock/factor) */
#define ACIA_DIV1 0
#define ACIA_DIV16 1
#define ACIA_DIV64 2
#define ACIA_RESET 3
/* character format */
#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */
#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */
#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */
#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */
#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */
#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */
#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */
#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */
/* transmit control */
#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */
#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */
#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */
#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */
/* receive control */
#define ACIA_RID (0<<7) /* RxINT disabled */
#define ACIA_RIE (1<<7) /* RxINT enabled */
/* status fields of the ACIA */
#define ACIA_RDRF 1 /* Receive Data Register Full */
#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */
#define ACIA_DCD (1<<2) /* Data Carrier Detect */
#define ACIA_CTS (1<<3) /* Clear To Send */
#define ACIA_FE (1<<4) /* Framing Error */
#define ACIA_OVRN (1<<5) /* Receiver Overrun */
#define ACIA_PE (1<<6) /* Parity Error */
#define ACIA_IRQ (1<<7) /* Interrupt Request */
#define ACIA_BAS (0xfffffc00)
struct ACIA
{
u_char key_ctrl;
u_char char_dummy1;
u_char key_data;
u_char char_dummy2;
u_char mid_ctrl;
u_char char_dummy3;
u_char mid_data;
};
# define acia ((*(volatile struct ACIA*)ACIA_BAS))
#define TT_DMASND_BAS (0xffff8900)
struct TT_DMASND {
u_char int_ctrl; /* Falcon: Interrupt control */
u_char ctrl;
u_char pad2;
u_char bas_hi;
u_char pad3;
u_char bas_mid;
u_char pad4;
u_char bas_low;
u_char pad5;
u_char addr_hi;
u_char pad6;
u_char addr_mid;
u_char pad7;
u_char addr_low;
u_char pad8;
u_char end_hi;
u_char pad9;
u_char end_mid;
u_char pad10;
u_char end_low;
u_char pad11[12];
u_char track_select; /* Falcon */
u_char mode;
u_char pad12[14];
/* Falcon only: */
u_short cbar_src;
u_short cbar_dst;
u_char ext_div;
u_char int_div;
u_char rec_track_select;
u_char dac_src;
u_char adc_src;
u_char input_gain;
u_short output_atten;
};
# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
#define DMASND_MFP_INT_REPLAY 0x01
#define DMASND_MFP_INT_RECORD 0x02
#define DMASND_TIMERA_INT_REPLAY 0x04
#define DMASND_TIMERA_INT_RECORD 0x08
#define DMASND_CTRL_OFF 0x00
#define DMASND_CTRL_ON 0x01
#define DMASND_CTRL_REPEAT 0x02
#define DMASND_CTRL_RECORD_ON 0x10
#define DMASND_CTRL_RECORD_OFF 0x00
#define DMASND_CTRL_RECORD_REPEAT 0x20
#define DMASND_CTRL_SELECT_REPLAY 0x00
#define DMASND_CTRL_SELECT_RECORD 0x80
#define DMASND_MODE_MONO 0x80
#define DMASND_MODE_STEREO 0x00
#define DMASND_MODE_8BIT 0x00
#define DMASND_MODE_16BIT 0x40 /* Falcon only */
#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */
#define DMASND_MODE_12KHZ 0x01
#define DMASND_MODE_25KHZ 0x02
#define DMASND_MODE_50KHZ 0x03
#define DMASNDSetBase(bufstart) \
do { \
tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
} while( 0 )
#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \
(tt_dmasnd.addr_mid << 8) + \
(tt_dmasnd.addr_low))
#define DMASNDSetEnd(bufend) \
do { \
tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \
tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
} while( 0 )
#define TT_MICROWIRE_BAS (0xffff8922)
struct TT_MICROWIRE {
u_short data;
u_short mask;
};
# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
#define MW_LM1992_ADDR 0x0400
#define MW_LM1992_VOLUME(dB) \
(0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
#define MW_LM1992_BALLEFT(dB) \
(0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
#define MW_LM1992_BALRIGHT(dB) \
(0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
#define MW_LM1992_TREBLE(dB) \
(0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
#define MW_LM1992_BASS(dB) \
(0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
#define MW_LM1992_PSG_LOW 0x000
#define MW_LM1992_PSG_HIGH 0x001
#define MW_LM1992_PSG_OFF 0x002
#define MSTE_RTC_BAS (0xfffffc21)
struct MSTE_RTC {
u_char sec_ones;
u_char dummy1;
u_char sec_tens;
u_char dummy2;
u_char min_ones;
u_char dummy3;
u_char min_tens;
u_char dummy4;
u_char hr_ones;
u_char dummy5;
u_char hr_tens;
u_char dummy6;
u_char weekday;
u_char dummy7;
u_char day_ones;
u_char dummy8;
u_char day_tens;
u_char dummy9;
u_char mon_ones;
u_char dummy10;
u_char mon_tens;
u_char dummy11;
u_char year_ones;
u_char dummy12;
u_char year_tens;
u_char dummy13;
u_char mode;
u_char dummy14;
u_char test;
u_char dummy15;
u_char reset;
};
#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
/*
** EtherNAT add-on card for Falcon - combined ethernet and USB adapter
*/
#define ATARI_ETHERNAT_PHYS_ADDR 0x80000000
#endif /* linux/atarihw.h */

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/*
** atariints.h -- Atari Linux interrupt handling structs and prototypes
**
** Copyright 1994 by Björn Brauel
**
** 5/2/94 Roman Hodek:
** TT interrupt definitions added.
**
** 12/02/96: (Roman)
** Adapted to new int handling scheme (see ataints.c); revised numbering
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _LINUX_ATARIINTS_H_
#define _LINUX_ATARIINTS_H_
#include <asm/irq.h>
#include <asm/atarihw.h>
/*
** Atari Interrupt sources.
**
*/
#define STMFP_SOURCE_BASE 8
#define TTMFP_SOURCE_BASE 24
#define SCC_SOURCE_BASE 40
#define VME_SOURCE_BASE 56
#define VME_MAX_SOURCES 16
#define NUM_ATARI_SOURCES 141
/* convert vector number to int source number */
#define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8)))
/* convert irq_handler index to vector number */
#define IRQ_SOURCE_TO_VECTOR(i) ((i) + ((i) < 8 ? 0x18 : (0x40-8)))
/* interrupt service types */
#define IRQ_TYPE_SLOW 0
#define IRQ_TYPE_FAST 1
#define IRQ_TYPE_PRIO 2
/* ST-MFP interrupts */
#define IRQ_MFP_BUSY (8)
#define IRQ_MFP_DCD (9)
#define IRQ_MFP_CTS (10)
#define IRQ_MFP_GPU (11)
#define IRQ_MFP_TIMD (12)
#define IRQ_MFP_TIMC (13)
#define IRQ_MFP_ACIA (14)
#define IRQ_MFP_FDC (15)
#define IRQ_MFP_ACSI IRQ_MFP_FDC
#define IRQ_MFP_FSCSI IRQ_MFP_FDC
#define IRQ_MFP_IDE IRQ_MFP_FDC
#define IRQ_MFP_TIMB (16)
#define IRQ_MFP_SERERR (17)
#define IRQ_MFP_SEREMPT (18)
#define IRQ_MFP_RECERR (19)
#define IRQ_MFP_RECFULL (20)
#define IRQ_MFP_TIMA (21)
#define IRQ_MFP_RI (22)
#define IRQ_MFP_MMD (23)
/* TT-MFP interrupts */
#define IRQ_TT_MFP_IO0 (24)
#define IRQ_TT_MFP_IO1 (25)
#define IRQ_TT_MFP_SCC (26)
#define IRQ_TT_MFP_RI (27)
#define IRQ_TT_MFP_TIMD (28)
#define IRQ_TT_MFP_TIMC (29)
#define IRQ_TT_MFP_DRVRDY (30)
#define IRQ_TT_MFP_SCSIDMA (31)
#define IRQ_TT_MFP_TIMB (32)
#define IRQ_TT_MFP_SERERR (33)
#define IRQ_TT_MFP_SEREMPT (34)
#define IRQ_TT_MFP_RECERR (35)
#define IRQ_TT_MFP_RECFULL (36)
#define IRQ_TT_MFP_TIMA (37)
#define IRQ_TT_MFP_RTC (38)
#define IRQ_TT_MFP_SCSI (39)
/* SCC interrupts */
#define IRQ_SCCB_TX (40)
#define IRQ_SCCB_STAT (42)
#define IRQ_SCCB_RX (44)
#define IRQ_SCCB_SPCOND (46)
#define IRQ_SCCA_TX (48)
#define IRQ_SCCA_STAT (50)
#define IRQ_SCCA_RX (52)
#define IRQ_SCCA_SPCOND (54)
/* shared MFP timer D interrupts - hires timer for EtherNEC et al. */
#define IRQ_MFP_TIMER1 (64)
#define IRQ_MFP_TIMER2 (65)
#define IRQ_MFP_TIMER3 (66)
#define IRQ_MFP_TIMER4 (67)
#define IRQ_MFP_TIMER5 (68)
#define IRQ_MFP_TIMER6 (69)
#define IRQ_MFP_TIMER7 (70)
#define IRQ_MFP_TIMER8 (71)
#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
#define MFP_ENABLE 0
#define MFP_PENDING 1
#define MFP_SERVICE 2
#define MFP_MASK 3
/* Utility functions for setting/clearing bits in the interrupt registers of
* the MFP. 'type' should be constant, if 'irq' is constant, too, code size is
* reduced. set_mfp_bit() is nonsense for PENDING and SERVICE registers. */
static inline int get_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = 1 << (irq & 7);
reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
return( *reg & mask );
}
static inline void set_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = 1 << (irq & 7);
reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
__asm__ __volatile__ ( "orb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
}
static inline void clear_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
mask = ~(1 << (irq & 7));
reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
if (type == MFP_PENDING || type == MFP_SERVICE)
__asm__ __volatile__ ( "moveb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
else
__asm__ __volatile__ ( "andb %0,%1"
: : "di" (mask), "m" (*reg) : "memory" );
}
/*
* {en,dis}able_irq have the usual semantics of temporary blocking the
* interrupt, but not losing requests that happen between disabling and
* enabling. This is done with the MFP mask registers.
*/
static inline void atari_enable_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
set_mfp_bit( irq, MFP_MASK );
}
static inline void atari_disable_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_MASK );
}
/*
* In opposite to {en,dis}able_irq, requests between turn{off,on}_irq are not
* "stored"
*/
static inline void atari_turnon_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
set_mfp_bit( irq, MFP_ENABLE );
}
static inline void atari_turnoff_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_ENABLE );
clear_mfp_bit( irq, MFP_PENDING );
}
static inline void atari_clear_pending_irq( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
clear_mfp_bit( irq, MFP_PENDING );
}
static inline int atari_irq_pending( unsigned irq )
{
if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return( 0 );
return( get_mfp_bit( irq, MFP_PENDING ) );
}
unsigned int atari_register_vme_int(void);
void atari_unregister_vme_int(unsigned int);
#endif /* linux/atariints.h */

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/*
** atarikb.h -- This header contains the prototypes of functions of
** the intelligent keyboard of the Atari needed by the
** mouse and joystick drivers.
**
** Copyright 1994 by Robert de Vries
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 20 Feb 1994 by Robert de Vries
*/
#ifndef _LINUX_ATARIKB_H
#define _LINUX_ATARIKB_H
void ikbd_write(const char *, int);
void ikbd_mouse_button_action(int mode);
void ikbd_mouse_rel_pos(void);
void ikbd_mouse_abs_pos(int xmax, int ymax);
void ikbd_mouse_kbd_mode(int dx, int dy);
void ikbd_mouse_thresh(int x, int y);
void ikbd_mouse_scale(int x, int y);
void ikbd_mouse_pos_get(int *x, int *y);
void ikbd_mouse_pos_set(int x, int y);
void ikbd_mouse_y0_bot(void);
void ikbd_mouse_y0_top(void);
void ikbd_mouse_disable(void);
void ikbd_joystick_event_on(void);
void ikbd_joystick_event_off(void);
void ikbd_joystick_get_state(void);
void ikbd_joystick_disable(void);
/* Hook for MIDI serial driver */
extern void (*atari_MIDI_interrupt_hook) (void);
/* Hook for keyboard inputdev driver */
extern void (*atari_input_keyboard_interrupt_hook) (unsigned char, char);
/* Hook for mouse inputdev driver */
extern void (*atari_input_mouse_interrupt_hook) (char *);
int atari_keyb_init(void);
#endif /* _LINUX_ATARIKB_H */

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#ifndef __ARCH_M68K_ATOMIC__
#define __ARCH_M68K_ATOMIC__
#include <linux/types.h>
#include <linux/irqflags.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/
/*
* We do not have SMP m68k systems, so we don't have to deal with that.
*/
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ACCESS_ONCE((v)->counter)
#define atomic_set(v, i) (((v)->counter) = i)
/*
* The ColdFire parts cannot do some immediate to memory operations,
* so for them we do not specify the "i" asm constraint.
*/
#ifdef CONFIG_COLDFIRE
#define ASM_DI "d"
#else
#define ASM_DI "di"
#endif
#define ATOMIC_OP(op, c_op, asm_op) \
static inline void atomic_##op(int i, atomic_t *v) \
{ \
__asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
} \
#ifdef CONFIG_RMW_INSNS
#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
static inline int atomic_##op##_return(int i, atomic_t *v) \
{ \
int t, tmp; \
\
__asm__ __volatile__( \
"1: movel %2,%1\n" \
" " #asm_op "l %3,%1\n" \
" casl %2,%1,%0\n" \
" jne 1b" \
: "+m" (*v), "=&d" (t), "=&d" (tmp) \
: "g" (i), "2" (atomic_read(v))); \
return t; \
}
#else
#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
static inline int atomic_##op##_return(int i, atomic_t * v) \
{ \
unsigned long flags; \
int t; \
\
local_irq_save(flags); \
t = (v->counter c_op i); \
local_irq_restore(flags); \
\
return t; \
}
#endif /* CONFIG_RMW_INSNS */
#define ATOMIC_OPS(op, c_op, asm_op) \
ATOMIC_OP(op, c_op, asm_op) \
ATOMIC_OP_RETURN(op, c_op, asm_op)
ATOMIC_OPS(add, +=, add)
ATOMIC_OPS(sub, -=, sub)
#undef ATOMIC_OPS
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP
static inline void atomic_inc(atomic_t *v)
{
__asm__ __volatile__("addql #1,%0" : "+m" (*v));
}
static inline void atomic_dec(atomic_t *v)
{
__asm__ __volatile__("subql #1,%0" : "+m" (*v));
}
static inline int atomic_dec_and_test(atomic_t *v)
{
char c;
__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
static inline int atomic_dec_and_test_lt(atomic_t *v)
{
char c;
__asm__ __volatile__(
"subql #1,%1; slt %0"
: "=d" (c), "=m" (*v)
: "m" (*v));
return c != 0;
}
static inline int atomic_inc_and_test(atomic_t *v)
{
char c;
__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
return c != 0;
}
#ifdef CONFIG_RMW_INSNS
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
#else /* !CONFIG_RMW_INSNS */
static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
unsigned long flags;
int prev;
local_irq_save(flags);
prev = atomic_read(v);
if (prev == old)
atomic_set(v, new);
local_irq_restore(flags);
return prev;
}
static inline int atomic_xchg(atomic_t *v, int new)
{
unsigned long flags;
int prev;
local_irq_save(flags);
prev = atomic_read(v);
atomic_set(v, new);
local_irq_restore(flags);
return prev;
}
#endif /* !CONFIG_RMW_INSNS */
#define atomic_dec_return(v) atomic_sub_return(1, (v))
#define atomic_inc_return(v) atomic_add_return(1, (v))
static inline int atomic_sub_and_test(int i, atomic_t *v)
{
char c;
__asm__ __volatile__("subl %2,%1; seq %0"
: "=d" (c), "+m" (*v)
: ASM_DI (i));
return c != 0;
}
static inline int atomic_add_negative(int i, atomic_t *v)
{
char c;
__asm__ __volatile__("addl %2,%1; smi %0"
: "=d" (c), "+m" (*v)
: ASM_DI (i));
return c != 0;
}
static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask)));
}
static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
{
__asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask));
}
static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
{
int c, old;
c = atomic_read(v);
for (;;) {
if (unlikely(c == (u)))
break;
old = atomic_cmpxchg((v), c, c + (a));
if (likely(old == c))
break;
c = old;
}
return c;
}
#endif /* __ARCH_M68K_ATOMIC __ */

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#ifndef _M68K_BITOPS_H
#define _M68K_BITOPS_H
/*
* Copyright 1992, Linus Torvalds.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <linux/compiler.h>
#include <asm/barrier.h>
/*
* Bit access functions vary across the ColdFire and 68k families.
* So we will break them out here, and then macro in the ones we want.
*
* ColdFire - supports standard bset/bclr/bchg with register operand only
* 68000 - supports standard bset/bclr/bchg with memory operand
* >= 68020 - also supports the bfset/bfclr/bfchg instructions
*
* Although it is possible to use only the bset/bclr/bchg with register
* operands on all platforms you end up with larger generated code.
* So we use the best form possible on a given platform.
*/
static inline void bset_reg_set_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bset %1,(%0)"
:
: "a" (p), "di" (nr & 7)
: "memory");
}
static inline void bset_mem_set_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bset %1,%0"
: "+m" (*p)
: "di" (nr & 7));
}
static inline void bfset_mem_set_bit(int nr, volatile unsigned long *vaddr)
{
__asm__ __volatile__ ("bfset %1{%0:#1}"
:
: "d" (nr ^ 31), "o" (*vaddr)
: "memory");
}
#if defined(CONFIG_COLDFIRE)
#define set_bit(nr, vaddr) bset_reg_set_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define set_bit(nr, vaddr) bset_mem_set_bit(nr, vaddr)
#else
#define set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
bset_mem_set_bit(nr, vaddr) : \
bfset_mem_set_bit(nr, vaddr))
#endif
#define __set_bit(nr, vaddr) set_bit(nr, vaddr)
static inline void bclr_reg_clear_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bclr %1,(%0)"
:
: "a" (p), "di" (nr & 7)
: "memory");
}
static inline void bclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bclr %1,%0"
: "+m" (*p)
: "di" (nr & 7));
}
static inline void bfclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
{
__asm__ __volatile__ ("bfclr %1{%0:#1}"
:
: "d" (nr ^ 31), "o" (*vaddr)
: "memory");
}
#if defined(CONFIG_COLDFIRE)
#define clear_bit(nr, vaddr) bclr_reg_clear_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define clear_bit(nr, vaddr) bclr_mem_clear_bit(nr, vaddr)
#else
#define clear_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
bclr_mem_clear_bit(nr, vaddr) : \
bfclr_mem_clear_bit(nr, vaddr))
#endif
#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr)
static inline void bchg_reg_change_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bchg %1,(%0)"
:
: "a" (p), "di" (nr & 7)
: "memory");
}
static inline void bchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
__asm__ __volatile__ ("bchg %1,%0"
: "+m" (*p)
: "di" (nr & 7));
}
static inline void bfchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
{
__asm__ __volatile__ ("bfchg %1{%0:#1}"
:
: "d" (nr ^ 31), "o" (*vaddr)
: "memory");
}
#if defined(CONFIG_COLDFIRE)
#define change_bit(nr, vaddr) bchg_reg_change_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define change_bit(nr, vaddr) bchg_mem_change_bit(nr, vaddr)
#else
#define change_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
bchg_mem_change_bit(nr, vaddr) : \
bfchg_mem_change_bit(nr, vaddr))
#endif
#define __change_bit(nr, vaddr) change_bit(nr, vaddr)
static inline int test_bit(int nr, const unsigned long *vaddr)
{
return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
}
static inline int bset_reg_test_and_set_bit(int nr,
volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bset %2,(%1); sne %0"
: "=d" (retval)
: "a" (p), "di" (nr & 7)
: "memory");
return retval;
}
static inline int bset_mem_test_and_set_bit(int nr,
volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bset %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int bfset_mem_test_and_set_bit(int nr,
volatile unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
: "=d" (retval)
: "d" (nr ^ 31), "o" (*vaddr)
: "memory");
return retval;
}
#if defined(CONFIG_COLDFIRE)
#define test_and_set_bit(nr, vaddr) bset_reg_test_and_set_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define test_and_set_bit(nr, vaddr) bset_mem_test_and_set_bit(nr, vaddr)
#else
#define test_and_set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
bset_mem_test_and_set_bit(nr, vaddr) : \
bfset_mem_test_and_set_bit(nr, vaddr))
#endif
#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr)
static inline int bclr_reg_test_and_clear_bit(int nr,
volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bclr %2,(%1); sne %0"
: "=d" (retval)
: "a" (p), "di" (nr & 7)
: "memory");
return retval;
}
static inline int bclr_mem_test_and_clear_bit(int nr,
volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bclr %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int bfclr_mem_test_and_clear_bit(int nr,
volatile unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
: "=d" (retval)
: "d" (nr ^ 31), "o" (*vaddr)
: "memory");
return retval;
}
#if defined(CONFIG_COLDFIRE)
#define test_and_clear_bit(nr, vaddr) bclr_reg_test_and_clear_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define test_and_clear_bit(nr, vaddr) bclr_mem_test_and_clear_bit(nr, vaddr)
#else
#define test_and_clear_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
bclr_mem_test_and_clear_bit(nr, vaddr) : \
bfclr_mem_test_and_clear_bit(nr, vaddr))
#endif
#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr)
static inline int bchg_reg_test_and_change_bit(int nr,
volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bchg %2,(%1); sne %0"
: "=d" (retval)
: "a" (p), "di" (nr & 7)
: "memory");
return retval;
}
static inline int bchg_mem_test_and_change_bit(int nr,
volatile unsigned long *vaddr)
{
char *p = (char *)vaddr + (nr ^ 31) / 8;
char retval;
__asm__ __volatile__ ("bchg %2,%1; sne %0"
: "=d" (retval), "+m" (*p)
: "di" (nr & 7));
return retval;
}
static inline int bfchg_mem_test_and_change_bit(int nr,
volatile unsigned long *vaddr)
{
char retval;
__asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
: "=d" (retval)
: "d" (nr ^ 31), "o" (*vaddr)
: "memory");
return retval;
}
#if defined(CONFIG_COLDFIRE)
#define test_and_change_bit(nr, vaddr) bchg_reg_test_and_change_bit(nr, vaddr)
#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#define test_and_change_bit(nr, vaddr) bchg_mem_test_and_change_bit(nr, vaddr)
#else
#define test_and_change_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
bchg_mem_test_and_change_bit(nr, vaddr) : \
bfchg_mem_test_and_change_bit(nr, vaddr))
#endif
#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)
/*
* The true 68020 and more advanced processors support the "bfffo"
* instruction for finding bits. ColdFire and simple 68000 parts
* (including CPU32) do not support this. They simply use the generic
* functions.
*/
#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/ffz.h>
#else
static inline int find_first_zero_bit(const unsigned long *vaddr,
unsigned size)
{
const unsigned long *p = vaddr;
int res = 32;
unsigned int words;
unsigned long num;
if (!size)
return 0;
words = (size + 31) >> 5;
while (!(num = ~*p++)) {
if (!--words)
goto out;
}
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
res ^= 31;
out:
res += ((long)p - (long)vaddr - 4) * 8;
return res < size ? res : size;
}
#define find_first_zero_bit find_first_zero_bit
static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
int offset)
{
const unsigned long *p = vaddr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
unsigned long num = ~*p++ & (~0UL << bit);
offset -= bit;
/* Look for zero in first longword */
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
if (res < 32) {
offset += res ^ 31;
return offset < size ? offset : size;
}
offset += 32;
if (offset >= size)
return size;
}
/* No zero yet, search remaining full bytes for a zero */
return offset + find_first_zero_bit(p, size - offset);
}
#define find_next_zero_bit find_next_zero_bit
static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
{
const unsigned long *p = vaddr;
int res = 32;
unsigned int words;
unsigned long num;
if (!size)
return 0;
words = (size + 31) >> 5;
while (!(num = *p++)) {
if (!--words)
goto out;
}
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
res ^= 31;
out:
res += ((long)p - (long)vaddr - 4) * 8;
return res < size ? res : size;
}
#define find_first_bit find_first_bit
static inline int find_next_bit(const unsigned long *vaddr, int size,
int offset)
{
const unsigned long *p = vaddr + (offset >> 5);
int bit = offset & 31UL, res;
if (offset >= size)
return size;
if (bit) {
unsigned long num = *p++ & (~0UL << bit);
offset -= bit;
/* Look for one in first longword */
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (num & -num));
if (res < 32) {
offset += res ^ 31;
return offset < size ? offset : size;
}
offset += 32;
if (offset >= size)
return size;
}
/* No one yet, search remaining full bytes for a one */
return offset + find_first_bit(p, size - offset);
}
#define find_next_bit find_next_bit
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
*/
static inline unsigned long ffz(unsigned long word)
{
int res;
__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
: "=d" (res) : "d" (~word & -~word));
return res ^ 31;
}
#endif
#ifdef __KERNEL__
#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
/*
* The newer ColdFire family members support a "bitrev" instruction
* and we can use that to implement a fast ffs. Older Coldfire parts,
* and normal 68000 parts don't have anything special, so we use the
* generic functions for those.
*/
#if (defined(__mcfisaaplus__) || defined(__mcfisac__)) && \
!defined(CONFIG_M68000) && !defined(CONFIG_MCPU32)
static inline int __ffs(int x)
{
__asm__ __volatile__ ("bitrev %0; ff1 %0"
: "=d" (x)
: "0" (x));
return x;
}
static inline int ffs(int x)
{
if (!x)
return 0;
return __ffs(x) + 1;
}
#else
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/__ffs.h>
#endif
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#else
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static inline int ffs(int x)
{
int cnt;
__asm__ ("bfffo %1{#0:#0},%0"
: "=d" (cnt)
: "dm" (x & -x));
return 32 - cnt;
}
#define __ffs(x) (ffs(x) - 1)
/*
* fls: find last bit set.
*/
static inline int fls(int x)
{
int cnt;
__asm__ ("bfffo %1{#0,#0},%0"
: "=d" (cnt)
: "dm" (x));
return 32 - cnt;
}
static inline int __fls(int x)
{
return fls(x) - 1;
}
#endif
#include <asm-generic/bitops/ext2-atomic.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#endif /* __KERNEL__ */
#endif /* _M68K_BITOPS_H */

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/*
** asm/blinken.h -- m68k blinkenlights support (currently hp300 only)
**
** (c) 1998 Phil Blundell <philb@gnu.org>
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _M68K_BLINKEN_H
#define _M68K_BLINKEN_H
#include <asm/setup.h>
#include <asm/io.h>
#define HP300_LEDS 0xf001ffff
extern unsigned char hp300_ledstate;
static __inline__ void blinken_leds(int on, int off)
{
if (MACH_IS_HP300)
{
hp300_ledstate |= on;
hp300_ledstate &= ~off;
out_8(HP300_LEDS, ~hp300_ledstate);
}
}
#endif

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arch/m68k/include/asm/bootinfo.h Normal file
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/*
** asm/bootinfo.h -- Definition of the Linux/m68k boot information structure
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
*/
#ifndef _M68K_BOOTINFO_H
#define _M68K_BOOTINFO_H
#include <uapi/asm/bootinfo.h>
#ifndef __ASSEMBLY__
#ifdef CONFIG_BOOTINFO_PROC
extern void save_bootinfo(const struct bi_record *bi);
#else
static inline void save_bootinfo(const struct bi_record *bi) {}
#endif
#endif /* __ASSEMBLY__ */
#endif /* _M68K_BOOTINFO_H */

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/* bootstd.h: Bootloader system call interface
*
* (c) 1999, Rt-Control, Inc.
*/
#ifndef __BOOTSTD_H__
#define __BOOTSTD_H__
#define NR_BSC 21 /* last used bootloader system call */
#define __BN_reset 0 /* reset and start the bootloader */
#define __BN_test 1 /* tests the system call interface */
#define __BN_exec 2 /* executes a bootloader image */
#define __BN_exit 3 /* terminates a bootloader image */
#define __BN_program 4 /* program FLASH from a chain */
#define __BN_erase 5 /* erase sector(s) of FLASH */
#define __BN_open 6
#define __BN_write 7
#define __BN_read 8
#define __BN_close 9
#define __BN_mmap 10 /* map a file descriptor into memory */
#define __BN_munmap 11 /* remove a file to memory mapping */
#define __BN_gethwaddr 12 /* get the hardware address of my interfaces */
#define __BN_getserialnum 13 /* get the serial number of this board */
#define __BN_getbenv 14 /* get a bootloader envvar */
#define __BN_setbenv 15 /* get a bootloader envvar */
#define __BN_setpmask 16 /* set the protection mask */
#define __BN_readenv 17 /* read environment variables */
#define __BN_flash_chattr_range 18
#define __BN_flash_erase_range 19
#define __BN_flash_write_range 20
/* Calling conventions compatible to (uC)linux/68k
* We use similar macros to call into the bootloader as for uClinux
*/
#define __bsc_return(type, res) \
do { \
if ((unsigned long)(res) >= (unsigned long)(-64)) { \
/* let errno be a function, preserve res in %d0 */ \
int __err = -(res); \
errno = __err; \
res = -1; \
} \
return (type)(res); \
} while (0)
#define _bsc0(type,name) \
type name(void) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res) \
); \
__bsc_return(type,__res); \
}
#define _bsc1(type,name,atype,a) \
type name(atype a) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a) \
); \
__bsc_return(type,__res); \
}
#define _bsc2(type,name,atype,a,btype,b) \
type name(atype a, btype b) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b) \
); \
__bsc_return(type,__res); \
}
#define _bsc3(type,name,atype,a,btype,b,ctype,c) \
type name(atype a, btype b, ctype c) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
register long __c __asm__ ("%d3") = (long)c; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c) \
); \
__bsc_return(type,__res); \
}
#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
type name(atype a, btype b, ctype c, dtype d) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
register long __c __asm__ ("%d3") = (long)c; \
register long __d __asm__ ("%d4") = (long)d; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c), "d" (__d) \
); \
__bsc_return(type,__res); \
}
#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
type name(atype a, btype b, ctype c, dtype d, etype e) \
{ \
register long __res __asm__ ("%d0") = __BN_##name; \
register long __a __asm__ ("%d1") = (long)a; \
register long __b __asm__ ("%d2") = (long)b; \
register long __c __asm__ ("%d3") = (long)c; \
register long __d __asm__ ("%d4") = (long)d; \
register long __e __asm__ ("%d5") = (long)e; \
__asm__ __volatile__ ("trap #2" \
: "=g" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c), "d" (__d), "d" (__e) \
); \
__bsc_return(type,__res); \
}
#endif /* __BOOTSTD_H__ */

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arch/m68k/include/asm/bug.h Normal file
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#ifndef _M68K_BUG_H
#define _M68K_BUG_H
#ifdef CONFIG_MMU
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
#ifndef CONFIG_SUN3
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
__builtin_trap(); \
} while (0)
#else
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
panic("BUG!"); \
} while (0)
#endif
#else
#define BUG() do { \
__builtin_trap(); \
} while (0)
#endif
#define HAVE_ARCH_BUG
#endif
#endif /* CONFIG_MMU */
#include <asm-generic/bug.h>
#endif

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arch/m68k/include/asm/bugs.h Normal file
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/*
* include/asm-m68k/bugs.h
*
* Copyright (C) 1994 Linus Torvalds
*/
/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
#ifdef CONFIG_MMU
extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */
#else
static void check_bugs(void)
{
}
#endif

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arch/m68k/include/asm/bvme6000hw.h Normal file
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#ifndef _M68K_BVME6000HW_H_
#define _M68K_BVME6000HW_H_
#include <asm/irq.h>
/*
* PIT structure
*/
#define BVME_PIT_BASE 0xffa00000
typedef struct {
unsigned char
pad_a[3], pgcr,
pad_b[3], psrr,
pad_c[3], paddr,
pad_d[3], pbddr,
pad_e[3], pcddr,
pad_f[3], pivr,
pad_g[3], pacr,
pad_h[3], pbcr,
pad_i[3], padr,
pad_j[3], pbdr,
pad_k[3], paar,
pad_l[3], pbar,
pad_m[3], pcdr,
pad_n[3], psr,
pad_o[3], res1,
pad_p[3], res2,
pad_q[3], tcr,
pad_r[3], tivr,
pad_s[3], res3,
pad_t[3], cprh,
pad_u[3], cprm,
pad_v[3], cprl,
pad_w[3], res4,
pad_x[3], crh,
pad_y[3], crm,
pad_z[3], crl,
pad_A[3], tsr,
pad_B[3], res5;
} PitRegs_t, *PitRegsPtr;
#define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE)))
#define BVME_RTC_BASE 0xff900000
typedef struct {
unsigned char
pad_a[3], msr,
pad_b[3], t0cr_rtmr,
pad_c[3], t1cr_omr,
pad_d[3], pfr_icr0,
pad_e[3], irr_icr1,
pad_f[3], bcd_tenms,
pad_g[3], bcd_sec,
pad_h[3], bcd_min,
pad_i[3], bcd_hr,
pad_j[3], bcd_dom,
pad_k[3], bcd_mth,
pad_l[3], bcd_year,
pad_m[3], bcd_ujcc,
pad_n[3], bcd_hjcc,
pad_o[3], bcd_dow,
pad_p[3], t0lsb,
pad_q[3], t0msb,
pad_r[3], t1lsb,
pad_s[3], t1msb,
pad_t[3], cmp_sec,
pad_u[3], cmp_min,
pad_v[3], cmp_hr,
pad_w[3], cmp_dom,
pad_x[3], cmp_mth,
pad_y[3], cmp_dow,
pad_z[3], sav_sec,
pad_A[3], sav_min,
pad_B[3], sav_hr,
pad_C[3], sav_dom,
pad_D[3], sav_mth,
pad_E[3], ram,
pad_F[3], test;
} RtcRegs_t, *RtcPtr_t;
#define BVME_I596_BASE 0xff100000
#define BVME_ETHIRQ_REG 0xff20000b
#define BVME_LOCAL_IRQ_STAT 0xff20000f
#define BVME_ETHERR 0x02
#define BVME_ABORT_STATUS 0x08
#define BVME_NCR53C710_BASE 0xff000000
#define BVME_SCC_A_ADDR 0xffb0000b
#define BVME_SCC_B_ADDR 0xffb00003
#define BVME_SCC_RTxC 7372800
#define BVME_CONFIG_REG 0xff500003
#define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG
#define BVME_CONFIG_SW1 0x08
#define BVME_CONFIG_SW2 0x04
#define BVME_CONFIG_SW3 0x02
#define BVME_CONFIG_SW4 0x01
#define BVME_IRQ_TYPE_PRIO 0
#define BVME_IRQ_PRN (IRQ_USER+20)
#define BVME_IRQ_TIMER (IRQ_USER+25)
#define BVME_IRQ_I596 IRQ_AUTO_2
#define BVME_IRQ_SCSI IRQ_AUTO_3
#define BVME_IRQ_RTC IRQ_AUTO_6
#define BVME_IRQ_ABORT IRQ_AUTO_7
/* SCC interrupts */
#define BVME_IRQ_SCC_BASE IRQ_USER
#define BVME_IRQ_SCCB_TX IRQ_USER
#define BVME_IRQ_SCCB_STAT (IRQ_USER+2)
#define BVME_IRQ_SCCB_RX (IRQ_USER+4)
#define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6)
#define BVME_IRQ_SCCA_TX (IRQ_USER+8)
#define BVME_IRQ_SCCA_STAT (IRQ_USER+10)
#define BVME_IRQ_SCCA_RX (IRQ_USER+12)
#define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14)
/* Address control registers */
#define BVME_ACR_A32VBA 0xff400003
#define BVME_ACR_A32MSK 0xff410003
#define BVME_ACR_A24VBA 0xff420003
#define BVME_ACR_A24MSK 0xff430003
#define BVME_ACR_A16VBA 0xff440003
#define BVME_ACR_A32LBA 0xff450003
#define BVME_ACR_A24LBA 0xff460003
#define BVME_ACR_ADDRCTL 0xff470003
#define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA
#define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK
#define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA
#define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK
#define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA
#define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA
#define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA
#define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL
#endif

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/*
* include/asm-m68k/cache.h
*/
#ifndef __ARCH_M68K_CACHE_H
#define __ARCH_M68K_CACHE_H
/* bytes per L1 cache line */
#define L1_CACHE_SHIFT 4
#define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT)
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#endif

5
arch/m68k/include/asm/cacheflush.h Normal file
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#ifdef __uClinux__
#include <asm/cacheflush_no.h>
#else
#include <asm/cacheflush_mm.h>
#endif

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arch/m68k/include/asm/cacheflush_mm.h Normal file
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#ifndef _M68K_CACHEFLUSH_H
#define _M68K_CACHEFLUSH_H
#include <linux/mm.h>
#ifdef CONFIG_COLDFIRE
#include <asm/mcfsim.h>
#endif
/* cache code */
#define FLUSH_I_AND_D (0x00000808)
#define FLUSH_I (0x00000008)
#ifndef ICACHE_MAX_ADDR
#define ICACHE_MAX_ADDR 0
#define ICACHE_SET_MASK 0
#define DCACHE_MAX_ADDR 0
#define DCACHE_SETMASK 0
#endif
#ifndef CACHE_MODE
#define CACHE_MODE 0
#define CACR_ICINVA 0
#define CACR_DCINVA 0
#define CACR_BCINVA 0
#endif
/*
* ColdFire architecture has no way to clear individual cache lines, so we
* are stuck invalidating all the cache entries when we want a clear operation.
*/
static inline void clear_cf_icache(unsigned long start, unsigned long end)
{
__asm__ __volatile__ (
"movec %0,%%cacr\n\t"
"nop"
:
: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));
}
static inline void clear_cf_dcache(unsigned long start, unsigned long end)
{
__asm__ __volatile__ (
"movec %0,%%cacr\n\t"
"nop"
:
: "r" (CACHE_MODE | CACR_DCINVA));
}
static inline void clear_cf_bcache(unsigned long start, unsigned long end)
{
__asm__ __volatile__ (
"movec %0,%%cacr\n\t"
"nop"
:
: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));
}
/*
* Use the ColdFire cpushl instruction to push (and invalidate) cache lines.
* The start and end addresses are cache line numbers not memory addresses.
*/
static inline void flush_cf_icache(unsigned long start, unsigned long end)
{
unsigned long set;
for (set = start; set <= end; set += (0x10 - 3)) {
__asm__ __volatile__ (
"cpushl %%ic,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%ic,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%ic,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%ic,(%0)"
: "=a" (set)
: "a" (set));
}
}
static inline void flush_cf_dcache(unsigned long start, unsigned long end)
{
unsigned long set;
for (set = start; set <= end; set += (0x10 - 3)) {
__asm__ __volatile__ (
"cpushl %%dc,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%dc,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%dc,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%dc,(%0)"
: "=a" (set)
: "a" (set));
}
}
static inline void flush_cf_bcache(unsigned long start, unsigned long end)
{
unsigned long set;
for (set = start; set <= end; set += (0x10 - 3)) {
__asm__ __volatile__ (
"cpushl %%bc,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%bc,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%bc,(%0)\n\t"
"addq%.l #1,%0\n\t"
"cpushl %%bc,(%0)"
: "=a" (set)
: "a" (set));
}
}
/*
* Cache handling functions
*/
static inline void flush_icache(void)
{
if (CPU_IS_COLDFIRE) {
flush_cf_icache(0, ICACHE_MAX_ADDR);
} else if (CPU_IS_040_OR_060) {
asm volatile ( "nop\n"
" .chip 68040\n"
" cpusha %bc\n"
" .chip 68k");
} else {
unsigned long tmp;
asm volatile ( "movec %%cacr,%0\n"
" or.w %1,%0\n"
" movec %0,%%cacr"
: "=&d" (tmp)
: "id" (FLUSH_I));
}
}
/*
* invalidate the cache for the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_clear(unsigned long paddr, int len);
/*
* push any dirty cache in the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_push(unsigned long paddr, int len);
/*
* push and invalidate pages in the specified user virtual
* memory range.
*/
extern void cache_push_v(unsigned long vaddr, int len);
/* This is needed whenever the virtual mapping of the current
process changes. */
#define __flush_cache_all() \
({ \
if (CPU_IS_COLDFIRE) { \
flush_cf_dcache(0, DCACHE_MAX_ADDR); \
} else if (CPU_IS_040_OR_060) { \
__asm__ __volatile__("nop\n\t" \
".chip 68040\n\t" \
"cpusha %dc\n\t" \
".chip 68k"); \
} else { \
unsigned long _tmp; \
__asm__ __volatile__("movec %%cacr,%0\n\t" \
"orw %1,%0\n\t" \
"movec %0,%%cacr" \
: "=&d" (_tmp) \
: "di" (FLUSH_I_AND_D)); \
} \
})
#define __flush_cache_030() \
({ \
if (CPU_IS_020_OR_030) { \
unsigned long _tmp; \
__asm__ __volatile__("movec %%cacr,%0\n\t" \
"orw %1,%0\n\t" \
"movec %0,%%cacr" \
: "=&d" (_tmp) \
: "di" (FLUSH_I_AND_D)); \
} \
})
#define flush_cache_all() __flush_cache_all()
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
static inline void flush_cache_mm(struct mm_struct *mm)
{
if (mm == current->mm)
__flush_cache_030();
}
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
/* flush_cache_range/flush_cache_page must be macros to avoid
a dependency on linux/mm.h, which includes this file... */
static inline void flush_cache_range(struct vm_area_struct *vma,
unsigned long start,
unsigned long end)
{
if (vma->vm_mm == current->mm)
__flush_cache_030();
}
static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
{
if (vma->vm_mm == current->mm)
__flush_cache_030();
}
/* Push the page at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
static inline void __flush_page_to_ram(void *vaddr)
{
if (CPU_IS_COLDFIRE) {
unsigned long addr, start, end;
addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1);
start = addr & ICACHE_SET_MASK;
end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK;
if (start > end) {
flush_cf_bcache(0, end);
end = ICACHE_MAX_ADDR;
}
flush_cf_bcache(start, end);
} else if (CPU_IS_040_OR_060) {
__asm__ __volatile__("nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (__pa(vaddr)));
} else {
unsigned long _tmp;
__asm__ __volatile__("movec %%cacr,%0\n\t"
"orw %1,%0\n\t"
"movec %0,%%cacr"
: "=&d" (_tmp)
: "di" (FLUSH_I));
}
}
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len);
extern void flush_icache_range(unsigned long address, unsigned long endaddr);
static inline void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
flush_cache_page(vma, vaddr, page_to_pfn(page));
memcpy(dst, src, len);
flush_icache_user_range(vma, page, vaddr, len);
}
static inline void copy_from_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr,
void *dst, void *src, int len)
{
flush_cache_page(vma, vaddr, page_to_pfn(page));
memcpy(dst, src, len);
}
#endif /* _M68K_CACHEFLUSH_H */

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#ifndef _M68KNOMMU_CACHEFLUSH_H
#define _M68KNOMMU_CACHEFLUSH_H
/*
* (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com>
*/
#include <linux/mm.h>
#include <asm/mcfsim.h>
#define flush_cache_all() __flush_cache_all()
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr) do { } while (0)
#define flush_dcache_range(start, len) __flush_dcache_all()
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start, len) __flush_icache_all()
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define flush_cache_vmap(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
void mcf_cache_push(void);
static inline void __clear_cache_all(void)
{
#ifdef CACHE_INVALIDATE
__asm__ __volatile__ (
"movec %0, %%CACR\n\t"
"nop\n\t"
: : "r" (CACHE_INVALIDATE) );
#endif
}
static inline void __flush_cache_all(void)
{
#ifdef CACHE_PUSH
mcf_cache_push();
#endif
__clear_cache_all();
}
/*
* Some ColdFire parts implement separate instruction and data caches,
* on those we should just flush the appropriate cache. If we don't need
* to do any specific flushing then this will be optimized away.
*/
static inline void __flush_icache_all(void)
{
#ifdef CACHE_INVALIDATEI
__asm__ __volatile__ (
"movec %0, %%CACR\n\t"
"nop\n\t"
: : "r" (CACHE_INVALIDATEI) );
#endif
}
static inline void __flush_dcache_all(void)
{
#ifdef CACHE_PUSH
mcf_cache_push();
#endif
#ifdef CACHE_INVALIDATED
__asm__ __volatile__ (
"movec %0, %%CACR\n\t"
"nop\n\t"
: : "r" (CACHE_INVALIDATED) );
#else
/* Flush the write buffer */
__asm__ __volatile__ ( "nop" );
#endif
}
/*
* Push cache entries at supplied address. We want to write back any dirty
* data and then invalidate the cache lines associated with this address.
*/
static inline void cache_push(unsigned long paddr, int len)
{
__flush_cache_all();
}
/*
* Clear cache entries at supplied address (that is don't write back any
* dirty data).
*/
static inline void cache_clear(unsigned long paddr, int len)
{
__clear_cache_all();
}
#endif /* _M68KNOMMU_CACHEFLUSH_H */

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#ifndef _M68K_CHECKSUM_H
#define _M68K_CHECKSUM_H
#include <linux/in6.h>
#ifdef CONFIG_GENERIC_CSUM
#include <asm-generic/checksum.h>
#else
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
__wsum csum_partial(const void *buff, int len, __wsum sum);
/*
* the same as csum_partial, but copies from src while it
* checksums
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
extern __wsum csum_partial_copy_from_user(const void __user *src,
void *dst,
int len, __wsum sum,
int *csum_err);
extern __wsum csum_partial_copy_nocheck(const void *src,
void *dst, int len,
__wsum sum);
/*
* This is a version of ip_fast_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*/
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
{
unsigned int sum = 0;
unsigned long tmp;
__asm__ ("subqw #1,%2\n"
"1:\t"
"movel %1@+,%3\n\t"
"addxl %3,%0\n\t"
"dbra %2,1b\n\t"
"movel %0,%3\n\t"
"swap %3\n\t"
"addxw %3,%0\n\t"
"clrw %3\n\t"
"addxw %3,%0\n\t"
: "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp)
: "0" (sum), "1" (iph), "2" (ihl)
: "memory");
return (__force __sum16)~sum;
}
static inline __sum16 csum_fold(__wsum sum)
{
unsigned int tmp = (__force u32)sum;
__asm__("swap %1\n\t"
"addw %1, %0\n\t"
"clrw %1\n\t"
"addxw %1, %0"
: "=&d" (sum), "=&d" (tmp)
: "0" (sum), "1" (tmp));
return (__force __sum16)~sum;
}
static inline __wsum
csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
__asm__ ("addl %2,%0\n\t"
"addxl %3,%0\n\t"
"addxl %4,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=d" (saddr)
: "g" (daddr), "1" (saddr), "d" (len + proto),
"0" (sum));
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline __sum16
csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
unsigned short proto, __wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold (csum_partial(buff, len, 0));
}
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ __sum16
csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
__u32 len, unsigned short proto, __wsum sum)
{
register unsigned long tmp;
__asm__("addl %2@,%0\n\t"
"movel %2@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %2@(12),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@,%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(4),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(8),%1\n\t"
"addxl %1,%0\n\t"
"movel %3@(12),%1\n\t"
"addxl %1,%0\n\t"
"addxl %4,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=&d" (tmp)
: "a" (saddr), "a" (daddr), "d" (len + proto),
"0" (sum));
return csum_fold(sum);
}
#endif /* CONFIG_GENERIC_CSUM */
#endif /* _M68K_CHECKSUM_H */

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#ifndef __ARCH_M68K_CMPXCHG__
#define __ARCH_M68K_CMPXCHG__
#include <linux/irqflags.h>
struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((volatile struct __xchg_dummy *)(x))
extern unsigned long __invalid_xchg_size(unsigned long, volatile void *, int);
#ifndef CONFIG_RMW_INSNS
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
unsigned long flags, tmp;
local_irq_save(flags);
switch (size) {
case 1:
tmp = *(u8 *)ptr;
*(u8 *)ptr = x;
x = tmp;
break;
case 2:
tmp = *(u16 *)ptr;
*(u16 *)ptr = x;
x = tmp;
break;
case 4:
tmp = *(u32 *)ptr;
*(u32 *)ptr = x;
x = tmp;
break;
default:
tmp = __invalid_xchg_size(x, ptr, size);
break;
}
local_irq_restore(flags);
return x;
}
#else
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
switch (size) {
case 1:
__asm__ __volatile__
("moveb %2,%0\n\t"
"1:\n\t"
"casb %0,%1,%2\n\t"
"jne 1b"
: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
case 2:
__asm__ __volatile__
("movew %2,%0\n\t"
"1:\n\t"
"casw %0,%1,%2\n\t"
"jne 1b"
: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
case 4:
__asm__ __volatile__
("movel %2,%0\n\t"
"1:\n\t"
"casl %0,%1,%2\n\t"
"jne 1b"
: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
default:
x = __invalid_xchg_size(x, ptr, size);
break;
}
return x;
}
#endif
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
#include <asm-generic/cmpxchg-local.h>
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
extern unsigned long __invalid_cmpxchg_size(volatile void *,
unsigned long, unsigned long, int);
/*
* Atomic compare and exchange. Compare OLD with MEM, if identical,
* store NEW in MEM. Return the initial value in MEM. Success is
* indicated by comparing RETURN with OLD.
*/
#ifdef CONFIG_RMW_INSNS
#define __HAVE_ARCH_CMPXCHG 1
static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
unsigned long new, int size)
{
switch (size) {
case 1:
__asm__ __volatile__ ("casb %0,%2,%1"
: "=d" (old), "=m" (*(char *)p)
: "d" (new), "0" (old), "m" (*(char *)p));
break;
case 2:
__asm__ __volatile__ ("casw %0,%2,%1"
: "=d" (old), "=m" (*(short *)p)
: "d" (new), "0" (old), "m" (*(short *)p));
break;
case 4:
__asm__ __volatile__ ("casl %0,%2,%1"
: "=d" (old), "=m" (*(int *)p)
: "d" (new), "0" (old), "m" (*(int *)p));
break;
default:
old = __invalid_cmpxchg_size(p, old, new, size);
break;
}
return old;
}
#define cmpxchg(ptr, o, n) \
((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
(unsigned long)(n), sizeof(*(ptr))))
#define cmpxchg_local(ptr, o, n) \
((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
(unsigned long)(n), sizeof(*(ptr))))
#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
#else
/*
* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
* them available.
*/
#define cmpxchg_local(ptr, o, n) \
((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
(unsigned long)(n), sizeof(*(ptr))))
#include <asm-generic/cmpxchg.h>
#endif
#endif /* __ARCH_M68K_CMPXCHG__ */

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/****************************************************************************/
/*
* coldfire.h -- Motorola ColdFire CPU sepecific defines
*
* (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo (www.lineo.com)
*/
/****************************************************************************/
#ifndef coldfire_h
#define coldfire_h
/****************************************************************************/
/*
* Define master clock frequency. This is done at config time now.
* No point enumerating dozens of possible clock options here. And
* in any case new boards come along from time to time that have yet
* another different clocking frequency.
*/
#ifdef CONFIG_CLOCK_SET
#define MCF_CLK CONFIG_CLOCK_FREQ
#else
#error "Don't know what your ColdFire CPU clock frequency is??"
#endif
/*
* Define the processor internal peripherals base address.
*
* The majority of ColdFire parts use an MBAR register to set
* the base address. Some have an IPSBAR register instead, and it
* has slightly different rules on its size and alignment. Some
* parts have fixed addresses and the internal peripherals cannot
* be relocated in the CPU address space.
*
* The value of MBAR or IPSBAR is config time selectable, we no
* longer hard define it here. No MBAR or IPSBAR will be defined if
* this part has a fixed peripheral address map.
*/
#ifdef CONFIG_MBAR
#define MCF_MBAR CONFIG_MBAR
#endif
#ifdef CONFIG_IPSBAR
#define MCF_IPSBAR CONFIG_IPSBAR
#endif
/****************************************************************************/
#endif /* coldfire_h */

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/*
* 68360 Communication Processor Module.
* Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
* Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
*
* This file contains structures and information for the communication
* processor channels. Some CPM control and status is available
* through the 68360 internal memory map. See include/asm/360_immap.h for details.
* This file is not a complete map of all of the 360 QUICC's capabilities
*
* On the MBX board, EPPC-Bug loads CPM microcode into the first 512
* bytes of the DP RAM and relocates the I2C parameter area to the
* IDMA1 space. The remaining DP RAM is available for buffer descriptors
* or other use.
*/
#ifndef __CPM_360__
#define __CPM_360__
/* CPM Command register masks: */
#define CPM_CR_RST ((ushort)0x8000)
#define CPM_CR_OPCODE ((ushort)0x0f00)
#define CPM_CR_CHAN ((ushort)0x00f0)
#define CPM_CR_FLG ((ushort)0x0001)
/* CPM Command set (opcodes): */
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRSTOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
#define CPM_CR_GCI_ABORT ((ushort)0x000a)
#define CPM_CR_RESET_BCS ((ushort)0x000a)
/* CPM Channel numbers. */
#define CPM_CR_CH_SCC1 ((ushort)0x0000)
#define CPM_CR_CH_SCC2 ((ushort)0x0004)
#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
#define CPM_CR_CH_TMR ((ushort)0x0005)
#define CPM_CR_CH_SCC3 ((ushort)0x0008)
#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
#define CPM_CR_CH_IDMA1 ((ushort)0x0009)
#define CPM_CR_CH_SCC4 ((ushort)0x000c)
#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
#define CPM_CR_CH_IDMA2 ((ushort)0x000d)
#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
#if 1 /* mleslie: I dinna think we have any such restrictions on
* DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
/* The dual ported RAM is multi-functional. Some areas can be (and are
* being) used for microcode. There is an area that can only be used
* as data ram for buffer descriptors, which is all we use right now.
* Currently the first 512 and last 256 bytes are used for microcode.
*/
/* mleslie: The uCquicc board is using no extra microcode in DPRAM */
#define CPM_DATAONLY_BASE ((uint)0x0000)
#define CPM_DATAONLY_SIZE ((uint)0x0800)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#endif
/* Export the base address of the communication processor registers
* and dual port ram. */
/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */
extern QUICC *pquicc;
uint m360_cpm_dpalloc(uint size);
/* void *m360_cpm_hostalloc(uint size); */
void m360_cpm_setbrg(uint brg, uint rate);
#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */
/* Buffer descriptors used by many of the CPM protocols. */
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#endif
/* rx bd status/control bits */
#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
/* tx bd status/control bits (as differ from rx bd) */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_UN ((ushort)0x0002) /* Underrun */
/* Parameter RAM offsets. */
/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
* In 2.0, we use a more structured C struct map of DPRAM, and so
* instead, we need only a parameter ram `slot' */
#define PRSLOT_SCC1 0
#define PRSLOT_SCC2 1
#define PRSLOT_SCC3 2
#define PRSLOT_SMC1 2
#define PRSLOT_SCC4 3
#define PRSLOT_SMC2 3
/* #define PROFF_SCC1 ((uint)0x0000) */
/* #define PROFF_SCC2 ((uint)0x0100) */
/* #define PROFF_SCC3 ((uint)0x0200) */
/* #define PROFF_SMC1 ((uint)0x0280) */
/* #define PROFF_SCC4 ((uint)0x0300) */
/* #define PROFF_SMC2 ((uint)0x0380) */
/* Define enough so I can at least use the serial port as a UART.
* The MBX uses SMC1 as the host serial port.
*/
typedef struct smc_uart {
ushort smc_rbase; /* Rx Buffer descriptor base address */
ushort smc_tbase; /* Tx Buffer descriptor base address */
u_char smc_rfcr; /* Rx function code */
u_char smc_tfcr; /* Tx function code */
ushort smc_mrblr; /* Max receive buffer length */
uint smc_rstate; /* Internal */
uint smc_idp; /* Internal */
ushort smc_rbptr; /* Internal */
ushort smc_ibc; /* Internal */
uint smc_rxtmp; /* Internal */
uint smc_tstate; /* Internal */
uint smc_tdp; /* Internal */
ushort smc_tbptr; /* Internal */
ushort smc_tbc; /* Internal */
uint smc_txtmp; /* Internal */
ushort smc_maxidl; /* Maximum idle characters */
ushort smc_tmpidl; /* Temporary idle counter */
ushort smc_brklen; /* Last received break length */
ushort smc_brkec; /* rcv'd break condition counter */
ushort smc_brkcr; /* xmt break count register */
ushort smc_rmask; /* Temporary bit mask */
} smc_uart_t;
/* Function code bits.
*/
#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
/* SMC uart mode register.
*/
#define SMCMR_REN ((ushort)0x0001)
#define SMCMR_TEN ((ushort)0x0002)
#define SMCMR_DM ((ushort)0x000c)
#define SMCMR_SM_GCI ((ushort)0x0000)
#define SMCMR_SM_UART ((ushort)0x0020)
#define SMCMR_SM_TRANS ((ushort)0x0030)
#define SMCMR_SM_MASK ((ushort)0x0030)
#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
#define SMCMR_REVD SMCMR_PM_EVEN
#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
#define SMCMR_BS SMCMR_PEN
#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
/* SMC2 as Centronics parallel printer. It is half duplex, in that
* it can only receive or transmit. The parameter ram values for
* each direction are either unique or properly overlap, so we can
* include them in one structure.
*/
typedef struct smc_centronics {
ushort scent_rbase;
ushort scent_tbase;
u_char scent_cfcr;
u_char scent_smask;
ushort scent_mrblr;
uint scent_rstate;
uint scent_r_ptr;
ushort scent_rbptr;
ushort scent_r_cnt;
uint scent_rtemp;
uint scent_tstate;
uint scent_t_ptr;
ushort scent_tbptr;
ushort scent_t_cnt;
uint scent_ttemp;
ushort scent_max_sl;
ushort scent_sl_cnt;
ushort scent_character1;
ushort scent_character2;
ushort scent_character3;
ushort scent_character4;
ushort scent_character5;
ushort scent_character6;
ushort scent_character7;
ushort scent_character8;
ushort scent_rccm;
ushort scent_rccr;
} smc_cent_t;
/* Centronics Status Mask Register.
*/
#define SMC_CENT_F ((u_char)0x08)
#define SMC_CENT_PE ((u_char)0x04)
#define SMC_CENT_S ((u_char)0x02)
/* SMC Event and Mask register.
*/
#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
#define SMCM_BSY ((unsigned char)0x04)
#define SMCM_TX ((unsigned char)0x02)
#define SMCM_RX ((unsigned char)0x01)
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
/* SCCs.
*/
#define SCC_GSMRH_IRP ((uint)0x00040000)
#define SCC_GSMRH_GDE ((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
#define SCC_GSMRH_REVD ((uint)0x00002000)
#define SCC_GSMRH_TRX ((uint)0x00001000)
#define SCC_GSMRH_TTX ((uint)0x00000800)
#define SCC_GSMRH_CDP ((uint)0x00000400)
#define SCC_GSMRH_CTSP ((uint)0x00000200)
#define SCC_GSMRH_CDS ((uint)0x00000100)
#define SCC_GSMRH_CTSS ((uint)0x00000080)
#define SCC_GSMRH_TFL ((uint)0x00000040)
#define SCC_GSMRH_RFW ((uint)0x00000020)
#define SCC_GSMRH_TXSY ((uint)0x00000010)
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
#define SCC_GSMRH_RTSM ((uint)0x00000002)
#define SCC_GSMRH_RSYN ((uint)0x00000001)
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
#define SCC_GSMRL_TCI ((uint)0x10000000)
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
#define SCC_GSMRL_RINV ((uint)0x02000000)
#define SCC_GSMRL_TINV ((uint)0x01000000)
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
#define SCC_GSMRL_TEND ((uint)0x00040000)
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
#define SCC_GSMRL_ENR ((uint)0x00000020)
#define SCC_GSMRL_ENT ((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
#define SCC_TODR_TOD ((ushort)0x8000)
/* SCC Event and Mask register.
*/
#define SCCM_TXE ((unsigned char)0x10)
#define SCCM_BSY ((unsigned char)0x04)
#define SCCM_TX ((unsigned char)0x02)
#define SCCM_RX ((unsigned char)0x01)
typedef struct scc_param {
ushort scc_rbase; /* Rx Buffer descriptor base address */
ushort scc_tbase; /* Tx Buffer descriptor base address */
u_char scc_rfcr; /* Rx function code */
u_char scc_tfcr; /* Tx function code */
ushort scc_mrblr; /* Max receive buffer length */
uint scc_rstate; /* Internal */
uint scc_idp; /* Internal */
ushort scc_rbptr; /* Internal */
ushort scc_ibc; /* Internal */
uint scc_rxtmp; /* Internal */
uint scc_tstate; /* Internal */
uint scc_tdp; /* Internal */
ushort scc_tbptr; /* Internal */
ushort scc_tbc; /* Internal */
uint scc_txtmp; /* Internal */
uint scc_rcrc; /* Internal */
uint scc_tcrc; /* Internal */
} sccp_t;
/* Function code bits.
*/
#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
/* CPM Ethernet through SCC1.
*/
typedef struct scc_enet {
sccp_t sen_genscc;
uint sen_cpres; /* Preset CRC */
uint sen_cmask; /* Constant mask for CRC */
uint sen_crcec; /* CRC Error counter */
uint sen_alec; /* alignment error counter */
uint sen_disfc; /* discard frame counter */
ushort sen_pads; /* Tx short frame pad character */
ushort sen_retlim; /* Retry limit threshold */
ushort sen_retcnt; /* Retry limit counter */
ushort sen_maxflr; /* maximum frame length register */
ushort sen_minflr; /* minimum frame length register */
ushort sen_maxd1; /* maximum DMA1 length */
ushort sen_maxd2; /* maximum DMA2 length */
ushort sen_maxd; /* Rx max DMA */
ushort sen_dmacnt; /* Rx DMA counter */
ushort sen_maxb; /* Max BD byte count */
ushort sen_gaddr1; /* Group address filter */
ushort sen_gaddr2;
ushort sen_gaddr3;
ushort sen_gaddr4;
uint sen_tbuf0data0; /* Save area 0 - current frame */
uint sen_tbuf0data1; /* Save area 1 - current frame */
uint sen_tbuf0rba; /* Internal */
uint sen_tbuf0crc; /* Internal */
ushort sen_tbuf0bcnt; /* Internal */
ushort sen_paddrh; /* physical address (MSB) */
ushort sen_paddrm;
ushort sen_paddrl; /* physical address (LSB) */
ushort sen_pper; /* persistence */
ushort sen_rfbdptr; /* Rx first BD pointer */
ushort sen_tfbdptr; /* Tx first BD pointer */
ushort sen_tlbdptr; /* Tx last BD pointer */
uint sen_tbuf1data0; /* Save area 0 - current frame */
uint sen_tbuf1data1; /* Save area 1 - current frame */
uint sen_tbuf1rba; /* Internal */
uint sen_tbuf1crc; /* Internal */
ushort sen_tbuf1bcnt; /* Internal */
ushort sen_txlen; /* Tx Frame length counter */
ushort sen_iaddr1; /* Individual address filter */
ushort sen_iaddr2;
ushort sen_iaddr3;
ushort sen_iaddr4;
ushort sen_boffcnt; /* Backoff counter */
/* NOTE: Some versions of the manual have the following items
* incorrectly documented. Below is the proper order.
*/
ushort sen_taddrh; /* temp address (MSB) */
ushort sen_taddrm;
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
#if defined (CONFIG_UCQUICC)
/* uCquicc has the following signals connected to Ethernet:
* 68360 - lxt905
* PA0/RXD1 - rxd
* PA1/TXD1 - txd
* PA8/CLK1 - tclk
* PA9/CLK2 - rclk
* PC0/!RTS1 - t_en
* PC1/!CTS1 - col
* PC5/!CD1 - cd
*/
#define PA_ENET_RXD PA_RXD1
#define PA_ENET_TXD PA_TXD1
#define PA_ENET_TCLK PA_CLK1
#define PA_ENET_RCLK PA_CLK2
#define PC_ENET_TENA PC_RTS1
#define PC_ENET_CLSN PC_CTS1
#define PC_ENET_RENA PC_CD1
/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
* SCC1.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000002c)
#endif /* config_ucquicc */
#ifdef MBX
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
* to the MBX860 board. Any two of the four available clocks could be
* used, and the MPC860 cookbook manual has an example using different
* clock pins.
*/
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PC_ENET_TENA ((ushort)0x0001)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif
#ifdef CONFIG_BSEIP
/* This ENET stuff is for the MPC823 with ethernet on SCC2.
* This is unique to the BSE ip-Engine board.
*/
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
/* BSE uses port B and C bits for PHY control also.
*/
#define PB_BSE_POWERUP ((uint)0x00000004)
#define PB_BSE_FDXDIS ((uint)0x00008000)
#define PC_BSE_LOOPBACK ((ushort)0x0800)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002c00)
#endif
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* SCC Mode Register (PMSR) as used by Ethernet.
*/
#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/* SCC as UART
*/
typedef struct scc_uart {
sccp_t scc_genscc;
uint scc_res1; /* Reserved */
uint scc_res2; /* Reserved */
ushort scc_maxidl; /* Maximum idle chars */
ushort scc_idlc; /* temp idle counter */
ushort scc_brkcr; /* Break count register */
ushort scc_parec; /* receive parity error counter */
ushort scc_frmec; /* receive framing error counter */
ushort scc_nosec; /* receive noise counter */
ushort scc_brkec; /* receive break condition counter */
ushort scc_brkln; /* last received break length */
ushort scc_uaddr1; /* UART address character 1 */
ushort scc_uaddr2; /* UART address character 2 */
ushort scc_rtemp; /* Temp storage */
ushort scc_toseq; /* Transmit out of sequence char */
ushort scc_char1; /* control character 1 */
ushort scc_char2; /* control character 2 */
ushort scc_char3; /* control character 3 */
ushort scc_char4; /* control character 4 */
ushort scc_char5; /* control character 5 */
ushort scc_char6; /* control character 6 */
ushort scc_char7; /* control character 7 */
ushort scc_char8; /* control character 8 */
ushort scc_rccm; /* receive control character mask */
ushort scc_rccr; /* receive control character register */
ushort scc_rlbc; /* receive last break character */
} scc_uart_t;
/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR ((ushort)0x1000)
#define UART_SCCM_GLT ((ushort)0x0800)
#define UART_SCCM_AB ((ushort)0x0200)
#define UART_SCCM_IDL ((ushort)0x0100)
#define UART_SCCM_GRA ((ushort)0x0080)
#define UART_SCCM_BRKE ((ushort)0x0040)
#define UART_SCCM_BRKS ((ushort)0x0020)
#define UART_SCCM_CCR ((ushort)0x0008)
#define UART_SCCM_BSY ((ushort)0x0004)
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PMSR when used as a UART.
*/
#define SCU_PMSR_FLC ((ushort)0x8000)
#define SCU_PMSR_SL ((ushort)0x4000)
#define SCU_PMSR_CL ((ushort)0x3000)
#define SCU_PMSR_UM ((ushort)0x0c00)
#define SCU_PMSR_FRZ ((ushort)0x0200)
#define SCU_PMSR_RZS ((ushort)0x0100)
#define SCU_PMSR_SYN ((ushort)0x0080)
#define SCU_PMSR_DRT ((ushort)0x0040)
#define SCU_PMSR_PEN ((ushort)0x0010)
#define SCU_PMSR_RPM ((ushort)0x000c)
#define SCU_PMSR_REVP ((ushort)0x0008)
#define SCU_PMSR_TPM ((ushort)0x0003)
#define SCU_PMSR_TEVP ((ushort)0x0003)
/* CPM Transparent mode SCC.
*/
typedef struct scc_trans {
sccp_t st_genscc;
uint st_cpres; /* Preset CRC */
uint st_cmask; /* Constant mask for CRC */
} scc_trans_t;
#define BD_SCC_TX_LAST ((ushort)0x0800)
/* CPM interrupts. There are nearly 32 interrupts generated by CPM
* channels or devices. All of these are presented to the PPC core
* as a single interrupt. The CPM interrupt handler dispatches its
* own handlers, in a similar fashion to the PPC core handler. We
* use the table as defined in the manuals (i.e. no special high
* priority and SCC1 == SCCa, etc...).
*/
/* #define CPMVEC_NR 32 */
/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
/* #define CPMVEC_SCC1 ((ushort)0x1e) */
/* #define CPMVEC_SCC2 ((ushort)0x1d) */
/* #define CPMVEC_SCC3 ((ushort)0x1c) */
/* #define CPMVEC_SCC4 ((ushort)0x1b) */
/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
/* #define CPMVEC_TIMER1 ((ushort)0x19) */
/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
/* #define CPMVEC_IDMA1 ((ushort)0x15) */
/* #define CPMVEC_IDMA2 ((ushort)0x14) */
/* #define CPMVEC_TIMER2 ((ushort)0x12) */
/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
/* #define CPMVEC_I2C ((ushort)0x10) */
/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
/* #define CPMVEC_TIMER4 ((ushort)0x07) */
/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
/* #define CPMVEC_SPI ((ushort)0x05) */
/* #define CPMVEC_SMC1 ((ushort)0x04) */
/* #define CPMVEC_SMC2 ((ushort)0x03) */
/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
/* #define CPMVEC_ERROR ((ushort)0x00) */
extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
/* CPM interrupt configuration vector.
*/
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
#endif /* __CPM_360__ */

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#ifndef _M68K_CONTREGS_H
#define _M68K_CONTREGS_H
/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
* space. These are for the mmu's context register, etc.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
/* 3=sun3
4=sun4 (as in sun4 sysmaint student book)
c=sun4c (according to davem) */
#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
#define AC_SYNC_ERR 0x60000000 /* c fault type */
#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
#define AC_M_CXR 0x0200 /* shv Context Register */
#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
#define AC_M_RESET 0x0700 /* hv Reset Reg */
#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
#define AC_M_ITR 0x1300 /* hv Index Tag Register */
#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
#endif /* _M68K_CONTREGS_H */

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#ifndef _M68K_CURRENT_H
#define _M68K_CURRENT_H
#ifdef CONFIG_MMU
register struct task_struct *current __asm__("%a2");
#else
/*
* Rather than dedicate a register (as the m68k source does), we
* just keep a global, we should probably just change it all to be
* current and lose _current_task.
*/
#include <linux/thread_info.h>
struct task_struct;
static inline struct task_struct *get_current(void)
{
return(current_thread_info()->task);
}
#define current get_current()
#endif /* CONFNIG_MMU */
#endif /* !(_M68K_CURRENT_H) */

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arch/m68k/include/asm/delay.h Normal file
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#ifndef _M68K_DELAY_H
#define _M68K_DELAY_H
#include <asm/param.h>
/*
* Copyright (C) 1994 Hamish Macdonald
* Copyright (C) 2004 Greg Ungerer <gerg@uclinux.com>
*
* Delay routines, using a pre-computed "loops_per_jiffy" value.
*/
#if defined(CONFIG_COLDFIRE)
/*
* The ColdFire runs the delay loop at significantly different speeds
* depending upon long word alignment or not. We'll pad it to
* long word alignment which is the faster version.
* The 0x4a8e is of course a 'tstl %fp' instruction. This is better
* than using a NOP (0x4e71) instruction because it executes in one
* cycle not three and doesn't allow for an arbitrary delay waiting
* for bus cycles to finish. Also fp/a6 isn't likely to cause a
* stall waiting for the register to become valid if such is added
* to the coldfire at some stage.
*/
#define DELAY_ALIGN ".balignw 4, 0x4a8e\n\t"
#else
/*
* No instruction alignment required for other m68k types.
*/
#define DELAY_ALIGN
#endif
static inline void __delay(unsigned long loops)
{
__asm__ __volatile__ (
DELAY_ALIGN
"1: subql #1,%0\n\t"
"jcc 1b"
: "=d" (loops)
: "0" (loops));
}
extern void __bad_udelay(void);
#ifdef CONFIG_CPU_HAS_NO_MULDIV64
/*
* The simpler m68k and ColdFire processors do not have a 32*32->64
* multiply instruction. So we need to handle them a little differently.
* We use a bit of shifting and a single 32*32->32 multiply to get close.
* This is a macro so that the const version can factor out the first
* multiply and shift.
*/
#define HZSCALE (268435456 / (1000000 / HZ))
#define __const_udelay(u) \
__delay(((((u) * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6)
#else
static inline void __xdelay(unsigned long xloops)
{
unsigned long tmp;
__asm__ ("mulul %2,%0:%1"
: "=d" (xloops), "=d" (tmp)
: "d" (xloops), "1" (loops_per_jiffy));
__delay(xloops * HZ);
}
/*
* The definition of __const_udelay is specifically made a macro so that
* the const factor (4295 = 2**32 / 1000000) can be optimized out when
* the delay is a const.
*/
#define __const_udelay(n) (__xdelay((n) * 4295))
#endif
static inline void __udelay(unsigned long usecs)
{
__const_udelay(usecs);
}
/*
* Use only for very small delays ( < 1 msec). Should probably use a
* lookup table, really, as the multiplications take much too long with
* short delays. This is a "reasonable" implementation, though (and the
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
#define udelay(n) (__builtin_constant_p(n) ? \
((n) > 20000 ? __bad_udelay() : __const_udelay(n)) : __udelay(n))
/*
* nanosecond delay:
*
* ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) is the number of loops
* per microsecond
*
* 1000 / ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) is the number of
* nanoseconds per loop
*
* So n / ( 1000 / ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) ) would
* be the number of loops for n nanoseconds
*/
/*
* The simpler m68k and ColdFire processors do not have a 32*32->64
* multiply instruction. So we need to handle them a little differently.
* We use a bit of shifting and a single 32*32->32 multiply to get close.
* This is a macro so that the const version can factor out the first
* multiply and shift.
*/
#define HZSCALE (268435456 / (1000000 / HZ))
#define ndelay(n) __delay(DIV_ROUND_UP((n) * ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6), 1000));
#endif /* defined(_M68K_DELAY_H) */

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#ifndef _M68K_DIV64_H
#define _M68K_DIV64_H
#ifdef CONFIG_CPU_HAS_NO_MULDIV64
#include <asm-generic/div64.h>
#else
#include <linux/types.h>
/* n = n / base; return rem; */
#define do_div(n, base) ({ \
union { \
unsigned long n32[2]; \
unsigned long long n64; \
} __n; \
unsigned long __rem, __upper; \
unsigned long __base = (base); \
\
__n.n64 = (n); \
if ((__upper = __n.n32[0])) { \
asm ("divul.l %2,%1:%0" \
: "=d" (__n.n32[0]), "=d" (__upper) \
: "d" (__base), "0" (__n.n32[0])); \
} \
asm ("divu.l %2,%1:%0" \
: "=d" (__n.n32[1]), "=d" (__rem) \
: "d" (__base), "1" (__upper), "0" (__n.n32[1])); \
(n) = __n.n64; \
__rem; \
})
#endif /* CONFIG_CPU_HAS_NO_MULDIV64 */
#endif /* _M68K_DIV64_H */

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#ifndef _M68K_DMA_MAPPING_H
#define _M68K_DMA_MAPPING_H
#include <asm/cache.h>
struct scatterlist;
static inline int dma_supported(struct device *dev, u64 mask)
{
return 1;
}
static inline int dma_set_mask(struct device *dev, u64 mask)
{
return 0;
}
extern void *dma_alloc_coherent(struct device *, size_t,
dma_addr_t *, gfp_t);
extern void dma_free_coherent(struct device *, size_t,
void *, dma_addr_t);
static inline void *dma_alloc_attrs(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag,
struct dma_attrs *attrs)
{
/* attrs is not supported and ignored */
return dma_alloc_coherent(dev, size, dma_handle, flag);
}
static inline void dma_free_attrs(struct device *dev, size_t size,
void *cpu_addr, dma_addr_t dma_handle,
struct dma_attrs *attrs)
{
/* attrs is not supported and ignored */
dma_free_coherent(dev, size, cpu_addr, dma_handle);
}
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *handle, gfp_t flag)
{
return dma_alloc_coherent(dev, size, handle, flag);
}
static inline void dma_free_noncoherent(struct device *dev, size_t size,
void *addr, dma_addr_t handle)
{
dma_free_coherent(dev, size, addr, handle);
}
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction dir)
{
/* we use coherent allocation, so not much to do here. */
}
extern dma_addr_t dma_map_single(struct device *, void *, size_t,
enum dma_data_direction);
static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
size_t size, enum dma_data_direction dir)
{
}
extern dma_addr_t dma_map_page(struct device *, struct page *,
unsigned long, size_t size,
enum dma_data_direction);
static inline void dma_unmap_page(struct device *dev, dma_addr_t address,
size_t size, enum dma_data_direction dir)
{
}
extern int dma_map_sg(struct device *, struct scatterlist *, int,
enum dma_data_direction);
static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nhwentries, enum dma_data_direction dir)
{
}
extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
enum dma_data_direction);
extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
enum dma_data_direction);
static inline void dma_sync_single_range_for_device(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
}
static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
size_t size, enum dma_data_direction dir)
{
}
static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
}
static inline void dma_sync_single_range_for_cpu(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
}
static inline int dma_mapping_error(struct device *dev, dma_addr_t handle)
{
return 0;
}
/* drivers/base/dma-mapping.c */
extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
void *cpu_addr, dma_addr_t dma_addr, size_t size);
extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
void *cpu_addr, dma_addr_t dma_addr,
size_t size);
#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s)
#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s)
#endif /* _M68K_DMA_MAPPING_H */

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#ifndef _M68K_DMA_H
#define _M68K_DMA_H 1
#ifdef CONFIG_COLDFIRE
/*
* ColdFire DMA Model:
* ColdFire DMA supports two forms of DMA: Single and Dual address. Single
* address mode emits a source address, and expects that the device will either
* pick up the data (DMA READ) or source data (DMA WRITE). This implies that
* the device will place data on the correct byte(s) of the data bus, as the
* memory transactions are always 32 bits. This implies that only 32 bit
* devices will find single mode transfers useful. Dual address DMA mode
* performs two cycles: source read and destination write. ColdFire will
* align the data so that the device will always get the correct bytes, thus
* is useful for 8 and 16 bit devices. This is the mode that is supported
* below.
*
* AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
*
* AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
*
* APR/18/2002 : added proper support for MCF5272 DMA controller.
* Arthur Shipkowski (art@videon-central.com)
*/
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
/*
* Set number of channels of DMA on ColdFire for different implementations.
*/
#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
defined(CONFIG_M528x) || defined(CONFIG_M525x)
#define MAX_M68K_DMA_CHANNELS 4
#elif defined(CONFIG_M5272)
#define MAX_M68K_DMA_CHANNELS 1
#elif defined(CONFIG_M53xx)
#define MAX_M68K_DMA_CHANNELS 0
#else
#define MAX_M68K_DMA_CHANNELS 2
#endif
extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
#if !defined(CONFIG_M5272)
#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ 0
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE 1
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD 2
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD 3
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG 4
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG 5
/* I/O to memory, 8 bits, single-address-mode */
#define DMA_MODE_READ_SINGLE 8
/* memory to I/O, 8 bits, single-address-mode */
#define DMA_MODE_WRITE_SINGLE 9
/* I/O to memory, 16 bits, single-address-mode */
#define DMA_MODE_READ_WORD_SINGLE 10
/* memory to I/O, 16 bits, single-address-mode */
#define DMA_MODE_WRITE_WORD_SINGLE 11
/* I/O to memory, 32 bits, single-address-mode */
#define DMA_MODE_READ_LONG_SINGLE 12
/* memory to I/O, 32 bits, single-address-mode */
#define DMA_MODE_WRITE_LONG_SINGLE 13
#else /* CONFIG_M5272 is defined */
/* Source static-address mode */
#define DMA_MODE_SRC_SA_BIT 0x01
/* Two bits to select between all four modes */
#define DMA_MODE_SSIZE_MASK 0x06
/* Offset to shift bits in */
#define DMA_MODE_SSIZE_OFF 0x01
/* Destination static-address mode */
#define DMA_MODE_DES_SA_BIT 0x10
/* Two bits to select between all four modes */
#define DMA_MODE_DSIZE_MASK 0x60
/* Offset to shift bits in */
#define DMA_MODE_DSIZE_OFF 0x05
/* Size modifiers */
#define DMA_MODE_SIZE_LONG 0x00
#define DMA_MODE_SIZE_BYTE 0x01
#define DMA_MODE_SIZE_WORD 0x02
#define DMA_MODE_SIZE_LINE 0x03
/*
* Aliases to help speed quick ports; these may be suboptimal, however. They
* do not include the SINGLE mode modifiers since the MCF5272 does not have a
* mode where the device is in control of its addressing.
*/
/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
#endif /* !defined(CONFIG_M5272) */
#if !defined(CONFIG_M5272)
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("enable_dma(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
}
static __inline__ void disable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
volatile unsigned char *dmapb;
#ifdef DMA_DEBUG
printk("disable_dma(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmapb = (unsigned char *) dma_base_addr[dmanr];
/* Turn off external requests, and stop any DMA in progress */
dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
}
/*
* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*
* This is a NOP for ColdFire. Provide a stub for compatibility.
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
volatile unsigned char *dmabp;
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif
dmabp = (unsigned char *) dma_base_addr[dmanr];
dmawp = (unsigned short *) dma_base_addr[dmanr];
/* Clear config errors */
dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
/* Set command register */
dmawp[MCFDMA_DCR] =
MCFDMA_DCR_INT | /* Enable completion irq */
MCFDMA_DCR_CS | /* Force one xfer per request */
MCFDMA_DCR_AA | /* Enable auto alignment */
/* single-address-mode */
((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
/* sets s_rw (-> r/w) high if Memory to I/0 */
((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
/* Memory to I/O or I/O to Memory */
((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
/* 32 bit, 16 bit or 8 bit transfers */
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
MCFDMA_DCR_SSIZE_BYTE)) |
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
MCFDMA_DCR_DSIZE_BYTE));
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
(int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
#endif
}
/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
volatile unsigned short *dmawp;
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmalp = (unsigned int *) dma_base_addr[dmanr];
/* Determine which address registers are used for memory/device accesses */
if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
/* Source incrementing, must be memory */
dmalp[MCFDMA_SAR] = a;
/* Set dest address, must be device */
dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
} else {
/* Destination incrementing, must be memory */
dmalp[MCFDMA_DAR] = a;
/* Set source address, must be device */
dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
}
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
(int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
(int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
#endif
}
/*
* Specific for Coldfire - sets device address.
* Should be called after the mode set call, and before set DMA address.
*/
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
{
#ifdef DMA_DEBUG
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dma_device_address[dmanr] = a;
}
/*
* NOTE 2: "count" represents _bytes_.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_BCR] = (unsigned short)count;
}
/*
* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* Otherwise, it returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
volatile unsigned short *dmawp;
unsigned short count;
#ifdef DMA_DEBUG
printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
count = dmawp[MCFDMA_BCR];
return((int) count);
}
#else /* CONFIG_M5272 is defined */
/*
* The MCF5272 DMA controller is very different than the controller defined above
* in terms of register mapping. For instance, with the exception of the 16-bit
* interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
*
* The big difference, however, is the lack of device-requested DMA. All modes
* are dual address transfer, and there is no 'device' setup or direction bit.
* You can DMA between a device and memory, between memory and memory, or even between
* two devices directly, with any combination of incrementing and non-incrementing
* addresses you choose. This puts a crimp in distinguishing between the 'device
* address' set up by set_dma_device_addr.
*
* Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
* which will act exactly as above in -- it will look to see if the source is set to
* autoincrement, and if so it will make the source use the set_dma_addr value and the
* destination the set_dma_device_addr value. Otherwise the source will be set to the
* set_dma_device_addr value and the destination will get the set_dma_addr value.
*
* The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
* and make it explicit. Depending on what you're doing, one of these two should work
* for you, but don't mix them in the same transfer setup.
*/
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("enable_dma(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
}
static __inline__ void disable_dma(unsigned int dmanr)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("disable_dma(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
/* Turn off external requests, and stop any DMA in progress */
dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
}
/*
* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*
* This is a NOP for ColdFire. Provide a stub for compatibility.
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
volatile unsigned int *dmalp;
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmawp = (unsigned short *) dma_base_addr[dmanr];
/* Clear config errors */
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
/* Set command register */
dmalp[MCFDMA_DMR] =
MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */
MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */
MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */
/* source static-address-mode */
((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
/* dest static-address-mode */
((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
/* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
(int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
#endif
}
/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
/* Determine which address registers are used for memory/device accesses */
if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
/* Source incrementing, must be memory */
dmalp[MCFDMA_DSAR] = a;
/* Set dest address, must be device */
dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
} else {
/* Destination incrementing, must be memory */
dmalp[MCFDMA_DDAR] = a;
/* Set source address, must be device */
dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
}
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
(int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
(int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
#endif
}
/*
* Specific for Coldfire - sets device address.
* Should be called after the mode set call, and before set DMA address.
*/
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
{
#ifdef DMA_DEBUG
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dma_device_address[dmanr] = a;
}
/*
* NOTE 2: "count" represents _bytes_.
*
* NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmalp[MCFDMA_DBCR] = count;
}
/*
* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* Otherwise, it returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
volatile unsigned int *dmalp;
unsigned int count;
#ifdef DMA_DEBUG
printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
count = dmalp[MCFDMA_DBCR];
return(count);
}
#endif /* !defined(CONFIG_M5272) */
#endif /* CONFIG_COLDFIRE */
/* it's useless on the m68k, but unfortunately needed by the new
bootmem allocator (but this should do it for this) */
#define MAX_DMA_ADDRESS PAGE_OFFSET
#define MAX_DMA_CHANNELS 8
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* _M68K_DMA_H */

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/*
* linux/include/asm-m68k/dsp56k.h - defines and declarations for
* DSP56k device driver
*
* Copyright (C) 1996,1997 Fredrik Noring, lars brinkhoff & Tomas Berndtsson
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/* Used for uploading DSP binary code */
struct dsp56k_upload {
int len;
char __user *bin;
};
/* For the DSP host flags */
struct dsp56k_host_flags {
int dir; /* Bit field. 1 = write output bit, 0 = do nothing.
* 0x0000 means reading only, 0x0011 means
* writing the bits stored in `out' on HF0 and HF1.
* Note that HF2 and HF3 can only be read.
*/
int out; /* Bit field like above. */
int status; /* Host register's current state is returned */
};
/* ioctl command codes */
#define DSP56K_UPLOAD 1 /* Upload DSP binary program */
#define DSP56K_SET_TX_WSIZE 2 /* Host transmit word size (1-4) */
#define DSP56K_SET_RX_WSIZE 3 /* Host receive word size (1-4) */
#define DSP56K_HOST_FLAGS 4 /* Host flag registers */
#define DSP56K_HOST_CMD 5 /* Trig Host Command (0-31) */

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/*
* include/asm-m68k/dma.h
*
* Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
*
* Hacked to fit Sun3x needs by Thomas Bogendoerfer
*/
#ifndef __M68K_DVMA_H
#define __M68K_DVMA_H
#define DVMA_PAGE_SHIFT 13
#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
#define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
extern void dvma_init(void);
extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
int len);
#define dvma_malloc(x) dvma_malloc_align(x, 0)
#define dvma_map(x, y) dvma_map_align(x, y, 0)
#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
extern unsigned long dvma_map_align(unsigned long kaddr, int len,
int align);
extern void *dvma_malloc_align(unsigned long len, unsigned long align);
extern void dvma_unmap(void *baddr);
extern void dvma_free(void *vaddr);
#ifdef CONFIG_SUN3
/* sun3 dvma page support */
/* memory and pmegs potentially reserved for dvma */
#define DVMA_PMEG_START 10
#define DVMA_PMEG_END 16
#define DVMA_START 0xf00000
#define DVMA_END 0xfe0000
#define DVMA_SIZE (DVMA_END-DVMA_START)
#define IOMMU_TOTAL_ENTRIES 128
#define IOMMU_ENTRIES 120
/* empirical kludge -- dvma regions only seem to work right on 0x10000
byte boundaries */
#define DVMA_REGION_SIZE 0x10000
#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
~(DVMA_REGION_SIZE-1))
/* virt <-> phys conversions */
#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
#define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
#define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
#define dvma_vtob(x) dvma_vtop(x)
#define dvma_btov(x) dvma_ptov(x)
static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
int len)
{
return 0;
}
#else /* Sun3x */
/* sun3x dvma page support */
#define DVMA_START 0x0
#define DVMA_END 0xf00000
#define DVMA_SIZE (DVMA_END-DVMA_START)
#define IOMMU_TOTAL_ENTRIES 2048
/* the prom takes the top meg */
#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
#define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
/* everything below this line is specific to dma used for the onboard
ESP scsi on sun3x */
/* Structure to describe the current status of DMA registers on the Sparc */
struct sparc_dma_registers {
__volatile__ unsigned long cond_reg; /* DMA condition register */
__volatile__ unsigned long st_addr; /* Start address of this transfer */
__volatile__ unsigned long cnt; /* How many bytes to transfer */
__volatile__ unsigned long dma_test; /* DMA test register */
};
/* DVMA chip revisions */
enum dvma_rev {
dvmarev0,
dvmaesc1,
dvmarev1,
dvmarev2,
dvmarev3,
dvmarevplus,
dvmahme
};
#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
/* Linux DMA information structure, filled during probe. */
struct Linux_SBus_DMA {
struct Linux_SBus_DMA *next;
struct linux_sbus_device *SBus_dev;
struct sparc_dma_registers *regs;
/* Status, misc info */
int node; /* Prom node for this DMA device */
int running; /* Are we doing DMA now? */
int allocated; /* Are we "owned" by anyone yet? */
/* Transfer information. */
unsigned long addr; /* Start address of current transfer */
int nbytes; /* Size of current transfer */
int realbytes; /* For splitting up large transfers, etc. */
/* DMA revision */
enum dvma_rev revision;
};
extern struct Linux_SBus_DMA *dma_chain;
/* Broken hardware... */
#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
/* Fields in the cond_reg register */
/* First, the version identification bits */
#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
#define DMA_VERS0 0x00000000 /* Sunray DMA version */
#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
#define DMA_VERS1 0x80000000 /* DMA rev 1 */
#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
#define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
/* Values describing the burst-size property from the PROM */
#define DMA_BURST1 0x01
#define DMA_BURST2 0x02
#define DMA_BURST4 0x04
#define DMA_BURST8 0x08
#define DMA_BURST16 0x10
#define DMA_BURST32 0x20
#define DMA_BURST64 0x40
#define DMA_BURSTBITS 0x7f
/* Determine highest possible final transfer address given a base */
#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
/* Yes, I hack a lot of elisp in my spare time... */
#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
#define DMA_BEGINDMA_W(regs) \
((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
#define DMA_BEGINDMA_R(regs) \
((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
/* For certain DMA chips, we need to disable ints upon irq entry
* and turn them back on when we are done. So in any ESP interrupt
* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
* when leaving the handler. You have been warned...
*/
#define DMA_IRQ_ENTRY(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
} while (0)
#define DMA_IRQ_EXIT(dma, dregs) do { \
if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
} while(0)
/* Reset the friggin' thing... */
#define DMA_RESET(dma) do { \
struct sparc_dma_registers *regs = dma->regs; \
/* Let the current FIFO drain itself */ \
sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
/* Reset the logic */ \
regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
__delay(400); /* let the bits set ;) */ \
regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
/* Enable FAST transfers if available */ \
if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
dma->running = 0; \
} while(0)
#endif /* !CONFIG_SUN3 */
#endif /* !(__M68K_DVMA_H) */

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#ifndef __ASMm68k_ELF_H
#define __ASMm68k_ELF_H
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
#include <asm/user.h>
/*
* 68k ELF relocation types
*/
#define R_68K_NONE 0
#define R_68K_32 1
#define R_68K_16 2
#define R_68K_8 3
#define R_68K_PC32 4
#define R_68K_PC16 5
#define R_68K_PC8 6
#define R_68K_GOT32 7
#define R_68K_GOT16 8
#define R_68K_GOT8 9
#define R_68K_GOT32O 10
#define R_68K_GOT16O 11
#define R_68K_GOT8O 12
#define R_68K_PLT32 13
#define R_68K_PLT16 14
#define R_68K_PLT8 15
#define R_68K_PLT32O 16
#define R_68K_PLT16O 17
#define R_68K_PLT8O 18
#define R_68K_COPY 19
#define R_68K_GLOB_DAT 20
#define R_68K_JMP_SLOT 21
#define R_68K_RELATIVE 22
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_m68kfp_struct elf_fpregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_68K)
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB
#define ELF_ARCH EM_68K
/* For SVR4/m68k the function pointer to be registered with `atexit' is
passed in %a1. Although my copy of the ABI has no such statement, it
is actually used on ASV. */
#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE)
#define ELF_EXEC_PAGESIZE 8192
#else
#define ELF_EXEC_PAGESIZE 4096
#endif
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#ifndef CONFIG_SUN3
#define ELF_ET_DYN_BASE 0xD0000000UL
#else
#define ELF_ET_DYN_BASE 0x0D800000UL
#endif
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
/* Bleech. */ \
pr_reg[0] = regs->d1; \
pr_reg[1] = regs->d2; \
pr_reg[2] = regs->d3; \
pr_reg[3] = regs->d4; \
pr_reg[4] = regs->d5; \
pr_reg[7] = regs->a0; \
pr_reg[8] = regs->a1; \
pr_reg[9] = regs->a2; \
pr_reg[14] = regs->d0; \
pr_reg[15] = rdusp(); \
pr_reg[16] = regs->orig_d0; \
pr_reg[17] = regs->sr; \
pr_reg[18] = regs->pc; \
pr_reg[19] = (regs->format << 12) | regs->vector; \
{ \
struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
pr_reg[5] = sw->d6; \
pr_reg[6] = sw->d7; \
pr_reg[10] = sw->a3; \
pr_reg[11] = sw->a4; \
pr_reg[12] = sw->a5; \
pr_reg[13] = sw->a6; \
}
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */
#define ELF_HWCAP (0)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo. */
#define ELF_PLATFORM (NULL)
#endif

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#ifndef __M68K_ENTRY_H
#define __M68K_ENTRY_H
#include <asm/setup.h>
#include <asm/page.h>
#ifdef __ASSEMBLY__
#include <asm/thread_info.h>
#endif
/*
* Stack layout in 'ret_from_exception':
*
* This allows access to the syscall arguments in registers d1-d5
*
* 0(sp) - d1
* 4(sp) - d2
* 8(sp) - d3
* C(sp) - d4
* 10(sp) - d5
* 14(sp) - a0
* 18(sp) - a1
* 1C(sp) - a2
* 20(sp) - d0
* 24(sp) - orig_d0
* 28(sp) - stack adjustment
* 2C(sp) - [ sr ] [ format & vector ]
* 2E(sp) - [ pc-hiword ] [ sr ]
* 30(sp) - [ pc-loword ] [ pc-hiword ]
* 32(sp) - [ format & vector ] [ pc-loword ]
* ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
* M68K COLDFIRE
*/
/* the following macro is used when enabling interrupts */
#if defined(MACH_ATARI_ONLY)
/* block out HSYNC = ipl 2 on the atari */
#define ALLOWINT (~0x500)
#else
/* portable version */
#define ALLOWINT (~0x700)
#endif /* machine compilation types */
#ifdef __ASSEMBLY__
/*
* This defines the normal kernel pt-regs layout.
*
* regs a3-a6 and d6-d7 are preserved by C code
* the kernel doesn't mess with usp unless it needs to
*/
#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
#ifdef CONFIG_COLDFIRE
#ifdef CONFIG_COLDFIRE_SW_A7
/*
* This is made a little more tricky on older ColdFires. There is no
* separate supervisor and user stack pointers. Need to artificially
* construct a usp in software... When doing this we need to disable
* interrupts, otherwise bad things will happen.
*/
.globl sw_usp
.globl sw_ksp
.macro SAVE_ALL_SYS
move #0x2700,%sr /* disable intrs */
btst #5,%sp@(2) /* from user? */
bnes 6f /* no, skip */
movel %sp,sw_usp /* save user sp */
addql #8,sw_usp /* remove exception */
movel sw_ksp,%sp /* kernel sp */
subql #8,%sp /* room for exception */
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
lea %sp@(-32),%sp /* space for 8 regs */
moveml %d1-%d5/%a0-%a2,%sp@
movel sw_usp,%a0 /* get usp */
movel %a0@-,%sp@(PT_OFF_PC) /* copy exception program counter */
movel %a0@-,%sp@(PT_OFF_FORMATVEC)/*copy exception format/vector/sr */
bra 7f
6:
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
lea %sp@(-32),%sp /* space for 8 regs */
moveml %d1-%d5/%a0-%a2,%sp@
7:
.endm
.macro SAVE_ALL_INT
SAVE_ALL_SYS
moveq #-1,%d0 /* not system call entry */
movel %d0,%sp@(PT_OFF_ORIG_D0)
.endm
.macro RESTORE_USER
move #0x2700,%sr /* disable intrs */
movel sw_usp,%a0 /* get usp */
movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
movel %sp@(PT_OFF_FORMATVEC),%a0@-/*copy exception format/vector/sr */
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stkadj */
addql #8,%sp /* remove exception */
movel %sp,sw_ksp /* save ksp */
subql #8,sw_usp /* set exception */
movel sw_usp,%sp /* restore usp */
rte
.endm
.macro RDUSP
movel sw_usp,%a3
.endm
.macro WRUSP
movel %a3,sw_usp
.endm
#else /* !CONFIG_COLDFIRE_SW_A7 */
/*
* Modern ColdFire parts have separate supervisor and user stack
* pointers. Simple load and restore macros for this case.
*/
.macro SAVE_ALL_SYS
move #0x2700,%sr /* disable intrs */
clrl %sp@- /* stkadj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
lea %sp@(-32),%sp /* space for 8 regs */
moveml %d1-%d5/%a0-%a2,%sp@
.endm
.macro SAVE_ALL_INT
move #0x2700,%sr /* disable intrs */
clrl %sp@- /* stkadj */
pea -1:w /* orig d0 */
movel %d0,%sp@- /* d0 */
lea %sp@(-32),%sp /* space for 8 regs */
moveml %d1-%d5/%a0-%a2,%sp@
.endm
.macro RESTORE_USER
moveml %sp@,%d1-%d5/%a0-%a2
lea %sp@(32),%sp /* space for 8 regs */
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stkadj */
rte
.endm
.macro RDUSP
/*move %usp,%a3*/
.word 0x4e6b
.endm
.macro WRUSP
/*move %a3,%usp*/
.word 0x4e63
.endm
#endif /* !CONFIG_COLDFIRE_SW_A7 */
.macro SAVE_SWITCH_STACK
lea %sp@(-24),%sp /* 6 regs */
moveml %a3-%a6/%d6-%d7,%sp@
.endm
.macro RESTORE_SWITCH_STACK
moveml %sp@,%a3-%a6/%d6-%d7
lea %sp@(24),%sp /* 6 regs */
.endm
#else /* !CONFIG_COLDFIRE */
/*
* All other types of m68k parts (68000, 680x0, CPU32) have the same
* entry and exit code.
*/
/*
* a -1 in the orig_d0 field signifies
* that the stack frame is NOT for syscall
*/
.macro SAVE_ALL_INT
clrl %sp@- /* stk_adj */
pea -1:w /* orig d0 */
movel %d0,%sp@- /* d0 */
moveml %d1-%d5/%a0-%a2,%sp@-
.endm
.macro SAVE_ALL_SYS
clrl %sp@- /* stk_adj */
movel %d0,%sp@- /* orig d0 */
movel %d0,%sp@- /* d0 */
moveml %d1-%d5/%a0-%a2,%sp@-
.endm
.macro RESTORE_ALL
moveml %sp@+,%a0-%a2/%d1-%d5
movel %sp@+,%d0
addql #4,%sp /* orig d0 */
addl %sp@+,%sp /* stk adj */
rte
.endm
.macro SAVE_SWITCH_STACK
moveml %a3-%a6/%d6-%d7,%sp@-
.endm
.macro RESTORE_SWITCH_STACK
moveml %sp@+,%a3-%a6/%d6-%d7
.endm
#endif /* !CONFIG_COLDFIRE */
/*
* Register %a2 is reserved and set to current task on MMU enabled systems.
* Non-MMU systems do not reserve %a2 in this way, and this definition is
* not used for them.
*/
#ifdef CONFIG_MMU
#define curptr a2
#define GET_CURRENT(tmp) get_current tmp
.macro get_current reg=%d0
movel %sp,\reg
andl #-THREAD_SIZE,\reg
movel \reg,%curptr
movel %curptr@,%curptr
.endm
#else
#define GET_CURRENT(tmp)
#endif /* CONFIG_MMU */
#else /* C source */
#define STR(X) STR1(X)
#define STR1(X) #X
#define SAVE_ALL_INT \
"clrl %%sp@-;" /* stk_adj */ \
"pea -1:w;" /* orig d0 = -1 */ \
"movel %%d0,%%sp@-;" /* d0 */ \
"moveml %%d1-%%d5/%%a0-%%a2,%%sp@-"
#define GET_CURRENT(tmp) \
"movel %%sp,"#tmp"\n\t" \
"andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
"movel "#tmp",%%a2\n\t" \
"movel %%a2@,%%a2"
#endif
#endif /* __M68K_ENTRY_H */

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#ifndef _ASM_FB_H_
#define _ASM_FB_H_
#include <linux/fb.h>
#include <linux/fs.h>
#include <asm/page.h>
#include <asm/setup.h>
#ifdef CONFIG_MMU
#ifdef CONFIG_SUN3
static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
unsigned long off)
{
pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE;
}
#else
static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
unsigned long off)
{
if (CPU_IS_020_OR_030)
pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030;
if (CPU_IS_040_OR_060) {
pgprot_val(vma->vm_page_prot) &= _CACHEMASK040;
/* Use no-cache mode, serialized */
pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S;
}
}
#endif /* CONFIG_SUN3 */
#else
#define fb_pgprotect(...) do {} while (0)
#endif /* CONFIG_MMU */
static inline int fb_is_primary_device(struct fb_info *info)
{
return 0;
}
#endif /* _ASM_FB_H_ */

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#ifndef __LINUX_FBIO_H
#define __LINUX_FBIO_H
#include <linux/compiler.h>
#include <linux/types.h>
/* Constants used for fbio SunOS compatibility */
/* (C) 1996 Miguel de Icaza */
/* Frame buffer types */
#define FBTYPE_NOTYPE -1
#define FBTYPE_SUN1BW 0 /* mono */
#define FBTYPE_SUN1COLOR 1
#define FBTYPE_SUN2BW 2
#define FBTYPE_SUN2COLOR 3
#define FBTYPE_SUN2GP 4
#define FBTYPE_SUN5COLOR 5
#define FBTYPE_SUN3COLOR 6
#define FBTYPE_MEMCOLOR 7
#define FBTYPE_SUN4COLOR 8
#define FBTYPE_NOTSUN1 9
#define FBTYPE_NOTSUN2 10
#define FBTYPE_NOTSUN3 11
#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
#define FBTYPE_SUNROP_COLOR 13
#define FBTYPE_SUNFB_VIDEO 14
#define FBTYPE_SUNGIFB 15
#define FBTYPE_SUNGPLAS 16
#define FBTYPE_SUNGP3 17
#define FBTYPE_SUNGT 18
#define FBTYPE_SUNLEO 19 /* zx Leo card */
#define FBTYPE_MDICOLOR 20 /* cg14 */
#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
/* Does not seem to be listed in the Sun file either */
#define FBTYPE_CREATOR 22
#define FBTYPE_PCI_IGA1682 23
#define FBTYPE_P9100COLOR 24
#define FBTYPE_PCI_GENERIC 1000
#define FBTYPE_PCI_MACH64 1001
/* fbio ioctls */
/* Returned by FBIOGTYPE */
struct fbtype {
int fb_type; /* fb type, see above */
int fb_height; /* pixels */
int fb_width; /* pixels */
int fb_depth;
int fb_cmsize; /* color map entries */
int fb_size; /* fb size in bytes */
};
#define FBIOGTYPE _IOR('F', 0, struct fbtype)
struct fbcmap {
int index; /* first element (0 origin) */
int count;
unsigned char __user *red;
unsigned char __user *green;
unsigned char __user *blue;
};
#ifdef __KERNEL__
#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
#else
#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
#endif
/* # of device specific values */
#define FB_ATTR_NDEVSPECIFIC 8
/* # of possible emulations */
#define FB_ATTR_NEMUTYPES 4
struct fbsattr {
int flags;
int emu_type; /* -1 if none */
int dev_specific[FB_ATTR_NDEVSPECIFIC];
};
struct fbgattr {
int real_type; /* real frame buffer type */
int owner; /* unknown */
struct fbtype fbtype; /* real frame buffer fbtype */
struct fbsattr sattr;
int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
};
#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
#define FBIOSVIDEO _IOW('F', 7, int)
#define FBIOGVIDEO _IOR('F', 8, int)
struct fbcursor {
short set; /* what to set, choose from the list above */
short enable; /* cursor on/off */
struct fbcurpos pos; /* cursor position */
struct fbcurpos hot; /* cursor hot spot */
struct fbcmap cmap; /* color map info */
struct fbcurpos size; /* cursor bit map size */
char __user *image; /* cursor image bits */
char __user *mask; /* cursor mask bits */
};
/* set/get cursor attributes/shape */
#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
/* set/get cursor position */
#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
/* get max cursor size */
#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
/* wid manipulation */
struct fb_wid_alloc {
#define FB_WID_SHARED_8 0
#define FB_WID_SHARED_24 1
#define FB_WID_DBL_8 2
#define FB_WID_DBL_24 3
__u32 wa_type;
__s32 wa_index; /* Set on return */
__u32 wa_count;
};
struct fb_wid_item {
__u32 wi_type;
__s32 wi_index;
__u32 wi_attrs;
__u32 wi_values[32];
};
struct fb_wid_list {
__u32 wl_flags;
__u32 wl_count;
struct fb_wid_item *wl_list;
};
#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
/* Creator ioctls */
#define FFB_IOCTL ('F'<<8)
#define FFB_SYS_INFO (FFB_IOCTL|80)
#define FFB_CLUTREAD (FFB_IOCTL|81)
#define FFB_CLUTPOST (FFB_IOCTL|82)
#define FFB_SETDIAGMODE (FFB_IOCTL|83)
#define FFB_GETMONITORID (FFB_IOCTL|84)
#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
#define FFB_SETSERVER (FFB_IOCTL|87)
#define FFB_SETOVCTL (FFB_IOCTL|88)
#define FFB_GETOVCTL (FFB_IOCTL|89)
#define FFB_GETSAXNUM (FFB_IOCTL|90)
#define FFB_FBDEBUG (FFB_IOCTL|91)
/* Cg14 ioctls */
#define MDI_IOCTL ('M'<<8)
#define MDI_RESET (MDI_IOCTL|1)
#define MDI_GET_CFGINFO (MDI_IOCTL|2)
#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
# define MDI_32_PIX 32
# define MDI_16_PIX 16
# define MDI_8_PIX 8
struct mdi_cfginfo {
int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
int mdi_type; /* FBTYPE name */
int mdi_height; /* height */
int mdi_width; /* width */
int mdi_size; /* available ram */
int mdi_mode; /* 8bpp, 16bpp or 32bpp */
int mdi_pixfreq; /* pixel clock (from PROM) */
};
/* SparcLinux specific ioctl for the MDI, should be replaced for
* the SET_XLUT/SET_CLUTn ioctls instead
*/
#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
/* leo & ffb ioctls */
struct fb_clut_alloc {
__u32 clutid; /* Set on return */
__u32 flag;
__u32 index;
};
struct fb_clut {
#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
char * red;
char * green;
char * blue;
};
struct fb_clut32 {
__u32 flag;
__u32 clutid;
__u32 offset;
__u32 count;
__u32 red;
__u32 green;
__u32 blue;
};
#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
#ifdef __KERNEL__
/* Addresses on the fd of a cgsix that are mappable */
#define CG6_FBC 0x70000000
#define CG6_TEC 0x70001000
#define CG6_BTREGS 0x70002000
#define CG6_FHC 0x70004000
#define CG6_THC 0x70005000
#define CG6_ROM 0x70006000
#define CG6_RAM 0x70016000
#define CG6_DHC 0x80000000
#define CG3_MMAP_OFFSET 0x4000000
/* Addresses on the fd of a tcx that are mappable */
#define TCX_RAM8BIT 0x00000000
#define TCX_RAM24BIT 0x01000000
#define TCX_UNK3 0x10000000
#define TCX_UNK4 0x20000000
#define TCX_CONTROLPLANE 0x28000000
#define TCX_UNK6 0x30000000
#define TCX_UNK7 0x38000000
#define TCX_TEC 0x70000000
#define TCX_BTREGS 0x70002000
#define TCX_THC 0x70004000
#define TCX_DHC 0x70008000
#define TCX_ALT 0x7000a000
#define TCX_SYNC 0x7000e000
#define TCX_UNK2 0x70010000
/* CG14 definitions */
/* Offsets into the OBIO space: */
#define CG14_REGS 0 /* registers */
#define CG14_CURSORREGS 0x1000 /* cursor registers */
#define CG14_DACREGS 0x2000 /* DAC registers */
#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
#define CG14_CLUT1 0x4000 /* Color Look Up Table */
#define CG14_CLUT2 0x5000 /* Color Look Up Table */
#define CG14_CLUT3 0x6000 /* Color Look Up Table */
#define CG14_AUTO 0xf000
#endif /* KERNEL */
/* These are exported to userland for applications to use */
/* Mappable offsets for the cg14: control registers */
#define MDI_DIRECT_MAP 0x10000000
#define MDI_CTLREG_MAP 0x20000000
#define MDI_CURSOR_MAP 0x30000000
#define MDI_SHDW_VRT_MAP 0x40000000
/* Mappable offsets for the cg14: frame buffer resolutions */
/* 32 bits */
#define MDI_CHUNKY_XBGR_MAP 0x50000000
#define MDI_CHUNKY_BGR_MAP 0x60000000
/* 16 bits */
#define MDI_PLANAR_X16_MAP 0x70000000
#define MDI_PLANAR_C16_MAP 0x80000000
/* 8 bit is done as CG3 MMAP offset */
/* 32 bits, planar */
#define MDI_PLANAR_X32_MAP 0x90000000
#define MDI_PLANAR_B32_MAP 0xa0000000
#define MDI_PLANAR_G32_MAP 0xb0000000
#define MDI_PLANAR_R32_MAP 0xc0000000
/* Mappable offsets on leo */
#define LEO_SS0_MAP 0x00000000
#define LEO_LC_SS0_USR_MAP 0x00800000
#define LEO_LD_SS0_MAP 0x00801000
#define LEO_LX_CURSOR_MAP 0x00802000
#define LEO_SS1_MAP 0x00803000
#define LEO_LC_SS1_USR_MAP 0x01003000
#define LEO_LD_SS1_MAP 0x01004000
#define LEO_UNK_MAP 0x01005000
#define LEO_LX_KRN_MAP 0x01006000
#define LEO_LC_SS0_KRN_MAP 0x01007000
#define LEO_LC_SS1_KRN_MAP 0x01008000
#define LEO_LD_GBL_MAP 0x01009000
#define LEO_UNK2_MAP 0x0100a000
#ifdef __KERNEL__
struct fbcmap32 {
int index; /* first element (0 origin) */
int count;
u32 red;
u32 green;
u32 blue;
};
#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
struct fbcursor32 {
short set; /* what to set, choose from the list above */
short enable; /* cursor on/off */
struct fbcurpos pos; /* cursor position */
struct fbcurpos hot; /* cursor hot spot */
struct fbcmap32 cmap; /* color map info */
struct fbcurpos size; /* cursor bit map size */
u32 image; /* cursor image bits */
u32 mask; /* cursor mask bits */
};
#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
#endif
#endif /* __LINUX_FBIO_H */

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/*
* include/asm-m68knommu/flat.h -- uClinux flat-format executables
*/
#ifndef __M68KNOMMU_FLAT_H__
#define __M68KNOMMU_FLAT_H__
#define flat_argvp_envp_on_stack() 1
#define flat_old_ram_flag(flags) (flags)
#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
#define flat_get_relocate_addr(rel) (rel)
static inline int flat_set_persistent(unsigned long relval,
unsigned long *persistent)
{
return 0;
}
#endif /* __M68KNOMMU_FLAT_H__ */

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/*
* Implementation independent bits of the Floppy driver.
*
* much of this file is derived from what was originally the Q40 floppy driver.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999, 2000, 2001
*
* Sun3x support added 2/4/2000 Sam Creasey (sammy@sammy.net)
*
*/
#include <asm/io.h>
#include <linux/vmalloc.h>
asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id);
/* constants... */
#undef MAX_DMA_ADDRESS
#define MAX_DMA_ADDRESS 0x00 /* nothing like that */
/*
* Again, the CMOS information doesn't work on m68k..
*/
#define FLOPPY0_TYPE (MACH_IS_Q40 ? 6 : 4)
#define FLOPPY1_TYPE 0
/* basically PC init + set use_virtual_dma */
#define FDC1 m68k_floppy_init()
#define N_FDC 1
#define N_DRIVE 8
/* vdma globals adapted from asm-i386/floppy.h */
static int virtual_dma_count=0;
static int virtual_dma_residue=0;
static char *virtual_dma_addr=NULL;
static int virtual_dma_mode=0;
static int doing_pdma=0;
#include <asm/sun3xflop.h>
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
static __inline__ unsigned char fd_inb(int port)
{
if(MACH_IS_Q40)
return inb_p(port);
else if(MACH_IS_SUN3X)
return sun3x_82072_fd_inb(port);
return 0;
}
static __inline__ void fd_outb(unsigned char value, int port)
{
if(MACH_IS_Q40)
outb_p(value, port);
else if(MACH_IS_SUN3X)
sun3x_82072_fd_outb(value, port);
}
static int fd_request_irq(void)
{
if(MACH_IS_Q40)
return request_irq(FLOPPY_IRQ, floppy_hardint,
0, "floppy", floppy_hardint);
else if(MACH_IS_SUN3X)
return sun3xflop_request_irq();
return -ENXIO;
}
static void fd_free_irq(void)
{
if(MACH_IS_Q40)
free_irq(FLOPPY_IRQ, floppy_hardint);
}
#define fd_request_dma() vdma_request_dma(FLOPPY_DMA,"floppy")
#define fd_get_dma_residue() vdma_get_dma_residue(FLOPPY_DMA)
#define fd_dma_mem_alloc(size) vdma_mem_alloc(size)
#define fd_dma_setup(addr, size, mode, io) vdma_dma_setup(addr, size, mode, io)
#define fd_enable_irq() /* nothing... */
#define fd_disable_irq() /* nothing... */
#define fd_free_dma() /* nothing */
/* No 64k boundary crossing problems on Q40 - no DMA at all */
#define CROSS_64KB(a,s) (0)
#define DMA_MODE_READ 0x44 /* i386 look-alike */
#define DMA_MODE_WRITE 0x48
static int m68k_floppy_init(void)
{
use_virtual_dma =1;
can_use_virtual_dma = 1;
if (MACH_IS_Q40)
return 0x3f0;
else if(MACH_IS_SUN3X)
return sun3xflop_init();
else
return -1;
}
static int vdma_request_dma(unsigned int dmanr, const char * device_id)
{
return 0;
}
static int vdma_get_dma_residue(unsigned int dummy)
{
return virtual_dma_count + virtual_dma_residue;
}
static unsigned long vdma_mem_alloc(unsigned long size)
{
return (unsigned long) vmalloc(size);
}
static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
{
vfree((void *)addr);
}
#define fd_dma_mem_free(addr,size) _fd_dma_mem_free(addr, size)
/* choose_dma_mode ???*/
static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
{
doing_pdma = 1;
virtual_dma_port = (MACH_IS_Q40 ? io : 0);
virtual_dma_mode = (mode == DMA_MODE_WRITE);
virtual_dma_addr = addr;
virtual_dma_count = size;
virtual_dma_residue = 0;
return 0;
}
static void fd_disable_dma(void)
{
doing_pdma = 0;
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
}
/* this is the only truly Q40 specific function */
asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id)
{
register unsigned char st;
#undef TRACE_FLPY_INT
#define NO_FLOPPY_ASSEMBLER
#ifdef TRACE_FLPY_INT
static int calls=0;
static int bytes=0;
static int dma_wait=0;
#endif
if(!doing_pdma) {
floppy_interrupt(irq, dev_id);
return IRQ_HANDLED;
}
#ifdef TRACE_FLPY_INT
if(!calls)
bytes = virtual_dma_count;
#endif
{
register int lcount;
register char *lptr;
/* serve 1st byte fast: */
st=1;
for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
lcount; lcount--, lptr++) {
st=inb(virtual_dma_port+4) & 0xa0 ;
if(st != 0xa0)
break;
if(virtual_dma_mode)
outb_p(*lptr, virtual_dma_port+5);
else
*lptr = inb_p(virtual_dma_port+5);
}
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
st = inb(virtual_dma_port+4);
}
#ifdef TRACE_FLPY_INT
calls++;
#endif
if(st == 0x20)
return IRQ_HANDLED;
if(!(st & 0x20)) {
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
#ifdef TRACE_FLPY_INT
printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
virtual_dma_count, virtual_dma_residue, calls, bytes,
dma_wait);
calls = 0;
dma_wait=0;
#endif
doing_pdma = 0;
floppy_interrupt(irq, dev_id);
return IRQ_HANDLED;
}
#ifdef TRACE_FLPY_INT
if(!virtual_dma_count)
dma_wait++;
#endif
return IRQ_HANDLED;
}
#define EXTRA_FLOPPY_PARAMS

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#ifndef __M68K_FPU_H
#define __M68K_FPU_H
/*
* MAX floating point unit state size (FSAVE/FRESTORE)
*/
#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
#define FPSTATESIZE (216)
#elif defined(CONFIG_M68040)
#define FPSTATESIZE (96)
#elif defined(CONFIG_M68KFPU_EMU)
#define FPSTATESIZE (28)
#elif defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
#define FPSTATESIZE (16)
#elif defined(CONFIG_M68060)
#define FPSTATESIZE (12)
#else
#define FPSTATESIZE (0)
#endif
#endif /* __M68K_FPU_H */

1
arch/m68k/include/asm/ftrace.h Normal file
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/* empty */

94
arch/m68k/include/asm/futex.h Normal file
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#ifndef _ASM_M68K_FUTEX_H
#define _ASM_M68K_FUTEX_H
#ifdef __KERNEL__
#if !defined(CONFIG_MMU)
#include <asm-generic/futex.h>
#else /* CONFIG_MMU */
#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/errno.h>
static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
u32 oldval, u32 newval)
{
u32 val;
if (unlikely(get_user(val, uaddr) != 0))
return -EFAULT;
if (val == oldval && unlikely(put_user(newval, uaddr) != 0))
return -EFAULT;
*uval = val;
return 0;
}
static inline int
futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
{
int op = (encoded_op >> 28) & 7;
int cmp = (encoded_op >> 24) & 15;
int oparg = (encoded_op << 8) >> 20;
int cmparg = (encoded_op << 20) >> 20;
int oldval, ret;
u32 tmp;
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
oparg = 1 << oparg;
pagefault_disable(); /* implies preempt_disable() */
ret = -EFAULT;
if (unlikely(get_user(oldval, uaddr) != 0))
goto out_pagefault_enable;
ret = 0;
tmp = oldval;
switch (op) {
case FUTEX_OP_SET:
tmp = oparg;
break;
case FUTEX_OP_ADD:
tmp += oparg;
break;
case FUTEX_OP_OR:
tmp |= oparg;
break;
case FUTEX_OP_ANDN:
tmp &= ~oparg;
break;
case FUTEX_OP_XOR:
tmp ^= oparg;
break;
default:
ret = -ENOSYS;
}
if (ret == 0 && unlikely(put_user(tmp, uaddr) != 0))
ret = -EFAULT;
out_pagefault_enable:
pagefault_enable(); /* subsumes preempt_enable() */
if (ret == 0) {
switch (cmp) {
case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
default: ret = -ENOSYS;
}
}
return ret;
}
#endif /* CONFIG_MMU */
#endif /* __KERNEL__ */
#endif /* _ASM_M68K_FUTEX_H */

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/*
* Coldfire generic GPIO support
*
* (C) Copyright 2009, Steven King <sfking@fdwdc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef coldfire_gpio_h
#define coldfire_gpio_h
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfgpio.h>
/*
* The Generic GPIO functions
*
* If the gpio is a compile time constant and is one of the Coldfire gpios,
* use the inline version, otherwise dispatch thru gpiolib.
*/
static inline int gpio_get_value(unsigned gpio)
{
if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
else
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) {
if (gpio < MCFGPIO_SCR_START) {
unsigned long flags;
MCFGPIO_PORTTYPE data;
local_irq_save(flags);
data = mcfgpio_read(__mcfgpio_podr(gpio));
if (value)
data |= mcfgpio_bit(gpio);
else
data &= ~mcfgpio_bit(gpio);
mcfgpio_write(data, __mcfgpio_podr(gpio));
local_irq_restore(flags);
} else {
if (value)
mcfgpio_write(mcfgpio_bit(gpio),
MCFGPIO_SETR_PORT(gpio));
else
mcfgpio_write(~mcfgpio_bit(gpio),
MCFGPIO_CLRR_PORT(gpio));
}
} else
__gpio_set_value(gpio, value);
}
static inline int gpio_to_irq(unsigned gpio)
{
#if defined(MCFGPIO_IRQ_MIN)
if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
#else
if (gpio < MCFGPIO_IRQ_MAX)
#endif
return gpio + MCFGPIO_IRQ_VECBASE;
else
return __gpio_to_irq(gpio);
}
static inline int irq_to_gpio(unsigned irq)
{
return (irq >= MCFGPIO_IRQ_VECBASE &&
irq < (MCFGPIO_IRQ_VECBASE + MCFGPIO_IRQ_MAX)) ?
irq - MCFGPIO_IRQ_VECBASE : -ENXIO;
}
static inline int gpio_cansleep(unsigned gpio)
{
return gpio < MCFGPIO_PIN_MAX ? 0 : __gpio_cansleep(gpio);
}
#ifndef CONFIG_GPIOLIB
static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
{
int err;
err = gpio_request(gpio, label);
if (err)
return err;
if (flags & GPIOF_DIR_IN)
err = gpio_direction_input(gpio);
else
err = gpio_direction_output(gpio,
(flags & GPIOF_INIT_HIGH) ? 1 : 0);
if (err)
gpio_free(gpio);
return err;
}
#endif /* !CONFIG_GPIOLIB */
#endif

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#ifndef __M68K_HARDIRQ_H
#define __M68K_HARDIRQ_H
#include <linux/threads.h>
#include <linux/cache.h>
#include <asm/irq.h>
#ifdef CONFIG_MMU
static inline void ack_bad_irq(unsigned int irq)
{
pr_crit("unexpected IRQ trap at vector %02x\n", irq);
}
/* entry.S is sensitive to the offsets of these fields */
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
#else
#include <asm-generic/hardirq.h>
#endif /* !CONFIG_MMU */
#endif

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#ifndef _M68K_HP300HW_H
#define _M68K_HP300HW_H
#include <asm/bootinfo-hp300.h>
extern unsigned long hp300_model;
#endif /* _M68K_HP300HW_H */

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/* Routines to test for presence/absence of hardware registers:
* see arch/m68k/mm/hwtest.c.
* -- PMM <pmaydell@chiark.greenend.org.uk> 05/1998
*
* Removed __init from decls. We might want them in modules, and
* the code is tiny anyway. 16/5/98 pb
*/
#ifndef __ASM_HWTEST_H
#define __ASM_HWTEST_H
extern int hwreg_present(volatile void *regp);
extern int hwreg_write(volatile void *regp, unsigned short val);
#endif

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/*
* Copyright (C) 1994-1996 Linus Torvalds & authors
*/
/* Copyright(c) 1996 Kars de Jong */
/* Based on the ide driver from 1.2.13pl8 */
/*
* Credits (alphabetical):
*
* - Bjoern Brauel
* - Kars de Jong
* - Torsten Ebeling
* - Dwight Engen
* - Thorsten Floeck
* - Roman Hodek
* - Guenther Kelleter
* - Chris Lawrence
* - Michael Rausch
* - Christian Sauer
* - Michael Schmitz
* - Jes Soerensen
* - Michael Thurm
* - Geert Uytterhoeven
*/
#ifndef _M68K_IDE_H
#define _M68K_IDE_H
#ifdef __KERNEL__
#include <asm/setup.h>
#include <asm/io.h>
#include <asm/irq.h>
#ifdef CONFIG_MMU
/*
* Get rid of defs from io.h - ide has its private and conflicting versions
* Since so far no single m68k platform uses ISA/PCI I/O space for IDE, we
* always use the `raw' MMIO versions
*/
#undef readb
#undef readw
#undef writeb
#undef writew
#define readb in_8
#define readw in_be16
#define __ide_mm_insw(port, addr, n) raw_insw((u16 *)port, addr, n)
#define __ide_mm_insl(port, addr, n) raw_insl((u32 *)port, addr, n)
#define writeb(val, port) out_8(port, val)
#define writew(val, port) out_be16(port, val)
#define __ide_mm_outsw(port, addr, n) raw_outsw((u16 *)port, addr, n)
#define __ide_mm_outsl(port, addr, n) raw_outsl((u32 *)port, addr, n)
#else
#define __ide_mm_insw(port, addr, n) io_insw((unsigned int)port, addr, n)
#define __ide_mm_insl(port, addr, n) io_insl((unsigned int)port, addr, n)
#define __ide_mm_outsw(port, addr, n) io_outsw((unsigned int)port, addr, n)
#define __ide_mm_outsl(port, addr, n) io_outsl((unsigned int)port, addr, n)
#endif /* CONFIG_MMU */
#endif /* __KERNEL__ */
#endif /* _M68K_IDE_H */

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#ifndef _M68K_IDPROM_H
#define _M68K_IDPROM_H
/*
* idprom.h: Macros and defines for idprom routines
*
* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
*/
#include <linux/types.h>
struct idprom {
u8 id_format; /* Format identifier (always 0x01) */
u8 id_machtype; /* Machine type */
u8 id_ethaddr[6]; /* Hardware ethernet address */
s32 id_date; /* Date of manufacture */
u32 id_sernum:24; /* Unique serial number */
u8 id_cksum; /* Checksum - xor of the data bytes */
u8 reserved[16];
};
extern struct idprom *idprom;
extern void idprom_init(void);
/* Sun3: in control space */
#define SUN3_IDPROM_BASE 0x00000000
#endif /* !(_M68K_IDPROM_H) */

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#ifndef _SUN3_INTERSIL_H
#define _SUN3_INTERSIL_H
/* bits 0 and 1 */
#define INTERSIL_FREQ_32K 0x00
#define INTERSIL_FREQ_1M 0x01
#define INTERSIL_FREQ_2M 0x02
#define INTERSIL_FREQ_4M 0x03
/* bit 2 */
#define INTERSIL_12H_MODE 0x00
#define INTERSIL_24H_MODE 0x04
/* bit 3 */
#define INTERSIL_STOP 0x00
#define INTERSIL_RUN 0x08
/* bit 4 */
#define INTERSIL_INT_ENABLE 0x10
#define INTERSIL_INT_DISABLE 0x00
/* bit 5 */
#define INTERSIL_MODE_NORMAL 0x00
#define INTERSIL_MODE_TEST 0x20
#define INTERSIL_HZ_100_MASK 0x02
struct intersil_dt {
unsigned char csec;
unsigned char hour;
unsigned char minute;
unsigned char second;
unsigned char month;
unsigned char day;
unsigned char year;
unsigned char weekday;
};
struct intersil_7170 {
struct intersil_dt counter;
struct intersil_dt alarm;
unsigned char int_reg;
unsigned char cmd_reg;
};
extern volatile char* clock_va;
#define intersil_clock ((volatile struct intersil_7170 *) clock_va)
#define intersil_clear() (void)intersil_clock->int_reg
#endif

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#ifdef __uClinux__
#include <asm/io_no.h>
#else
#include <asm/io_mm.h>
#endif

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/*
* linux/include/asm-m68k/io.h
*
* 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
* IO access
* - added Q40 support
* - added skeleton for GG-II and Amiga PCMCIA
* 2/3/01 RZ: - moved a few more defs into raw_io.h
*
* inX/outX should not be used by any driver unless it does
* ISA access. Other drivers should use function defined in raw_io.h
* or define its own macros on top of these.
*
* inX(),outX() are for ISA I/O
* isa_readX(),isa_writeX() are for ISA memory
*/
#ifndef _IO_H
#define _IO_H
#ifdef __KERNEL__
#include <linux/compiler.h>
#include <asm/raw_io.h>
#include <asm/virtconvert.h>
#include <asm-generic/iomap.h>
#ifdef CONFIG_ATARI
#include <asm/atarihw.h>
#endif
/*
* IO/MEM definitions for various ISA bridges
*/
#ifdef CONFIG_Q40
#define q40_isa_io_base 0xff400000
#define q40_isa_mem_base 0xff800000
#define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
#define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr)))
#define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr)))
#define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr)))
#define MULTI_ISA 0
#endif /* Q40 */
#ifdef CONFIG_AMIGA_PCMCIA
#include <asm/amigayle.h>
#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
#ifndef MULTI_ISA
#define MULTI_ISA 0
#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
#endif /* AMIGA_PCMCIA */
#ifdef CONFIG_ATARI_ROM_ISA
#define enec_isa_read_base 0xfffa0000
#define enec_isa_write_base 0xfffb0000
#define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
#define ENEC_ISA_IO_W(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
#define ENEC_ISA_MEM_B(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
#define ENEC_ISA_MEM_W(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
#ifndef MULTI_ISA
#define MULTI_ISA 0
#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
#endif /* ATARI_ROM_ISA */
#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
#define HAVE_ARCH_PIO_SIZE
#define PIO_OFFSET 0
#define PIO_MASK 0xffff
#define PIO_RESERVED 0x10000
u8 mcf_pci_inb(u32 addr);
u16 mcf_pci_inw(u32 addr);
u32 mcf_pci_inl(u32 addr);
void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
void mcf_pci_outb(u8 v, u32 addr);
void mcf_pci_outw(u16 v, u32 addr);
void mcf_pci_outl(u32 v, u32 addr);
void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
#define inb mcf_pci_inb
#define inb_p mcf_pci_inb
#define inw mcf_pci_inw
#define inw_p mcf_pci_inw
#define inl mcf_pci_inl
#define inl_p mcf_pci_inl
#define insb mcf_pci_insb
#define insw mcf_pci_insw
#define insl mcf_pci_insl
#define outb mcf_pci_outb
#define outb_p mcf_pci_outb
#define outw mcf_pci_outw
#define outw_p mcf_pci_outw
#define outl mcf_pci_outl
#define outl_p mcf_pci_outl
#define outsb mcf_pci_outsb
#define outsw mcf_pci_outsw
#define outsl mcf_pci_outsl
#define readb(addr) in_8(addr)
#define writeb(v, addr) out_8((addr), (v))
#define readw(addr) in_le16(addr)
#define writew(v, addr) out_le16((addr), (v))
#elif defined(CONFIG_ISA) || defined(CONFIG_ATARI_ROM_ISA)
#if MULTI_ISA == 0
#undef MULTI_ISA
#endif
#define ISA_TYPE_Q40 (1)
#define ISA_TYPE_AG (2)
#define ISA_TYPE_ENEC (3)
#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
#define ISA_TYPE ISA_TYPE_Q40
#define ISA_SEX 0
#endif
#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
#define ISA_TYPE ISA_TYPE_AG
#define ISA_SEX 1
#endif
#if defined(CONFIG_ATARI_ROM_ISA) && !defined(MULTI_ISA)
#define ISA_TYPE ISA_TYPE_ENEC
#define ISA_SEX 0
#endif
#ifdef MULTI_ISA
extern int isa_type;
extern int isa_sex;
#define ISA_TYPE isa_type
#define ISA_SEX isa_sex
#endif
/*
* define inline addr translation functions. Normally only one variant will
* be compiled in so the case statement will be optimised away
*/
static inline u8 __iomem *isa_itb(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr);
#endif
#ifdef CONFIG_ATARI_ROM_ISA
case ISA_TYPE_ENEC: return (u8 __iomem *)ENEC_ISA_IO_B(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
static inline u16 __iomem *isa_itw(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr);
#endif
#ifdef CONFIG_ATARI_ROM_ISA
case ISA_TYPE_ENEC: return (u16 __iomem *)ENEC_ISA_IO_W(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
static inline u32 __iomem *isa_itl(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u32 __iomem *)AG_ISA_IO_W(addr);
#endif
default: return 0; /* avoid warnings, just in case */
}
}
static inline u8 __iomem *isa_mtb(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u8 __iomem *)addr;
#endif
#ifdef CONFIG_ATARI_ROM_ISA
case ISA_TYPE_ENEC: return (u8 __iomem *)ENEC_ISA_MEM_B(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
static inline u16 __iomem *isa_mtw(unsigned long addr)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: return (u16 __iomem *)addr;
#endif
#ifdef CONFIG_ATARI_ROM_ISA
case ISA_TYPE_ENEC: return (u16 __iomem *)ENEC_ISA_MEM_W(addr);
#endif
default: return NULL; /* avoid warnings, just in case */
}
}
#define isa_inb(port) in_8(isa_itb(port))
#define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port)))
#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
#define isa_outb(val,port) out_8(isa_itb(port),(val))
#define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
#define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
#define isa_readw(p) \
(ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
: in_le16(isa_mtw((unsigned long)(p))))
#define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
#define isa_writew(val,p) \
(ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
: out_le16(isa_mtw((unsigned long)(p)),(val)))
#ifdef CONFIG_ATARI_ROM_ISA
#define isa_rom_inb(port) rom_in_8(isa_itb(port))
#define isa_rom_inw(port) \
(ISA_SEX ? rom_in_be16(isa_itw(port)) \
: rom_in_le16(isa_itw(port)))
#define isa_rom_outb(val, port) rom_out_8(isa_itb(port), (val))
#define isa_rom_outw(val, port) \
(ISA_SEX ? rom_out_be16(isa_itw(port), (val)) \
: rom_out_le16(isa_itw(port), (val)))
#define isa_rom_readb(p) rom_in_8(isa_mtb((unsigned long)(p)))
#define isa_rom_readw(p) \
(ISA_SEX ? rom_in_be16(isa_mtw((unsigned long)(p))) \
: rom_in_le16(isa_mtw((unsigned long)(p))))
#define isa_rom_readw_swap(p) \
(ISA_SEX ? rom_in_le16(isa_mtw((unsigned long)(p))) \
: rom_in_be16(isa_mtw((unsigned long)(p))))
#define isa_rom_readw_raw(p) rom_in_be16(isa_mtw((unsigned long)(p)))
#define isa_rom_writeb(val, p) rom_out_8(isa_mtb((unsigned long)(p)), (val))
#define isa_rom_writew(val, p) \
(ISA_SEX ? rom_out_be16(isa_mtw((unsigned long)(p)), (val)) \
: rom_out_le16(isa_mtw((unsigned long)(p)), (val)))
#define isa_rom_writew_swap(val, p) \
(ISA_SEX ? rom_out_le16(isa_mtw((unsigned long)(p)), (val)) \
: rom_out_be16(isa_mtw((unsigned long)(p)), (val)))
#define isa_rom_writew_raw(val, p) rom_out_be16(isa_mtw((unsigned long)(p)), (val))
#endif /* CONFIG_ATARI_ROM_ISA */
static inline void isa_delay(void)
{
switch(ISA_TYPE)
{
#ifdef CONFIG_Q40
case ISA_TYPE_Q40: isa_outb(0,0x80); break;
#endif
#ifdef CONFIG_AMIGA_PCMCIA
case ISA_TYPE_AG: break;
#endif
#ifdef CONFIG_ATARI_ROM_ISA
case ISA_TYPE_ENEC: break;
#endif
default: break; /* avoid warnings */
}
}
#define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;})
#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
#define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;})
#define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();})
#define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;})
#define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();})
#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr))
#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr))
#define isa_insw(port, buf, nr) \
(ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
#define isa_outsw(port, buf, nr) \
(ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
#define isa_insl(port, buf, nr) \
(ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \
raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
#define isa_outsl(port, buf, nr) \
(ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
#ifdef CONFIG_ATARI_ROM_ISA
#define isa_rom_inb_p(p) ({ u8 _v = isa_rom_inb(p); isa_delay(); _v; })
#define isa_rom_inw_p(p) ({ u16 _v = isa_rom_inw(p); isa_delay(); _v; })
#define isa_rom_outb_p(v, p) ({ isa_rom_outb((v), (p)); isa_delay(); })
#define isa_rom_outw_p(v, p) ({ isa_rom_outw((v), (p)); isa_delay(); })
#define isa_rom_insb(port, buf, nr) raw_rom_insb(isa_itb(port), (u8 *)(buf), (nr))
#define isa_rom_insw(port, buf, nr) \
(ISA_SEX ? raw_rom_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
raw_rom_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
#define isa_rom_outsb(port, buf, nr) raw_rom_outsb(isa_itb(port), (u8 *)(buf), (nr))
#define isa_rom_outsw(port, buf, nr) \
(ISA_SEX ? raw_rom_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
raw_rom_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
#endif /* CONFIG_ATARI_ROM_ISA */
#endif /* CONFIG_ISA || CONFIG_ATARI_ROM_ISA */
#if defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA)
#define inb isa_inb
#define inb_p isa_inb_p
#define outb isa_outb
#define outb_p isa_outb_p
#define inw isa_inw
#define inw_p isa_inw_p
#define outw isa_outw
#define outw_p isa_outw_p
#define inl isa_inl
#define inl_p isa_inl_p
#define outl isa_outl
#define outl_p isa_outl_p
#define insb isa_insb
#define insw isa_insw
#define insl isa_insl
#define outsb isa_outsb
#define outsw isa_outsw
#define outsl isa_outsl
#define readb isa_readb
#define readw isa_readw
#define writeb isa_writeb
#define writew isa_writew
#endif /* CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
#ifdef CONFIG_ATARI_ROM_ISA
/*
* kernel with both ROM port ISA and IDE compiled in, those have
* conflicting defs for in/out. Simply consider port < 1024
* ROM port ISA and everything else regular ISA for IDE. read,write defined
* below.
*/
#define inb(port) ((port) < 1024 ? isa_rom_inb(port) : in_8(port))
#define inb_p(port) ((port) < 1024 ? isa_rom_inb_p(port) : in_8(port))
#define inw(port) ((port) < 1024 ? isa_rom_inw(port) : in_le16(port))
#define inw_p(port) ((port) < 1024 ? isa_rom_inw_p(port) : in_le16(port))
#define inl isa_inl
#define inl_p isa_inl_p
#define outb(val, port) ((port) < 1024 ? isa_rom_outb((val), (port)) : out_8((port), (val)))
#define outb_p(val, port) ((port) < 1024 ? isa_rom_outb_p((val), (port)) : out_8((port), (val)))
#define outw(val, port) ((port) < 1024 ? isa_rom_outw((val), (port)) : out_le16((port), (val)))
#define outw_p(val, port) ((port) < 1024 ? isa_rom_outw_p((val), (port)) : out_le16((port), (val)))
#define outl isa_outl
#define outl_p isa_outl_p
#define insb(port, buf, nr) ((port) < 1024 ? isa_rom_insb((port), (buf), (nr)) : isa_insb((port), (buf), (nr)))
#define insw(port, buf, nr) ((port) < 1024 ? isa_rom_insw((port), (buf), (nr)) : isa_insw((port), (buf), (nr)))
#define insl isa_insl
#define outsb(port, buf, nr) ((port) < 1024 ? isa_rom_outsb((port), (buf), (nr)) : isa_outsb((port), (buf), (nr)))
#define outsw(port, buf, nr) ((port) < 1024 ? isa_rom_outsw((port), (buf), (nr)) : isa_outsw((port), (buf), (nr)))
#define outsl isa_outsl
#define readb(addr) in_8(addr)
#define writeb(val, addr) out_8((addr), (val))
#define readw(addr) in_le16(addr)
#define writew(val, addr) out_le16((addr), (val))
#endif /* CONFIG_ATARI_ROM_ISA */
#if !defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA)
/*
* We need to define dummy functions for GENERIC_IOMAP support.
*/
#define inb(port) 0xff
#define inb_p(port) 0xff
#define outb(val,port) ((void)0)
#define outb_p(val,port) ((void)0)
#define inw(port) 0xffff
#define inw_p(port) 0xffff
#define outw(val,port) ((void)0)
#define outw_p(val,port) ((void)0)
#define inl(port) 0xffffffffUL
#define inl_p(port) 0xffffffffUL
#define outl(val,port) ((void)0)
#define outl_p(val,port) ((void)0)
#define insb(port,buf,nr) ((void)0)
#define outsb(port,buf,nr) ((void)0)
#define insw(port,buf,nr) ((void)0)
#define outsw(port,buf,nr) ((void)0)
#define insl(port,buf,nr) ((void)0)
#define outsl(port,buf,nr) ((void)0)
/*
* These should be valid on any ioremap()ed region
*/
#define readb(addr) in_8(addr)
#define writeb(val,addr) out_8((addr),(val))
#define readw(addr) in_le16(addr)
#define writew(val,addr) out_le16((addr),(val))
#endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
#define readl(addr) in_le32(addr)
#define writel(val,addr) out_le32((addr),(val))
#define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr))
#define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr))
#define readsl(port, buf, nr) raw_insl((port), (u32 *)(buf), (nr))
#define writesb(port, buf, nr) raw_outsb((port), (u8 *)(buf), (nr))
#define writesw(port, buf, nr) raw_outsw((port), (u16 *)(buf), (nr))
#define writesl(port, buf, nr) raw_outsl((port), (u32 *)(buf), (nr))
#define mmiowb()
static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void __iomem *ioremap_writethrough(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
__builtin_memset((void __force *) addr, val, count);
}
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
{
__builtin_memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
__builtin_memcpy((void __force *) dst, src, count);
}
#ifndef CONFIG_SUN3
#define IO_SPACE_LIMIT 0xffff
#else
#define IO_SPACE_LIMIT 0x0fffffff
#endif
#endif /* __KERNEL__ */
#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *) port;
}
static inline void ioport_unmap(void __iomem *p)
{
}
#endif /* _IO_H */

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#ifndef _M68KNOMMU_IO_H
#define _M68KNOMMU_IO_H
#ifdef __KERNEL__
#include <asm/virtconvert.h>
#include <asm-generic/iomap.h>
/*
* These are for ISA/PCI shared memory _only_ and should never be used
* on any other type of memory, including Zorro memory. They are meant to
* access the bus in the bus byte order which is little-endian!.
*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the m68k architecture, we just read/write the
* memory location directly.
*/
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesirable for some devices.
*/
/*
* swap functions are sometimes needed to interface little-endian hardware
*/
static inline unsigned short _swapw(volatile unsigned short v)
{
return ((v << 8) | (v >> 8));
}
static inline unsigned int _swapl(volatile unsigned long v)
{
return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
}
#define readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define readw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define readl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
static inline void io_outsb(unsigned int addr, const void *buf, int len)
{
volatile unsigned char *ap = (volatile unsigned char *) addr;
unsigned char *bp = (unsigned char *) buf;
while (len--)
*ap = *bp++;
}
static inline void io_outsw(unsigned int addr, const void *buf, int len)
{
volatile unsigned short *ap = (volatile unsigned short *) addr;
unsigned short *bp = (unsigned short *) buf;
while (len--)
*ap = _swapw(*bp++);
}
static inline void io_outsl(unsigned int addr, const void *buf, int len)
{
volatile unsigned int *ap = (volatile unsigned int *) addr;
unsigned int *bp = (unsigned int *) buf;
while (len--)
*ap = _swapl(*bp++);
}
static inline void io_insb(unsigned int addr, void *buf, int len)
{
volatile unsigned char *ap = (volatile unsigned char *) addr;
unsigned char *bp = (unsigned char *) buf;
while (len--)
*bp++ = *ap;
}
static inline void io_insw(unsigned int addr, void *buf, int len)
{
volatile unsigned short *ap = (volatile unsigned short *) addr;
unsigned short *bp = (unsigned short *) buf;
while (len--)
*bp++ = _swapw(*ap);
}
static inline void io_insl(unsigned int addr, void *buf, int len)
{
volatile unsigned int *ap = (volatile unsigned int *) addr;
unsigned int *bp = (unsigned int *) buf;
while (len--)
*bp++ = _swapl(*ap);
}
#define mmiowb()
/*
* make the short names macros so specific devices
* can override them as required
*/
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
#define inb(addr) readb(addr)
#define inw(addr) readw(addr)
#define inl(addr) readl(addr)
#define outb(x,addr) ((void) writeb(x,addr))
#define outw(x,addr) ((void) writew(x,addr))
#define outl(x,addr) ((void) writel(x,addr))
#define inb_p(addr) inb(addr)
#define inw_p(addr) inw(addr)
#define inl_p(addr) inl(addr)
#define outb_p(x,addr) outb(x,addr)
#define outw_p(x,addr) outw(x,addr)
#define outl_p(x,addr) outl(x,addr)
#define outsb(a,b,l) io_outsb(a,b,l)
#define outsw(a,b,l) io_outsw(a,b,l)
#define outsl(a,b,l) io_outsl(a,b,l)
#define insb(a,b,l) io_insb(a,b,l)
#define insw(a,b,l) io_insw(a,b,l)
#define insl(a,b,l) io_insl(a,b,l)
#define IO_SPACE_LIMIT 0xffffffff
/* Values for nocacheflag and cmode */
#define IOMAP_FULL_CACHING 0
#define IOMAP_NOCACHE_SER 1
#define IOMAP_NOCACHE_NONSER 2
#define IOMAP_WRITETHROUGH 3
static inline void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
{
return (void *) physaddr;
}
static inline void *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
#define iounmap(addr) do { } while(0)
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *) port;
}
static inline void ioport_unmap(void __iomem *p)
{
}
#endif /* __KERNEL__ */
#endif /* _M68KNOMMU_IO_H */

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#ifndef _M68K_IRQ_H_
#define _M68K_IRQ_H_
/*
* This should be the same as the max(NUM_X_SOURCES) for all the
* different m68k hosts compiled into the kernel.
* Currently the Atari has 72 and the Amiga 24, but if both are
* supported in the kernel it is better to make room for 72.
* With EtherNAT add-on card on Atari, the highest interrupt
* number is 140 so NR_IRQS needs to be 141.
*/
#if defined(CONFIG_COLDFIRE)
#define NR_IRQS 256
#elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
#define NR_IRQS 200
#elif defined(CONFIG_ATARI)
#define NR_IRQS 141
#elif defined(CONFIG_MAC)
#define NR_IRQS 72
#elif defined(CONFIG_Q40)
#define NR_IRQS 43
#elif defined(CONFIG_AMIGA) || !defined(CONFIG_MMU)
#define NR_IRQS 32
#elif defined(CONFIG_APOLLO)
#define NR_IRQS 24
#elif defined(CONFIG_HP300)
#define NR_IRQS 8
#else
#define NR_IRQS 0
#endif
#if defined(CONFIG_M68020) || defined(CONFIG_M68030) || \
defined(CONFIG_M68040) || defined(CONFIG_M68060)
/*
* Interrupt source definitions
* General interrupt sources are the level 1-7.
* Adding an interrupt service routine for one of these sources
* results in the addition of that routine to a chain of routines.
* Each one is called in succession. Each individual interrupt
* service routine should determine if the device associated with
* that routine requires service.
*/
#define IRQ_SPURIOUS 0
#define IRQ_AUTO_1 1 /* level 1 interrupt */
#define IRQ_AUTO_2 2 /* level 2 interrupt */
#define IRQ_AUTO_3 3 /* level 3 interrupt */
#define IRQ_AUTO_4 4 /* level 4 interrupt */
#define IRQ_AUTO_5 5 /* level 5 interrupt */
#define IRQ_AUTO_6 6 /* level 6 interrupt */
#define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */
#define IRQ_USER 8
struct irq_data;
struct irq_chip;
struct irq_desc;
extern unsigned int m68k_irq_startup(struct irq_data *data);
extern unsigned int m68k_irq_startup_irq(unsigned int irq);
extern void m68k_irq_shutdown(struct irq_data *data);
extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int,
struct pt_regs *));
extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt);
extern void m68k_setup_irq_controller(struct irq_chip *,
void (*handle)(unsigned int irq,
struct irq_desc *desc),
unsigned int irq, unsigned int cnt);
extern unsigned int irq_canonicalize(unsigned int irq);
#else
#define irq_canonicalize(irq) (irq)
#endif /* !(CONFIG_M68020 || CONFIG_M68030 || CONFIG_M68040 || CONFIG_M68060) */
asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
extern atomic_t irq_err_count;
#endif /* _M68K_IRQ_H_ */

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#ifndef _M68K_IRQFLAGS_H
#define _M68K_IRQFLAGS_H
#include <linux/types.h>
#ifdef CONFIG_MMU
#include <linux/preempt_mask.h>
#endif
#include <linux/preempt.h>
#include <asm/thread_info.h>
#include <asm/entry.h>
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile ("movew %%sr,%0" : "=d" (flags) : : "memory");
return flags;
}
static inline void arch_local_irq_disable(void)
{
#ifdef CONFIG_COLDFIRE
asm volatile (
"move %/sr,%%d0 \n\t"
"ori.l #0x0700,%%d0 \n\t"
"move %%d0,%/sr \n"
: /* no outputs */
:
: "cc", "%d0", "memory");
#else
asm volatile ("oriw #0x0700,%%sr" : : : "memory");
#endif
}
static inline void arch_local_irq_enable(void)
{
#if defined(CONFIG_COLDFIRE)
asm volatile (
"move %/sr,%%d0 \n\t"
"andi.l #0xf8ff,%%d0 \n\t"
"move %%d0,%/sr \n"
: /* no outputs */
:
: "cc", "%d0", "memory");
#else
# if defined(CONFIG_MMU)
if (MACH_IS_Q40 || !hardirq_count())
# endif
asm volatile (
"andiw %0,%%sr"
:
: "i" (ALLOWINT)
: "memory");
#endif
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile ("movew %0,%%sr" : : "d" (flags) : "memory");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
if (MACH_IS_ATARI) {
/* Ignore HSYNC = ipl 2 on Atari */
return (flags & ~(ALLOWINT | 0x200)) != 0;
}
return (flags & ~ALLOWINT) != 0;
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
#endif /* _M68K_IRQFLAGS_H */

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#ifndef _ASM_M68K_KEXEC_H
#define _ASM_M68K_KEXEC_H
#ifdef CONFIG_KEXEC
/* Maximum physical address we can use pages from */
#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
/* Maximum address we can reach in physical address mode */
#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
/* Maximum address we can use for the control code buffer */
#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
#define KEXEC_CONTROL_PAGE_SIZE 4096
#define KEXEC_ARCH KEXEC_ARCH_68K
#ifndef __ASSEMBLY__
static inline void crash_setup_regs(struct pt_regs *newregs,
struct pt_regs *oldregs)
{
/* Dummy implementation for now */
}
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_KEXEC */
#endif /* _ASM_M68K_KEXEC_H */

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#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
#define __ALIGN .align 4
#define __ALIGN_STR ".align 4"
#endif

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arch/m68k/include/asm/m5206sim.h Normal file
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/****************************************************************************/
/*
* m5206sim.h -- ColdFire 5206 System Integration Module support.
*
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*/
/****************************************************************************/
#ifndef m5206sim_h
#define m5206sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5206)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
/*
* Define the 5206 SIM register set addresses.
*/
#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
#ifdef CONFIG_M5206e
#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
#endif
#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
#ifdef CONFIG_M5206e
#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
#else
#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
#endif
#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
#if defined(CONFIG_NETtel)
#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
#else
#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
#endif
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
/*
* Generic GPIO
*/
#define MCFGPIO_PIN_MAX 8
#define MCFGPIO_IRQ_VECBASE -1
#define MCFGPIO_IRQ_MAX -1
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
#ifdef CONFIG_M5206e
#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
/* Clear to select T0 input */
#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
/* Clear to select T0 output */
#endif
/*
* Some symbol defines for the Interrupt Control Register
*/
#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
#ifdef CONFIG_M5206e
#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
#endif
/****************************************************************************/
#endif /* m5206sim_h */

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/****************************************************************************/
/*
* m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
*
* (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
*/
/****************************************************************************/
#ifndef m520xsim_h
#define m520xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m520x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 520x SIM register set addresses.
*/
#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
/*
* The common interrupt controller code just wants to know the absolute
* address to the SIMR and CIMR registers (not offsets into IPSBAR).
* The 520x family only has a single INTC unit.
*/
#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
#define MCFINTC1_SIMR (0)
#define MCFINTC1_CIMR (0)
#define MCFINTC1_ICR0 (0)
#define MCFINTC2_SIMR (0)
#define MCFINTC2_CIMR (0)
#define MCFINTC2_ICR0 (0)
#define MCFINT_VECBASE 64
#define MCFINT_UART0 26 /* Interrupt number for UART0 */
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
/*
* SDRAM configuration registers.
*/
#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
/*
* EPORT and GPIO registers.
*/
#define MCFEPORT_EPPAR 0xFC088000
#define MCFEPORT_EPDDR 0xFC088002
#define MCFEPORT_EPIER 0xFC088003
#define MCFEPORT_EPDR 0xFC088004
#define MCFEPORT_EPPDR 0xFC088005
#define MCFEPORT_EPFR 0xFC088006
#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
#define MCFGPIO_PODR_BE 0xFC0A4001
#define MCFGPIO_PODR_CS 0xFC0A4002
#define MCFGPIO_PODR_FECI2C 0xFC0A4003
#define MCFGPIO_PODR_QSPI 0xFC0A4004
#define MCFGPIO_PODR_TIMER 0xFC0A4005
#define MCFGPIO_PODR_UART 0xFC0A4006
#define MCFGPIO_PODR_FECH 0xFC0A4007
#define MCFGPIO_PODR_FECL 0xFC0A4008
#define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
#define MCFGPIO_PDDR_BE 0xFC0A400D
#define MCFGPIO_PDDR_CS 0xFC0A400E
#define MCFGPIO_PDDR_FECI2C 0xFC0A400F
#define MCFGPIO_PDDR_QSPI 0xFC0A4010
#define MCFGPIO_PDDR_TIMER 0xFC0A4011
#define MCFGPIO_PDDR_UART 0xFC0A4012
#define MCFGPIO_PDDR_FECH 0xFC0A4013
#define MCFGPIO_PDDR_FECL 0xFC0A4014
#define MCFGPIO_PPDSDR_CS 0xFC0A401A
#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B
#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C
#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D
#define MCFGPIO_PPDSDR_UART 0xFC0A401E
#define MCFGPIO_PPDSDR_FECH 0xFC0A401F
#define MCFGPIO_PPDSDR_FECL 0xFC0A4020
#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
#define MCFGPIO_PCLRR_BE 0xFC0A4025
#define MCFGPIO_PCLRR_CS 0xFC0A4026
#define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
#define MCFGPIO_PCLRR_QSPI 0xFC0A4028
#define MCFGPIO_PCLRR_TIMER 0xFC0A4029
#define MCFGPIO_PCLRR_UART 0xFC0A402A
#define MCFGPIO_PCLRR_FECH 0xFC0A402B
#define MCFGPIO_PCLRR_FECL 0xFC0A402C
/*
* Generic GPIO support
*/
#define MCFGPIO_PODR MCFGPIO_PODR_CS
#define MCFGPIO_PDDR MCFGPIO_PDDR_CS
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS
#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS
#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS
#define MCFGPIO_PIN_MAX 80
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
#define MCF_GPIO_PAR_UART 0xFC0A4036
#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
#define MCF_GPIO_PAR_QSPI 0xFC0A4034
#define MCF_GPIO_PAR_FEC 0xFC0A4038
#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
/*
* PIT timer module.
*/
#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
/*
* UART module.
*/
#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
/*
* FEC module.
*/
#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
#define MCFFEC_SIZE0 0x800 /* Register set size */
/*
* QSPI module.
*/
#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
#define MCFQSPI_SIZE 0x40 /* Register set size */
#define MCFQSPI_CS0 46
#define MCFQSPI_CS1 47
#define MCFQSPI_CS2 27
/*
* Reset Control Unit.
*/
#define MCF_RCR 0xFC0A0000
#define MCF_RSR 0xFC0A0001
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/*
* Power Management.
*/
#define MCFPM_WCR 0xfc040013
#define MCFPM_PPMSR0 0xfc04002c
#define MCFPM_PPMCR0 0xfc04002d
#define MCFPM_PPMHR0 0xfc040030
#define MCFPM_PPMLR0 0xfc040034
#define MCFPM_LPCR 0xfc0a0007
/****************************************************************************/
#endif /* m520xsim_h */

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/****************************************************************************/
/*
* m523xsim.h -- ColdFire 523x System Integration Module support.
*
* (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef m523xsim_h
#define m523xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m523x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 523x SIM register set addresses.
*/
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
/*
* Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR (MCF_IPSBAR + 0x110000)
#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/*
* UART module.
*/
#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
#define MCFFEC_SIZE0 0x800
/*
* QSPI module.
*/
#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
#define MCFQSPI_SIZE 0x40
#define MCFQSPI_CS0 91
#define MCFQSPI_CS1 92
#define MCFQSPI_CS2 103
#define MCFQSPI_CS3 99
/*
* GPIO module.
*/
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
/*
* EPort
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
/*
* Generic GPIO support
*/
#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
#define MCFGPIO_PIN_MAX 107
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* Pin Assignment
*/
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
#define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E)
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
/****************************************************************************/
#endif /* m523xsim_h */

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/****************************************************************************/
/*
* m525xsim.h -- ColdFire 525x System Integration Module support.
*
* (C) Copyright 2012, Steven king <sfking@fdwdc.com>
* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
*/
/****************************************************************************/
#ifndef m525xsim_h
#define m525xsim_h
/****************************************************************************/
/*
* This header supports ColdFire 5249, 5251 and 5253. There are a few
* little differences between them, but most of the peripheral support
* can be used by all of them.
*/
#define CPU_NAME "COLDFIRE(m525x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* The 525x has a second MBAR region, define its address.
*/
#define MCF_MBAR2 0x80000000
/*
* Define the 525x SIM register set addresses.
*/
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Secondary Interrupt Controller (in MBAR2)
*/
#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
((((i) - MCFINTC2_VECBASE) / 8) * 4))
#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
/*
* UART module.
*/
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
/*
* QSPI module.
*/
#define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */
#define MCFQSPI_SIZE 0x40 /* Register set size */
#ifdef CONFIG_M5249
#define MCFQSPI_CS0 29
#define MCFQSPI_CS1 24
#define MCFQSPI_CS2 21
#define MCFQSPI_CS3 22
#else
#define MCFQSPI_CS0 15
#define MCFQSPI_CS1 16
#define MCFQSPI_CS2 24
#define MCFQSPI_CS3 28
#endif
/*
* I2C module.
*/
#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
#define MCFI2C_SIZE0 0x20 /* Register set size */
#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
#define MCFI2C_SIZE1 0x20 /* Register set size */
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
#define MCF_IRQ_I2C0 29
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
/*
* Define the base interrupt for the second interrupt controller.
* We set it to 128, out of the way of the base interrupts, and plenty
* of room for its 64 interrupts.
*/
#define MCFINTC2_VECBASE 128
#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39)
#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
/*
* General purpose IO registers (in MBAR2).
*/
#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 64
#ifdef CONFIG_M5249
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
#else
#define MCFGPIO_IRQ_MAX 7
#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
#endif
/****************************************************************************/
#ifdef __ASSEMBLER__
#ifdef CONFIG_M5249C3
/*
* The M5249C3 board needs a little help getting all its SIM devices
* initialized at kernel start time. dBUG doesn't set much up, so
* we need to do it manually.
*/
.macro m5249c3_setup
/*
* Set MBAR1 and MBAR2, just incase they are not set.
*/
movel #0x10000001,%a0
movec %a0,%MBAR /* map MBAR region */
subql #1,%a0 /* get MBAR address in a0 */
movel #0x80000001,%a1
movec %a1,#3086 /* map MBAR2 region */
subql #1,%a1 /* get MBAR2 address in a1 */
/*
* Move secondary interrupts to their base (128).
*/
moveb #MCFINTC2_VECBASE,%d0
moveb %d0,0x16b(%a1) /* interrupt base register */
/*
* Work around broken CSMR0/DRAM vector problem.
*/
movel #0x001F0021,%d0 /* disable C/I bit */
movel %d0,0x84(%a0) /* set CSMR0 */
/*
* Disable the PLL firstly. (Who knows what state it is
* in here!).
*/
movel 0x180(%a1),%d0 /* get current PLL value */
andl #0xfffffffe,%d0 /* PLL bypass first */
movel %d0,0x180(%a1) /* set PLL register */
nop
#if CONFIG_CLOCK_FREQ == 140000000
/*
* Set initial clock frequency. This assumes M5249C3 board
* is fitted with 11.2896MHz crystal. It will program the
* PLL for 140MHz. Lets go fast :-)
*/
movel #0x125a40f0,%d0 /* set for 140MHz */
movel %d0,0x180(%a1) /* set PLL register */
orl #0x1,%d0
movel %d0,0x180(%a1) /* set PLL register */
#endif
/*
* Setup CS1 for ethernet controller.
* (Setup as per M5249C3 doco).
*/
movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
movel %d0,0x8c(%a0)
movel #0x001f0021,%d0 /* CS1 size of 1Mb */
movel %d0,0x90(%a0)
movew #0x0080,%d0 /* CS1 = 16bit port, AA */
movew %d0,0x96(%a0)
/*
* Setup CS2 for IDE interface.
*/
movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
movel %d0,0x98(%a0)
movel #0x001f0001,%d0 /* CS2 size of 1MB */
movel %d0,0x9c(%a0)
movew #0x0080,%d0 /* CS2 = 16bit, TA */
movew %d0,0xa2(%a0)
movel #0x00107000,%d0 /* IDEconfig1 */
movel %d0,0x18c(%a1)
movel #0x000c0400,%d0 /* IDEconfig2 */
movel %d0,0x190(%a1)
movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
orl %d0,0xc(%a1) /* function GPIO19 */
orl %d0,0x8(%a1) /* enable GPIO19 as output */
orl %d0,0x4(%a1) /* de-assert IDE reset */
.endm
#define PLATFORM_SETUP m5249c3_setup
#endif /* CONFIG_M5249C3 */
#endif /* __ASSEMBLER__ */
/****************************************************************************/
#endif /* m525xsim_h */

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/****************************************************************************/
/*
* m5272sim.h -- ColdFire 5272 System Integration Module support.
*
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
*/
/****************************************************************************/
#ifndef m5272sim_h
#define m5272sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5272)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
/*
* Define the 5272 SIM register set addresses.
*/
#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
#define MCFFEC_SIZE0 0x1d0
/*
* Define system peripheral IRQ usage.
*/
#define MCFINT_VECBASE 64 /* Base of interrupts */
#define MCF_IRQ_SPURIOUS 64 /* User Spurious */
#define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
#define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
#define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
#define MCF_IRQ_EINT4 68 /* External Interrupt 4 */
#define MCF_IRQ_TIMER1 69 /* Timer 1 */
#define MCF_IRQ_TIMER2 70 /* Timer 2 */
#define MCF_IRQ_TIMER3 71 /* Timer 3 */
#define MCF_IRQ_TIMER4 72 /* Timer 4 */
#define MCF_IRQ_UART0 73 /* UART 0 */
#define MCF_IRQ_UART1 74 /* UART 1 */
#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
#define MCF_IRQ_USB1 78 /* USB Endpoint 1 */
#define MCF_IRQ_USB2 79 /* USB Endpoint 2 */
#define MCF_IRQ_USB3 80 /* USB Endpoint 3 */
#define MCF_IRQ_USB4 81 /* USB Endpoint 4 */
#define MCF_IRQ_USB5 82 /* USB Endpoint 5 */
#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
#define MCF_IRQ_DMA 85 /* DMA Controller */
#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
#define MCF_IRQ_SWTO 92 /* Software Watchdog */
#define MCFINT_VECMAX 95 /* Maxmum interrupt */
#define MCF_IRQ_TIMER MCF_IRQ_TIMER1
#define MCF_IRQ_PROFILER MCF_IRQ_TIMER2
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 48
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/****************************************************************************/
#endif /* m5272sim_h */

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/****************************************************************************/
/*
* m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
*
* (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
*/
/****************************************************************************/
#ifndef m527xsim_h
#define m527xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m527x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m52xxacr.h>
/*
* Define the 5270/5271 SIM register set addresses.
*/
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
#define MCFINT2_VECBASE 128 /* Vector base number 2 */
#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
/*
* SDRAM configuration registers.
*/
#ifdef CONFIG_M5271
#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
#endif
#ifdef CONFIG_M5275
#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
#endif
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
/*
* UART module.
*/
#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
#define MCFFEC_SIZE0 0x800
#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
#define MCFFEC_SIZE1 0x800
/*
* QSPI module.
*/
#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
#define MCFQSPI_SIZE 0x40
#ifdef CONFIG_M5271
#define MCFQSPI_CS0 91
#define MCFQSPI_CS1 92
#define MCFQSPI_CS2 99
#define MCFQSPI_CS3 103
#endif
#ifdef CONFIG_M5275
#define MCFQSPI_CS0 59
#define MCFQSPI_CS1 60
#define MCFQSPI_CS2 61
#define MCFQSPI_CS3 62
#endif
/*
* GPIO module.
*/
#ifdef CONFIG_M5271
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
/*
* Generic GPIO support
*/
#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
#define MCFGPIO_PIN_MAX 100
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* Port Pin Assignment registers.
*/
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x0ff0
#define UART2_ENABLE_MASK 0x3000
#endif /* CONFIG_M5271 */
#ifdef CONFIG_M5275
#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005)
#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008)
#define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A)
#define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B)
#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C)
#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D)
#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E)
#define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F)
#define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010)
#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011)
#define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012)
#define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013)
#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014)
#define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015)
#define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016)
#define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017)
#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018)
#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020)
#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021)
#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024)
#define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026)
#define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027)
#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028)
#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029)
#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A)
#define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B)
#define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C)
#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D)
#define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E)
#define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F)
#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030)
#define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031)
#define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032)
#define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033)
#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034)
#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C)
#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D)
#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040)
#define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042)
#define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043)
#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044)
#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045)
#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046)
#define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047)
#define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048)
#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049)
#define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B)
#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C)
#define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D)
#define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E)
#define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F)
#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050)
#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058)
#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059)
#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C)
#define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E)
#define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F)
#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060)
#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061)
#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062)
#define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063)
#define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064)
#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065)
#define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066)
#define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067)
#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068)
#define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069)
#define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A)
#define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B)
#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C)
/*
* Generic GPIO support
*/
#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
#define MCFGPIO_PIN_MAX 148
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* Port Pin Assignment registers.
*/
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076)
#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A)
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C)
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080)
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x00f0
#define UART2_ENABLE_MASK 0x3f00
#endif /* CONFIG_M5275 */
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
/*
* EPort
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
/*
* Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR (MCF_IPSBAR + 0x110000)
#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/****************************************************************************/
#endif /* m527xsim_h */

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arch/m68k/include/asm/m528xsim.h Normal file
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/****************************************************************************/
/*
* m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
*
* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
*/
/****************************************************************************/
#ifndef m528xsim_h
#define m528xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m528x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
/*
* Define the 5280/5282 SIM register set addresses.
*/
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
/*
* UART module.
*/
#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
#define MCFFEC_SIZE0 0x800
/*
* QSPI module.
*/
#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
#define MCFQSPI_SIZE 0x40
#define MCFQSPI_CS0 147
#define MCFQSPI_CS1 148
#define MCFQSPI_CS2 149
#define MCFQSPI_CS3 150
/*
* GPIO registers
*/
#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000)
#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001)
#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002)
#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003)
#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004)
#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005)
#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006)
#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007)
#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008)
#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009)
#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A)
#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B)
#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C)
#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D)
#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E)
#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F)
#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010)
#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011)
#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014)
#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015)
#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016)
#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017)
#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018)
#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019)
#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A)
#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B)
#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C)
#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D)
#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E)
#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F)
#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020)
#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021)
#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022)
#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023)
#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024)
#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025)
#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028)
#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029)
#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A)
#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B)
#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C)
#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D)
#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E)
#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F)
#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030)
#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031)
#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032)
#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033)
#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034)
#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035)
#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036)
#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037)
#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038)
#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039)
#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C)
#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D)
#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E)
#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F)
#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040)
#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041)
#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042)
#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043)
#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044)
#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045)
#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046)
#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047)
#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048)
#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049)
#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A)
#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B)
#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C)
#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D)
#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
/*
* Edge Port registers
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
/*
* Queued ADC registers
*/
#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
/*
* General Purpose Timers registers
*/
#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
/*
*
* definitions for generic gpio support
*
*/
#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */
#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */
#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */
#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
#define MCFGPIO_PIN_MAX 180
/*
* Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR (MCF_IPSBAR + 0x110000)
#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/****************************************************************************/
#endif /* m528xsim_h */

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/****************************************************************************/
/*
* m52xxacr.h -- ColdFire version 2 core cache support
*
* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef m52xxacr_h
#define m52xxacr_h
/****************************************************************************/
/*
* All varients of the ColdFire using version 2 cores have a similar
* cache setup. Although not absolutely identical the cache register
* definitions are compatible for all of them. Mostly they support a
* configurable cache memory that can be instruction only, data only,
* or split instruction and data. The exception is the very old version 2
* core based parts, like the 5206(e), 5249 and 5272, which are instruction
* cache only. Cache size varies from 2k up to 16k.
*/
/*
* Define the Cache Control register flags.
*/
#define CACR_CENB 0x80000000 /* Enable cache */
#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
#define CACR_CINV 0x01000000 /* Invalidate cache */
#define CACR_DISI 0x00800000 /* Disable instruction cache */
#define CACR_DISD 0x00400000 /* Disable data cache */
#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
#define CACR_INVD 0x00100000 /* Invalidate data cache */
#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
#define CACR_DCM 0x00000200 /* Default cache mode */
#define CACR_DBWE 0x00000100 /* Buffered write enable */
#define CACR_DWP 0x00000020 /* Write protection */
#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
/*
* Define the Access Control register flags.
*/
#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
#define ACR_ENABLE 0x00008000 /* Enable this ACR */
#define ACR_USER 0x00000000 /* Allow only user accesses */
#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
#define ACR_ANY 0x00004000 /* Allow any access type */
#define ACR_CENB 0x00000000 /* Caching of region enabled */
#define ACR_CDIS 0x00000040 /* Caching of region disabled */
#define ACR_BWE 0x00000020 /* Write buffer enabled */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
/*
* Set the cache controller settings we will use. On the cores that support
* a split cache configuration we allow all the combinations at Kconfig
* time. For those cores that only have an instruction cache we just set
* that as on.
*/
#if defined(CONFIG_CACHE_I)
#define CACHE_TYPE (CACR_DISD + CACR_EUSP)
#define CACHE_INVTYPEI 0
#elif defined(CONFIG_CACHE_D)
#define CACHE_TYPE (CACR_DISI + CACR_EUSP)
#define CACHE_INVTYPED 0
#elif defined(CONFIG_CACHE_BOTH)
#define CACHE_TYPE CACR_EUSP
#define CACHE_INVTYPEI CACR_INVI
#define CACHE_INVTYPED CACR_INVD
#else
/* This is the instruction cache only devices (no split cache, no eusp) */
#define CACHE_TYPE 0
#define CACHE_INVTYPEI 0
#endif
#define CACHE_INIT (CACR_CINV + CACHE_TYPE)
#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM)
#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
#if defined(CACHE_INVTYPEI)
#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
#endif
#if defined(CACHE_INVTYPED)
#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
#endif
#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
(0x000f0000) + \
(ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
#define ACR1_MODE 0
/****************************************************************************/
#endif /* m52xxsim_h */

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/****************************************************************************/
/*
* m5307sim.h -- ColdFire 5307 System Integration Module support.
*
* (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
* (C) Copyright 1999, Lineo (www.lineo.com)
*
* Modified by David W. Miller for the MCF5307 Eval Board.
*/
/****************************************************************************/
#ifndef m5307sim_h
#define m5307sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5307)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m53xxacr.h>
/*
* Define the 5307 SIM register set addresses.
*/
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#ifdef CONFIG_OLDMASK
#define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
#define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
#define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
#define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
#else
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
#endif /* CONFIG_OLDMASK */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
/*
* UART module.
*/
#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */
#else
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
#endif
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 16
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/* Definition offset address for CS2-7 -- old mask 5307 */
#define MCF5307_CS2 (0x400000)
#define MCF5307_CS3 (0x600000)
#define MCF5307_CS4 (0x800000)
#define MCF5307_CS5 (0xA00000)
#define MCF5307_CS6 (0xC00000)
#define MCF5307_CS7 (0xE00000)
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
/* Clear to select par I/O */
#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
/* Clear to select par I/O */
/*
* Defines for the IRQPAR Register
*/
#define IRQ5_LEVEL4 0x80
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
/****************************************************************************/
#endif /* m5307sim_h */

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/****************************************************************************/
/*
* m53xxacr.h -- ColdFire version 3 core cache support
*
* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef m53xxacr_h
#define m53xxacr_h
/****************************************************************************/
/*
* All varients of the ColdFire using version 3 cores have a similar
* cache setup. They have a unified instruction and data cache, with
* configurable write-through or copy-back operation.
*/
/*
* Define the Cache Control register flags.
*/
#define CACR_EC 0x80000000 /* Enable cache */
#define CACR_ESB 0x20000000 /* Enable store buffer */
#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
#define CACR_HLCK 0x08000000 /* Half cache lock mode */
#define CACR_CINVA 0x01000000 /* Invalidate cache */
#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
#define CACR_WPROTECT 0x00000020 /* Write protect*/
#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
/*
* Define the Access Control register flags.
*/
#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
#define ACR_ENABLE 0x00008000 /* Enable this ACR */
#define ACR_USER 0x00000000 /* Allow only user accesses */
#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
#define ACR_ANY 0x00004000 /* Allow any access type */
#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
/*
* Define the cache type and arrangement (needed for pushes).
*/
#if defined(CONFIG_M5307)
#define CACHE_SIZE 0x2000 /* 8k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#elif defined(CONFIG_M53xx)
#define CACHE_SIZE 0x4000 /* 16k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#endif
#define CACHE_LINE_SIZE 16 /* 16 byte line size */
#define CACHE_WAYS 4 /* 4 ways - set associative */
/*
* Set the cache controller settings we will use. This default in the
* CACR is cache inhibited, we use the ACR register to set cacheing
* enabled on the regions we want (eg RAM).
*/
#if defined(CONFIG_CACHE_COPYBACK)
#define CACHE_TYPE ACR_CM_CB
#define CACHE_PUSH
#else
#define CACHE_TYPE ACR_CM_WT
#endif
#ifdef CONFIG_COLDFIRE_SW_A7
#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
#else
#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
#endif
/*
* Unified cache means we will never need to flush for coherency of
* instruction fetch. We will need to flush to maintain memory/DMA
* coherency though in all cases. And for copyback caches we will need
* to push cached data as well.
*/
#define CACHE_INIT CACR_CINVA
#define CACHE_INVALIDATE CACR_CINVA
#define CACHE_INVALIDATED CACR_CINVA
#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
(0x000f0000) + \
(ACR_ENABLE + ACR_ANY + CACHE_TYPE))
#define ACR1_MODE 0
/****************************************************************************/
#endif /* m53xxsim_h */

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/****************************************************************************/
/*
* m5407sim.h -- ColdFire 5407 System Integration Module support.
*
* (C) Copyright 2000, Lineo (www.lineo.com)
* (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
*
* Modified by David W. Miller for the MCF5307 Eval Board.
*/
/****************************************************************************/
#ifndef m5407sim_h
#define m5407sim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m5407)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m54xxacr.h>
/*
* Define the 5407 SIM register set addresses.
*/
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Timer module.
*/
#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
#define MCFSIM_PADDR (MCF_MBAR + 0x244)
#define MCFSIM_PADAT (MCF_MBAR + 0x248)
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 16
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
/* Clear to select par I/O */
#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
/* Clear to select par I/O */
/*
* Defines for the IRQPAR Register
*/
#define IRQ5_LEVEL4 0x80
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
/****************************************************************************/
#endif /* m5407sim_h */

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/*
* m5441xsim.h -- Coldfire 5441x register definitions
*
* (C) Copyright 2012, Steven King <sfking@fdwdc.com>
*/
#ifndef m5441xsim_h
#define m5441xsim_h
#define CPU_NAME "COLDFIRE(m5441x)"
#define CPU_INSTR_PER_JIFFY 2
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m54xxacr.h>
/*
* Reset Controller Module.
*/
#define MCF_RCR 0xec090000
#define MCF_RSR 0xec090001
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/*
* Interrupt Controller Modules.
*/
/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
#define MCFINT_VECBASE 64
#define MCFINT0_VECBASE MCFINT_VECBASE
#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
/* interrupt controller 0 */
#define MCFINTC0_SIMR 0xfc04801c
#define MCFINTC0_CIMR 0xfc04801d
#define MCFINTC0_ICR0 0xfc048040
/* interrupt controller 1 */
#define MCFINTC1_SIMR 0xfc04c01c
#define MCFINTC1_CIMR 0xfc04c01d
#define MCFINTC1_ICR0 0xfc04c040
/* interrupt controller 2 */
#define MCFINTC2_SIMR 0xfc05001c
#define MCFINTC2_CIMR 0xfc05001d
#define MCFINTC2_ICR0 0xfc050040
/* on interrupt controller 0 */
#define MCFINT0_EPORT0 1
#define MCFINT0_UART0 26
#define MCFINT0_UART1 27
#define MCFINT0_UART2 28
#define MCFINT0_UART3 29
#define MCFINT0_I2C0 30
#define MCFINT0_DSPI0 31
#define MCFINT0_TIMER0 32
#define MCFINT0_TIMER1 33
#define MCFINT0_TIMER2 34
#define MCFINT0_TIMER3 35
#define MCFINT0_FECRX0 36
#define MCFINT0_FECTX0 40
#define MCFINT0_FECENTC0 42
#define MCFINT0_FECRX1 49
#define MCFINT0_FECTX1 53
#define MCFINT0_FECENTC1 55
/* on interrupt controller 1 */
#define MCFINT1_UART4 48
#define MCFINT1_UART5 49
#define MCFINT1_UART6 50
#define MCFINT1_UART7 51
#define MCFINT1_UART8 52
#define MCFINT1_UART9 53
#define MCFINT1_DSPI1 54
#define MCFINT1_DSPI2 55
#define MCFINT1_DSPI3 56
#define MCFINT1_I2C1 57
#define MCFINT1_I2C2 58
#define MCFINT1_I2C3 59
#define MCFINT1_I2C4 60
#define MCFINT1_I2C5 61
/* on interrupt controller 2 */
#define MCFINT2_PIT0 13
#define MCFINT2_PIT1 14
#define MCFINT2_PIT2 15
#define MCFINT2_PIT3 16
#define MCFINT2_RTC 26
/*
* PIT timer module.
*/
#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
/*
* Power Management
*/
#define MCFPM_WCR 0xfc040013
#define MCFPM_PPMSR0 0xfc04002c
#define MCFPM_PPMCR0 0xfc04002d
#define MCFPM_PPMSR1 0xfc04002e
#define MCFPM_PPMCR1 0xfc04002f
#define MCFPM_PPMHR0 0xfc040030
#define MCFPM_PPMLR0 0xfc040034
#define MCFPM_PPMHR1 0xfc040038
#define MCFPM_PPMLR1 0xfc04003c
#define MCFPM_LPCR 0xec090007
/*
* UART module.
*/
#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
/*
* FEC modules.
*/
#define MCFFEC_BASE0 0xfc0d4000
#define MCFFEC_SIZE0 0x800
#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
#define MCFFEC_BASE1 0xfc0d8000
#define MCFFEC_SIZE1 0x800
#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
/*
* I2C modules.
*/
#define MCFI2C_BASE0 0xfc058000
#define MCFI2C_SIZE0 0x20
#define MCFI2C_BASE1 0xfc038000
#define MCFI2C_SIZE1 0x20
#define MCFI2C_BASE2 0xec010000
#define MCFI2C_SIZE2 0x20
#define MCFI2C_BASE3 0xec014000
#define MCFI2C_SIZE3 0x20
#define MCFI2C_BASE4 0xec018000
#define MCFI2C_SIZE4 0x20
#define MCFI2C_BASE5 0xec01c000
#define MCFI2C_SIZE5 0x20
#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
/*
* EPORT Module.
*/
#define MCFEPORT_EPPAR 0xfc090000
#define MCFEPORT_EPIER 0xfc090003
#define MCFEPORT_EPFR 0xfc090006
/*
* RTC Module.
*/
#define MCFRTC_BASE 0xfc0a8000
#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
/*
* GPIO Module.
*/
#define MCFGPIO_PODR_A 0xec094000
#define MCFGPIO_PODR_B 0xec094001
#define MCFGPIO_PODR_C 0xec094002
#define MCFGPIO_PODR_D 0xec094003
#define MCFGPIO_PODR_E 0xec094004
#define MCFGPIO_PODR_F 0xec094005
#define MCFGPIO_PODR_G 0xec094006
#define MCFGPIO_PODR_H 0xec094007
#define MCFGPIO_PODR_I 0xec094008
#define MCFGPIO_PODR_J 0xec094009
#define MCFGPIO_PODR_K 0xec09400a
#define MCFGPIO_PDDR_A 0xec09400c
#define MCFGPIO_PDDR_B 0xec09400d
#define MCFGPIO_PDDR_C 0xec09400e
#define MCFGPIO_PDDR_D 0xec09400f
#define MCFGPIO_PDDR_E 0xec094010
#define MCFGPIO_PDDR_F 0xec094011
#define MCFGPIO_PDDR_G 0xec094012
#define MCFGPIO_PDDR_H 0xec094013
#define MCFGPIO_PDDR_I 0xec094014
#define MCFGPIO_PDDR_J 0xec094015
#define MCFGPIO_PDDR_K 0xec094016
#define MCFGPIO_PPDSDR_A 0xec094018
#define MCFGPIO_PPDSDR_B 0xec094019
#define MCFGPIO_PPDSDR_C 0xec09401a
#define MCFGPIO_PPDSDR_D 0xec09401b
#define MCFGPIO_PPDSDR_E 0xec09401c
#define MCFGPIO_PPDSDR_F 0xec09401d
#define MCFGPIO_PPDSDR_G 0xec09401e
#define MCFGPIO_PPDSDR_H 0xec09401f
#define MCFGPIO_PPDSDR_I 0xec094020
#define MCFGPIO_PPDSDR_J 0xec094021
#define MCFGPIO_PPDSDR_K 0xec094022
#define MCFGPIO_PCLRR_A 0xec094024
#define MCFGPIO_PCLRR_B 0xec094025
#define MCFGPIO_PCLRR_C 0xec094026
#define MCFGPIO_PCLRR_D 0xec094027
#define MCFGPIO_PCLRR_E 0xec094028
#define MCFGPIO_PCLRR_F 0xec094029
#define MCFGPIO_PCLRR_G 0xec09402a
#define MCFGPIO_PCLRR_H 0xec09402b
#define MCFGPIO_PCLRR_I 0xec09402c
#define MCFGPIO_PCLRR_J 0xec09402d
#define MCFGPIO_PCLRR_K 0xec09402e
#define MCFGPIO_PAR_FBCTL 0xec094048
#define MCFGPIO_PAR_BE 0xec094049
#define MCFGPIO_PAR_CS 0xec09404a
#define MCFGPIO_PAR_CANI2C 0xec09404b
#define MCFGPIO_PAR_IRQ0H 0xec09404c
#define MCFGPIO_PAR_IRQ0L 0xec09404d
#define MCFGPIO_PAR_DSPIOWH 0xec09404e
#define MCFGPIO_PAR_DSPIOWL 0xec09404f
#define MCFGPIO_PAR_TIMER 0xec094050
#define MCFGPIO_PAR_UART2 0xec094051
#define MCFGPIO_PAR_UART1 0xec094052
#define MCFGPIO_PAR_UART0 0xec094053
#define MCFGPIO_PAR_SDHCH 0xec094054
#define MCFGPIO_PAR_SDHCL 0xec094055
#define MCFGPIO_PAR_SIMP0H 0xec094056
#define MCFGPIO_PAR_SIMP0L 0xec094057
#define MCFGPIO_PAR_SSI0H 0xec094058
#define MCFGPIO_PAR_SSI0L 0xec094059
#define MCFGPIO_PAR_DEBUGH1 0xec09405a
#define MCFGPIO_PAR_DEBUGH0 0xec09405b
#define MCFGPIO_PAR_DEBUGl 0xec09405c
#define MCFGPIO_PAR_FEC 0xec09405e
/* generalization for generic gpio support */
#define MCFGPIO_PODR MCFGPIO_PODR_A
#define MCFGPIO_PDDR MCFGPIO_PDDR_A
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
#define MCFGPIO_IRQ_MIN 17
#define MCFGPIO_IRQ_MAX 24
#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
#define MCFGPIO_PIN_MAX 87
#endif /* m5441xsim_h */

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/*
* Bit definitions for the MCF54xx ACR and CACR registers.
*/
#ifndef m54xxacr_h
#define m54xxacr_h
/*
* Define the Cache register flags.
*/
#define CACR_DEC 0x80000000 /* Enable data cache */
#define CACR_DWP 0x40000000 /* Data write protection */
#define CACR_DESB 0x20000000 /* Enable data store buffer */
#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
#define CACR_DDCM_P 0x04000000 /* No cache, precise */
#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
#define CACR_BEC 0x00080000 /* Enable branch cache */
#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
#define CACR_IEC 0x00008000 /* Enable instruction cache */
#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
#define ACR_BASE_POS 24 /* Address Base */
#define ACR_MASK_POS 16 /* Address Mask */
#define ACR_ENABLE 0x00008000 /* Enable address */
#define ACR_USER 0x00000000 /* User mode access only */
#define ACR_SUPER 0x00002000 /* Supervisor mode only */
#define ACR_ANY 0x00004000 /* Match any access mode */
#define ACR_CM_WT 0x00000000 /* Write through mode */
#define ACR_CM_CP 0x00000020 /* Copyback mode */
#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
#define ACR_CM 0x00000060 /* Cache mode mask */
#define ACR_SP 0x00000008 /* Supervisor protect */
#define ACR_WPROTECT 0x00000004 /* Write protect */
#define ACR_BA(x) ((x) & 0xff000000)
#define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
#if defined(CONFIG_M5407)
#define ICACHE_SIZE 0x4000 /* instruction - 16k */
#define DCACHE_SIZE 0x2000 /* data - 8k */
#elif defined(CONFIG_M54xx)
#define ICACHE_SIZE 0x8000 /* instruction - 32k */
#define DCACHE_SIZE 0x8000 /* data - 32k */
#elif defined(CONFIG_M5441x)
#define ICACHE_SIZE 0x2000 /* instruction - 8k */
#define DCACHE_SIZE 0x2000 /* data - 8k */
#endif
#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
#define CACHE_WAYS 4 /* 4 ways */
#define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
#define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
#define ICACHE_MAX_ADDR ICACHE_SET_MASK
#define DCACHE_MAX_ADDR DCACHE_SET_MASK
/*
* Version 4 cores have a true harvard style separate instruction
* and data cache. Enable data and instruction caches, also enable write
* buffers and branch accelerator.
*/
/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
/* use '+' instead of '|' for assembler's sake */
/* Enable data cache */
/* Enable data store buffer */
/* outside ACRs : No cache, precise */
/* Enable instruction+branch caches */
#if defined(CONFIG_M5407)
#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
#else
#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
#endif
#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
#if defined(CONFIG_MMU)
/*
* If running with the MMU enabled then we need to map the internal
* register region as non-cacheable. And then we map all our RAM as
* cacheable and supervisor access only.
*/
#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
#if defined(CONFIG_CACHE_COPYBACK)
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
#else
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
#endif
#define ACR2_MODE 0
#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP)
#else
/*
* For the non-MMU enabled case we map all of RAM as cacheable.
*/
#if defined(CONFIG_CACHE_COPYBACK)
#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
#else
#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
#endif
#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
#define ACR1_MODE 0
#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
#define ACR3_MODE 0
#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
/* Copyback cache mode must push dirty cache lines first */
#define CACHE_PUSH
#endif
#endif /* CONFIG_MMU */
#endif /* m54xxacr_h */

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/*
* File: m54xxgpt.h
* Purpose: Register and bit definitions for the MCF54XX
*
* Notes:
*
*/
#ifndef m54xxgpt_h
#define m54xxgpt_h
/*********************************************************************
*
* General Purpose Timers (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
#define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
#define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
#define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
#define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
#define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
#define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
#define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
#define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
#define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
#define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828)
#define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C)
#define MCF_GPT_GMS3 (MCF_MBAR + 0x000830)
#define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834)
#define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838)
#define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C)
#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010))
#define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010))
#define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010))
#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
#define MCF_GPT_GMS_IEN (0x00000100)
#define MCF_GPT_GMS_OD (0x00000200)
#define MCF_GPT_GMS_SC (0x00000400)
#define MCF_GPT_GMS_CE (0x00001000)
#define MCF_GPT_GMS_WDEN (0x00008000)
#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
#define MCF_GPT_GMS_ICT_ANY (0x00000000)
#define MCF_GPT_GMS_ICT_RISE (0x00010000)
#define MCF_GPT_GMS_ICT_FALL (0x00020000)
#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
#define MCF_GPT_GMS_GPIO_MASK (0x00000030)
#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
#define MCF_GPT_GMS_TMS_PWM (0x00000003)
#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
#define MCF_GPT_GMS_TMS_MASK (0x00000007)
/* Bit definitions and macros for MCF_GPT_GCIR */
#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GPWM */
#define MCF_GPT_GPWM_LOAD (0x00000001)
#define MCF_GPT_GPWM_PWMOP (0x00000100)
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GSR */
#define MCF_GPT_GSR_CAPT (0x00000001)
#define MCF_GPT_GSR_COMP (0x00000002)
#define MCF_GPT_GSR_PWMP (0x00000004)
#define MCF_GPT_GSR_TEXP (0x00000008)
#define MCF_GPT_GSR_PIN (0x00000100)
#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
/********************************************************************/
#endif /* m54xxgpt_h */

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/****************************************************************************/
/*
* m54xxpci.h -- ColdFire 547x and 548x PCI bus support
*
* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/****************************************************************************/
#ifndef M54XXPCI_H
#define M54XXPCI_H
/****************************************************************************/
/*
* The core set of PCI support registers are mapped into the MBAR region.
*/
#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
#define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */
/*
* Definitions for the Global status and control register.
*/
#define PCIGSCR_PE 0x20000000 /* Parity error detected */
#define PCIGSCR_SE 0x10000000 /* System error detected */
#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
#define PCIGSCR_SEE 0x00001000 /* System error intr enable */
#define PCIGSCR_RESET 0x00000001 /* Reset bit */
/*
* Bit definitions for the PCICAR configuration address register.
*/
#define PCICAR_E 0x80000000 /* Enable config space */
#define PCICAR_BUSN 16 /* Move bus bits */
#define PCICAR_DEVFNN 8 /* Move devfn bits */
#define PCICAR_DWORDN 0 /* Move dword bits */
/*
* The initiator windows hold the memory and IO mapping information.
* This macro creates the register values from the desired addresses.
*/
#define WXBTAR(hostaddr, pciaddr, size) \
(((hostaddr) & 0xff000000) | \
((((size) - 1) & 0xff000000) >> 8) | \
(((pciaddr) & 0xff000000) >> 16))
#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
/*
* Bit definitions for the PCIBATR registers.
*/
#define PCITBATR0_E 0x00000001 /* Enable window 0 */
#define PCITBATR1_E 0x00000001 /* Enable window 1 */
/*
* PCI arbiter support definitions and macros.
*/
#define PACR_INTMPRI 0x00000001
#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
#define PACR_INTMINTE 0x00010000
#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
#define PACR_PKMD 0x40000000
#define PACR_DS 0x80000000
#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
/****************************************************************************/
#endif /* M54XXPCI_H */

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/*
* m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
*/
#ifndef m54xxsim_h
#define m54xxsim_h
#define CPU_NAME "COLDFIRE(m54xx)"
#define CPU_INSTR_PER_JIFFY 2
#define MCF_BUSCLK (MCF_CLK / 2)
#include <asm/m54xxacr.h>
#define MCFINT_VECBASE 64
/*
* Interrupt Controller Registers
*/
#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
/*
* UART module.
*/
#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
/*
* Slice Timer support.
*/
#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
/*
* Generic GPIO support
*/
#define MCFGPIO_PODR (MCF_MBAR + 0xA00)
#define MCFGPIO_PDDR (MCF_MBAR + 0xA10)
#define MCFGPIO_PPDR (MCF_MBAR + 0xA20)
#define MCFGPIO_SETR (MCF_MBAR + 0xA20)
#define MCFGPIO_CLRR (MCF_MBAR + 0xA30)
#define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* EDGE Port support.
*/
#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
/*
* Pin Assignment register definitions
*/
#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
#define MCF_PAR_SDA (0x0008)
#define MCF_PAR_SCL (0x0004)
#define MCF_PAR_PSC_TXD (0x04)
#define MCF_PAR_PSC_RXD (0x08)
#define MCF_PAR_PSC_CTS_GPIO (0x00)
#define MCF_PAR_PSC_CTS_BCLK (0x80)
#define MCF_PAR_PSC_CTS_CTS (0xC0)
#define MCF_PAR_PSC_RTS_GPIO (0x00)
#define MCF_PAR_PSC_RTS_FSYNC (0x20)
#define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40)
#endif /* m54xxsim_h */

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#include <asm/m68360_regs.h>
#include <asm/m68360_pram.h>
#include <asm/m68360_quicc.h>
#include <asm/m68360_enet.h>
#ifdef CONFIG_M68360
#define CPM_INTERRUPT 4
/* see MC68360 User's Manual, p. 7-377 */
#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */
#endif /* CONFIG_M68360 */

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/***********************************
* $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
***********************************
*
***************************************
* Definitions for the ETHERNET controllers
***************************************
*/
#ifndef __ETHER_H
#define __ETHER_H
#include <asm/quicc_simple.h>
/*
* transmit BD's
*/
#define T_R 0x8000 /* ready bit */
#define E_T_PAD 0x4000 /* short frame padding */
#define T_W 0x2000 /* wrap bit */
#define T_I 0x1000 /* interrupt on completion */
#define T_L 0x0800 /* last in frame */
#define T_TC 0x0400 /* transmit CRC (when last) */
#define T_DEF 0x0200 /* defer indication */
#define T_HB 0x0100 /* heartbeat */
#define T_LC 0x0080 /* error: late collision */
#define T_RL 0x0040 /* error: retransmission limit */
#define T_RC 0x003c /* retry count */
#define T_UN 0x0002 /* error: underrun */
#define T_CSL 0x0001 /* carier sense lost */
#define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL)
/*
* receive BD's
*/
#define R_E 0x8000 /* buffer empty */
#define R_W 0x2000 /* wrap bit */
#define R_I 0x1000 /* interrupt on reception */
#define R_L 0x0800 /* last BD in frame */
#define R_F 0x0400 /* first BD in frame */
#define R_M 0x0100 /* received because of promisc. mode */
#define R_LG 0x0020 /* frame too long */
#define R_NO 0x0010 /* non-octet aligned */
#define R_SH 0x0008 /* short frame */
#define R_CR 0x0004 /* receive CRC error */
#define R_OV 0x0002 /* receive overrun */
#define R_CL 0x0001 /* collision */
#define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL)
/*
* ethernet interrupts
*/
#define ETHERNET_GRA 0x0080 /* graceful stop complete */
#define ETHERNET_TXE 0x0010 /* transmit error */
#define ETHERNET_RXF 0x0008 /* receive frame */
#define ETHERNET_BSY 0x0004 /* busy condition */
#define ETHERNET_TXB 0x0002 /* transmit buffer */
#define ETHERNET_RXB 0x0001 /* receive buffer */
/*
* ethernet protocol specific mode register (PSMR)
*/
#define ETHER_HBC 0x8000 /* heartbeat checking */
#define ETHER_FC 0x4000 /* force collision */
#define ETHER_RSH 0x2000 /* receive short frames */
#define ETHER_IAM 0x1000 /* individual address mode */
#define ETHER_CRC_32 (0x2<<10) /* Enable CRC */
#define ETHER_PRO 0x0200 /* promiscuous */
#define ETHER_BRO 0x0100 /* broadcast address */
#define ETHER_SBT 0x0080 /* stop backoff timer */
#define ETHER_LPB 0x0040 /* Loop Back Mode */
#define ETHER_SIP 0x0020 /* sample input pins */
#define ETHER_LCW 0x0010 /* late collision window */
#define ETHER_NIB_13 (0x0<<1) /* # of ignored bits 13 */
#define ETHER_NIB_14 (0x1<<1) /* # of ignored bits 14 */
#define ETHER_NIB_15 (0x2<<1) /* # of ignored bits 15 */
#define ETHER_NIB_16 (0x3<<1) /* # of ignored bits 16 */
#define ETHER_NIB_21 (0x4<<1) /* # of ignored bits 21 */
#define ETHER_NIB_22 (0x5<<1) /* # of ignored bits 22 */
#define ETHER_NIB_23 (0x6<<1) /* # of ignored bits 23 */
#define ETHER_NIB_24 (0x7<<1) /* # of ignored bits 24 */
/*
* ethernet specific parameters
*/
#define CRC_WORD 4 /* Length in bytes of CRC */
#define C_PRES 0xffffffff /* preform 32 bit CRC */
#define C_MASK 0xdebb20e3 /* comply with 32 bit CRC */
#define CRCEC 0x00000000
#define ALEC 0x00000000
#define DISFC 0x00000000
#define PADS 0x00000000
#define RET_LIM 0x000f /* retry 15 times to send a frame before interrupt */
#define ETH_MFLR 0x05ee /* 1518 max frame size */
#define MINFLR 0x0040 /* Minimum frame size 64 */
#define MAXD1 0x05ee /* Max dma count 1518 */
#define MAXD2 0x05ee
#define GADDR1 0x00000000 /* Clear group address */
#define GADDR2 0x00000000
#define GADDR3 0x00000000
#define GADDR4 0x00000000
#define P_PER 0x00000000 /*not used */
#define IADDR1 0x00000000 /* Individual hash table not used */
#define IADDR2 0x00000000
#define IADDR3 0x00000000
#define IADDR4 0x00000000
#define TADDR_H 0x00000000 /* clear this regs */
#define TADDR_M 0x00000000
#define TADDR_L 0x00000000
/* SCC Parameter Ram */
#define RFCR 0x18 /* normal operation */
#define TFCR 0x18 /* normal operation */
#define E_MRBLR 1518 /* Max ethernet frame length */
/*
* ethernet specific structure
*/
typedef union {
unsigned char b[6];
struct {
unsigned short high;
unsigned short middl;
unsigned short low;
} w;
} ETHER_ADDR;
typedef struct {
int max_frame_length;
int promisc_mode;
int reject_broadcast;
ETHER_ADDR phys_adr;
} ETHER_SPECIFIC;
typedef struct {
ETHER_ADDR dst_addr;
ETHER_ADDR src_addr;
unsigned short type_or_len;
unsigned char data[1];
} ETHER_FRAME;
#define MAX_DATALEN 1500
typedef struct {
ETHER_ADDR dst_addr;
ETHER_ADDR src_addr;
unsigned short type_or_len;
unsigned char data[MAX_DATALEN];
unsigned char fcs[CRC_WORD];
} ETHER_MAX_FRAME;
/*
* Internal ethernet function prototypes
*/
void ether_interrupt(int scc_num);
/* mleslie: debug */
/* static void ethernet_rx_internal(int scc_num); */
/* static void ethernet_tx_internal(int scc_num); */
/*
* User callable routines prototypes (ethernet specific)
*/
void ethernet_init(int scc_number,
alloc_routine *alloc_buffer,
free_routine *free_buffer,
store_rx_buffer_routine *store_rx_buffer,
handle_tx_error_routine *handle_tx_error,
handle_rx_error_routine *handle_rx_error,
handle_lost_error_routine *handle_lost_error,
ETHER_SPECIFIC *ether_spec);
int ethernet_tx(int scc_number, void *buf, int length);
#endif

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/***********************************
* $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
***********************************
*
***************************************
* Definitions of the parameter area RAM.
* Note that different structures are overlaid
* at the same offsets for the different modes
* of operation.
***************************************
*/
#ifndef __PRAM_H
#define __PRAM_H
/* Time slot assignment table */
#define VALID_SLOT 0x8000
#define WRAP_SLOT 0x4000
/*****************************************************************
Global Multichannel parameter RAM
*****************************************************************/
struct global_multi_pram {
/*
* Global Multichannel parameter RAM
*/
unsigned long mcbase; /* Multichannel Base pointer */
unsigned short qmcstate; /* Multichannel Controller state */
unsigned short mrblr; /* Maximum Receive Buffer Length */
unsigned short tx_s_ptr; /* TSTATx Pointer */
unsigned short rxptr; /* Current Time slot entry in TSATRx */
unsigned short grfthr; /* Global Receive frame threshold */
unsigned short grfcnt; /* Global Receive Frame Count */
unsigned long intbase; /* Multichannel Base address */
unsigned long iintptr; /* Pointer to interrupt queue */
unsigned short rx_s_ptr; /* TSTARx Pointer */
unsigned short txptr; /* Current Time slot entry in TSATTx */
unsigned long c_mask32; /* CRC Constant (debb20e3) */
unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */
unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */
unsigned short c_mask16; /* CRC Constant (f0b8) */
};
/*****************************************************************
Quicc32 HDLC parameter RAM
*****************************************************************/
struct quicc32_pram {
unsigned short tbase; /* Tx Buffer Descriptors Base Address */
unsigned short chamr; /* Channel Mode Register */
unsigned long tstate; /* Tx Internal State */
unsigned long txintr; /* Tx Internal Data Pointer */
unsigned short tbptr; /* Tx Buffer Descriptor Pointer */
unsigned short txcntr; /* Tx Internal Byte Count */
unsigned long tupack; /* (Tx Temp) */
unsigned long zistate; /* Zero Insertion machine state */
unsigned long tcrc; /* Temp Transmit CRC */
unsigned short intmask; /* Channel's interrupt mask flags */
unsigned short bdflags;
unsigned short rbase; /* Rx Buffer Descriptors Base Address */
unsigned short mflr; /* Max Frame Length Register */
unsigned long rstate; /* Rx Internal State */
unsigned long rxintr; /* Rx Internal Data Pointer */
unsigned short rbptr; /* Rx Buffer Descriptor Pointer */
unsigned short rxbyc; /* Rx Internal Byte Count */
unsigned long rpack; /* (Rx Temp) */
unsigned long zdstate; /* Zero Deletion machine state */
unsigned long rcrc; /* Temp Transmit CRC */
unsigned short maxc; /* Max_length counter */
unsigned short tmp_mb; /* Temp */
};
/*****************************************************************
HDLC parameter RAM
*****************************************************************/
struct hdlc_pram {
/*
* SCC parameter RAM
*/
unsigned short rbase; /* RX BD base address */
unsigned short tbase; /* TX BD base address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned long rcrc; /* temp receive CRC */
unsigned long tcrc; /* temp transmit CRC */
/*
* HDLC specific parameter RAM
*/
unsigned char RESERVED1[4]; /* Reserved area */
unsigned long c_mask; /* CRC constant */
unsigned long c_pres; /* CRC preset */
unsigned short disfc; /* discarded frame counter */
unsigned short crcec; /* CRC error counter */
unsigned short abtsc; /* abort sequence counter */
unsigned short nmarc; /* nonmatching address rx cnt */
unsigned short retrc; /* frame retransmission cnt */
unsigned short mflr; /* maximum frame length reg */
unsigned short max_cnt; /* maximum length counter */
unsigned short rfthr; /* received frames threshold */
unsigned short rfcnt; /* received frames count */
unsigned short hmask; /* user defined frm addr mask */
unsigned short haddr1; /* user defined frm address 1 */
unsigned short haddr2; /* user defined frm address 2 */
unsigned short haddr3; /* user defined frm address 3 */
unsigned short haddr4; /* user defined frm address 4 */
unsigned short tmp; /* temp */
unsigned short tmp_mb; /* temp */
};
/*****************************************************************
UART parameter RAM
*****************************************************************/
/*
* bits in uart control characters table
*/
#define CC_INVALID 0x8000 /* control character is valid */
#define CC_REJ 0x4000 /* don't store char in buffer */
#define CC_CHAR 0x00ff /* control character */
/* UART */
struct uart_pram {
/*
* SCC parameter RAM
*/
unsigned short rbase; /* RX BD base address */
unsigned short tbase; /* TX BD base address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rx_temp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned long rcrc; /* temp receive CRC */
unsigned long tcrc; /* temp transmit CRC */
/*
* UART specific parameter RAM
*/
unsigned char RESERVED1[8]; /* Reserved area */
unsigned short max_idl; /* maximum idle characters */
unsigned short idlc; /* rx idle counter (internal) */
unsigned short brkcr; /* break count register */
unsigned short parec; /* Rx parity error counter */
unsigned short frmer; /* Rx framing error counter */
unsigned short nosec; /* Rx noise counter */
unsigned short brkec; /* Rx break character counter */
unsigned short brkln; /* Reaceive break length */
unsigned short uaddr1; /* address character 1 */
unsigned short uaddr2; /* address character 2 */
unsigned short rtemp; /* temp storage */
unsigned short toseq; /* Tx out of sequence char */
unsigned short cc[8]; /* Rx control characters */
unsigned short rccm; /* Rx control char mask */
unsigned short rccr; /* Rx control char register */
unsigned short rlbc; /* Receive last break char */
};
/*****************************************************************
BISYNC parameter RAM
*****************************************************************/
struct bisync_pram {
/*
* SCC parameter RAM
*/
unsigned short rbase; /* RX BD base address */
unsigned short tbase; /* TX BD base address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned long rcrc; /* temp receive CRC */
unsigned long tcrc; /* temp transmit CRC */
/*
* BISYNC specific parameter RAM
*/
unsigned char RESERVED1[4]; /* Reserved area */
unsigned long crcc; /* CRC Constant Temp Value */
unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
unsigned short parec; /* Receive Parity Error Counter */
unsigned short bsync; /* BISYNC SYNC Character */
unsigned short bdle; /* BISYNC DLE Character */
unsigned short cc[8]; /* Rx control characters */
unsigned short rccm; /* Receive Control Character Mask */
};
/*****************************************************************
IOM2 parameter RAM
(overlaid on tx bd[5] of SCC channel[2])
*****************************************************************/
struct iom2_pram {
unsigned short ci_data; /* ci data */
unsigned short monitor_data; /* monitor data */
unsigned short tstate; /* transmitter state */
unsigned short rstate; /* receiver state */
};
/*****************************************************************
SPI/SMC parameter RAM
(overlaid on tx bd[6,7] of SCC channel[2])
*****************************************************************/
#define SPI_R 0x8000 /* Ready bit in BD */
struct spi_pram {
unsigned short rbase; /* Rx BD Base Address */
unsigned short tbase; /* Tx BD Base Address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
};
struct smc_uart_pram {
unsigned short rbase; /* Rx BD Base Address */
unsigned short tbase; /* Tx BD Base Address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned short max_idl; /* Maximum IDLE Characters */
unsigned short idlc; /* Temporary IDLE Counter */
unsigned short brkln; /* Last Rx Break Length */
unsigned short brkec; /* Rx Break Condition Counter */
unsigned short brkcr; /* Break Count Register (Tx) */
unsigned short r_mask; /* Temporary bit mask */
};
struct smc_trnsp_pram {
unsigned short rbase; /* rx BD Base Address */
unsigned short tbase; /* Tx BD Base Address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned short reserved[5]; /* Reserved */
};
struct idma_pram {
unsigned short ibase; /* IDMA BD Base Address */
unsigned short ibptr; /* IDMA buffer descriptor pointer */
unsigned long istate; /* IDMA internal state */
unsigned long itemp; /* IDMA temp */
};
struct ethernet_pram {
/*
* SCC parameter RAM
*/
unsigned short rbase; /* RX BD base address */
unsigned short tbase; /* TX BD base address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned long rcrc; /* temp receive CRC */
unsigned long tcrc; /* temp transmit CRC */
/*
* ETHERNET specific parameter RAM
*/
unsigned long c_pres; /* preset CRC */
unsigned long c_mask; /* constant mask for CRC */
unsigned long crcec; /* CRC error counter */
unsigned long alec; /* alighnment error counter */
unsigned long disfc; /* discard frame counter */
unsigned short pads; /* short frame PAD characters */
unsigned short ret_lim; /* retry limit threshold */
unsigned short ret_cnt; /* retry limit counter */
unsigned short mflr; /* maximum frame length reg */
unsigned short minflr; /* minimum frame length reg */
unsigned short maxd1; /* maximum DMA1 length reg */
unsigned short maxd2; /* maximum DMA2 length reg */
unsigned short maxd; /* rx max DMA */
unsigned short dma_cnt; /* rx dma counter */
unsigned short max_b; /* max bd byte count */
unsigned short gaddr1; /* group address filter 1 */
unsigned short gaddr2; /* group address filter 2 */
unsigned short gaddr3; /* group address filter 3 */
unsigned short gaddr4; /* group address filter 4 */
unsigned long tbuf0_data0; /* save area 0 - current frm */
unsigned long tbuf0_data1; /* save area 1 - current frm */
unsigned long tbuf0_rba0;
unsigned long tbuf0_crc;
unsigned short tbuf0_bcnt;
union {
unsigned char b[6];
struct {
unsigned short high;
unsigned short middl;
unsigned short low;
} w;
} paddr;
unsigned short p_per; /* persistence */
unsigned short rfbd_ptr; /* rx first bd pointer */
unsigned short tfbd_ptr; /* tx first bd pointer */
unsigned short tlbd_ptr; /* tx last bd pointer */
unsigned long tbuf1_data0; /* save area 0 - next frame */
unsigned long tbuf1_data1; /* save area 1 - next frame */
unsigned long tbuf1_rba0;
unsigned long tbuf1_crc;
unsigned short tbuf1_bcnt;
unsigned short tx_len; /* tx frame length counter */
unsigned short iaddr1; /* individual address filter 1*/
unsigned short iaddr2; /* individual address filter 2*/
unsigned short iaddr3; /* individual address filter 3*/
unsigned short iaddr4; /* individual address filter 4*/
unsigned short boff_cnt; /* back-off counter */
unsigned short taddr_h; /* temp address (MSB) */
unsigned short taddr_m; /* temp address */
unsigned short taddr_l; /* temp address (LSB) */
};
struct transparent_pram {
/*
* SCC parameter RAM
*/
unsigned short rbase; /* RX BD base address */
unsigned short tbase; /* TX BD base address */
unsigned char rfcr; /* Rx function code */
unsigned char tfcr; /* Tx function code */
unsigned short mrblr; /* Rx buffer length */
unsigned long rstate; /* Rx internal state */
unsigned long rptr; /* Rx internal data pointer */
unsigned short rbptr; /* rb BD Pointer */
unsigned short rcount; /* Rx internal byte count */
unsigned long rtemp; /* Rx temp */
unsigned long tstate; /* Tx internal state */
unsigned long tptr; /* Tx internal data pointer */
unsigned short tbptr; /* Tx BD pointer */
unsigned short tcount; /* Tx byte count */
unsigned long ttemp; /* Tx temp */
unsigned long rcrc; /* temp receive CRC */
unsigned long tcrc; /* temp transmit CRC */
/*
* TRANSPARENT specific parameter RAM
*/
unsigned long crc_p; /* CRC Preset */
unsigned long crc_c; /* CRC constant */
};
struct timer_pram {
/*
* RISC timers parameter RAM
*/
unsigned short tm_base; /* RISC timer table base adr */
unsigned short tm_ptr; /* RISC timer table pointer */
unsigned short r_tmr; /* RISC timer mode register */
unsigned short r_tmv; /* RISC timer valid register */
unsigned long tm_cmd; /* RISC timer cmd register */
unsigned long tm_cnt; /* RISC timer internal cnt */
};
#endif

362
arch/m68k/include/asm/m68360_quicc.h Normal file
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/***********************************
* $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
***********************************
*
***************************************
* Definitions of QUICC memory structures
***************************************
*/
#ifndef __M68360_QUICC_H
#define __M68360_QUICC_H
/*
* include registers and
* parameter ram definitions files
*/
#include <asm/m68360_regs.h>
#include <asm/m68360_pram.h>
/* Buffer Descriptors */
typedef struct quicc_bd {
volatile unsigned short status;
volatile unsigned short length;
volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */
} QUICC_BD;
#ifdef MOTOROLA_ORIGINAL
struct user_data {
/* BASE + 0x000: user data memory */
volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
volatile unsigned char udata_bd[0x200]; /*user data Ucode */
volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */
volatile unsigned char RESERVED1[0x500]; /* Reserved area */
};
#else
struct user_data {
/* BASE + 0x000: user data memory */
volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/
volatile unsigned char udata_bd1[0x200]; /* user, bds */
volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */
volatile unsigned char udata_bd2[0x100]; /* user, bds */
volatile unsigned char RESERVED1[0x400]; /* Reserved area */
};
#endif
/*
* internal ram
*/
typedef struct quicc {
union {
struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */
struct user_data u;
}ch_or_u; /* multipul or user space */
/* BASE + 0xc00: PARAMETER RAM */
union {
struct scc_pram {
union {
struct hdlc_pram h;
struct uart_pram u;
struct bisync_pram b;
struct transparent_pram t;
unsigned char RESERVED66[0x70];
} pscc; /* scc parameter area (protocol dependent) */
union {
struct {
unsigned char RESERVED70[0x10];
struct spi_pram spi;
unsigned char RESERVED72[0x8];
struct timer_pram timer;
} timer_spi;
struct {
struct idma_pram idma;
unsigned char RESERVED67[0x4];
union {
struct smc_uart_pram u;
struct smc_trnsp_pram t;
} psmc;
} idma_smc;
} pothers;
} scc;
struct ethernet_pram enet_scc;
struct global_multi_pram m;
unsigned char pr[0x100];
} pram[4];
/* reserved */
/* BASE + 0x1000: INTERNAL REGISTERS */
/* SIM */
volatile unsigned long sim_mcr; /* module configuration reg */
volatile unsigned short sim_simtr; /* module test register */
volatile unsigned char RESERVED2[0x2]; /* Reserved area */
volatile unsigned char sim_avr; /* auto vector reg */
volatile unsigned char sim_rsr; /* reset status reg */
volatile unsigned char RESERVED3[0x2]; /* Reserved area */
volatile unsigned char sim_clkocr; /* CLCO control register */
volatile unsigned char RESERVED62[0x3]; /* Reserved area */
volatile unsigned short sim_pllcr; /* PLL control register */
volatile unsigned char RESERVED63[0x2]; /* Reserved area */
volatile unsigned short sim_cdvcr; /* Clock devider control register */
volatile unsigned short sim_pepar; /* Port E pin assignment register */
volatile unsigned char RESERVED64[0xa]; /* Reserved area */
volatile unsigned char sim_sypcr; /* system protection control*/
volatile unsigned char sim_swiv; /* software interrupt vector*/
volatile unsigned char RESERVED6[0x2]; /* Reserved area */
volatile unsigned short sim_picr; /* periodic interrupt control reg */
volatile unsigned char RESERVED7[0x2]; /* Reserved area */
volatile unsigned short sim_pitr; /* periodic interrupt timing reg */
volatile unsigned char RESERVED8[0x3]; /* Reserved area */
volatile unsigned char sim_swsr; /* software service */
volatile unsigned long sim_bkar; /* breakpoint address register*/
volatile unsigned long sim_bkcr; /* breakpoint control register*/
volatile unsigned char RESERVED10[0x8]; /* Reserved area */
/* MEMC */
volatile unsigned long memc_gmr; /* Global memory register */
volatile unsigned short memc_mstat; /* MEMC status register */
volatile unsigned char RESERVED11[0xa]; /* Reserved area */
volatile unsigned long memc_br0; /* base register 0 */
volatile unsigned long memc_or0; /* option register 0 */
volatile unsigned char RESERVED12[0x8]; /* Reserved area */
volatile unsigned long memc_br1; /* base register 1 */
volatile unsigned long memc_or1; /* option register 1 */
volatile unsigned char RESERVED13[0x8]; /* Reserved area */
volatile unsigned long memc_br2; /* base register 2 */
volatile unsigned long memc_or2; /* option register 2 */
volatile unsigned char RESERVED14[0x8]; /* Reserved area */
volatile unsigned long memc_br3; /* base register 3 */
volatile unsigned long memc_or3; /* option register 3 */
volatile unsigned char RESERVED15[0x8]; /* Reserved area */
volatile unsigned long memc_br4; /* base register 3 */
volatile unsigned long memc_or4; /* option register 3 */
volatile unsigned char RESERVED16[0x8]; /* Reserved area */
volatile unsigned long memc_br5; /* base register 3 */
volatile unsigned long memc_or5; /* option register 3 */
volatile unsigned char RESERVED17[0x8]; /* Reserved area */
volatile unsigned long memc_br6; /* base register 3 */
volatile unsigned long memc_or6; /* option register 3 */
volatile unsigned char RESERVED18[0x8]; /* Reserved area */
volatile unsigned long memc_br7; /* base register 3 */
volatile unsigned long memc_or7; /* option register 3 */
volatile unsigned char RESERVED9[0x28]; /* Reserved area */
/* TEST */
volatile unsigned short test_tstmra; /* master shift a */
volatile unsigned short test_tstmrb; /* master shift b */
volatile unsigned short test_tstsc; /* shift count */
volatile unsigned short test_tstrc; /* repetition counter */
volatile unsigned short test_creg; /* control */
volatile unsigned short test_dreg; /* destributed register */
volatile unsigned char RESERVED58[0x404]; /* Reserved area */
/* IDMA1 */
volatile unsigned short idma_iccr; /* channel configuration reg*/
volatile unsigned char RESERVED19[0x2]; /* Reserved area */
volatile unsigned short idma1_cmr; /* dma mode reg */
volatile unsigned char RESERVED68[0x2]; /* Reserved area */
volatile unsigned long idma1_sapr; /* dma source addr ptr */
volatile unsigned long idma1_dapr; /* dma destination addr ptr */
volatile unsigned long idma1_bcr; /* dma byte count reg */
volatile unsigned char idma1_fcr; /* function code reg */
volatile unsigned char RESERVED20; /* Reserved area */
volatile unsigned char idma1_cmar; /* channel mask reg */
volatile unsigned char RESERVED21; /* Reserved area */
volatile unsigned char idma1_csr; /* channel status reg */
volatile unsigned char RESERVED22[0x3]; /* Reserved area */
/* SDMA */
volatile unsigned char sdma_sdsr; /* status reg */
volatile unsigned char RESERVED23; /* Reserved area */
volatile unsigned short sdma_sdcr; /* configuration reg */
volatile unsigned long sdma_sdar; /* address reg */
/* IDMA2 */
volatile unsigned char RESERVED69[0x2]; /* Reserved area */
volatile unsigned short idma2_cmr; /* dma mode reg */
volatile unsigned long idma2_sapr; /* dma source addr ptr */
volatile unsigned long idma2_dapr; /* dma destination addr ptr */
volatile unsigned long idma2_bcr; /* dma byte count reg */
volatile unsigned char idma2_fcr; /* function code reg */
volatile unsigned char RESERVED24; /* Reserved area */
volatile unsigned char idma2_cmar; /* channel mask reg */
volatile unsigned char RESERVED25; /* Reserved area */
volatile unsigned char idma2_csr; /* channel status reg */
volatile unsigned char RESERVED26[0x7]; /* Reserved area */
/* Interrupt Controller */
volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
volatile unsigned long intr_cipr; /* CP interrupt pending reg */
volatile unsigned long intr_cimr; /* CP interrupt mask reg */
volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
/* Parallel I/O */
volatile unsigned short pio_padir; /* port A data direction reg */
volatile unsigned short pio_papar; /* port A pin assignment reg */
volatile unsigned short pio_paodr; /* port A open drain reg */
volatile unsigned short pio_padat; /* port A data register */
volatile unsigned char RESERVED28[0x8]; /* Reserved area */
volatile unsigned short pio_pcdir; /* port C data direction reg*/
volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
volatile unsigned short pio_pcso; /* port C special options */
volatile unsigned short pio_pcdat; /* port C data register */
volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
volatile unsigned char RESERVED29[0x16]; /* Reserved area */
/* Timer */
volatile unsigned short timer_tgcr; /* timer global configuration reg */
volatile unsigned char RESERVED30[0xe]; /* Reserved area */
volatile unsigned short timer_tmr1; /* timer 1 mode reg */
volatile unsigned short timer_tmr2; /* timer 2 mode reg */
volatile unsigned short timer_trr1; /* timer 1 referance reg */
volatile unsigned short timer_trr2; /* timer 2 referance reg */
volatile unsigned short timer_tcr1; /* timer 1 capture reg */
volatile unsigned short timer_tcr2; /* timer 2 capture reg */
volatile unsigned short timer_tcn1; /* timer 1 counter reg */
volatile unsigned short timer_tcn2; /* timer 2 counter reg */
volatile unsigned short timer_tmr3; /* timer 3 mode reg */
volatile unsigned short timer_tmr4; /* timer 4 mode reg */
volatile unsigned short timer_trr3; /* timer 3 referance reg */
volatile unsigned short timer_trr4; /* timer 4 referance reg */
volatile unsigned short timer_tcr3; /* timer 3 capture reg */
volatile unsigned short timer_tcr4; /* timer 4 capture reg */
volatile unsigned short timer_tcn3; /* timer 3 counter reg */
volatile unsigned short timer_tcn4; /* timer 4 counter reg */
volatile unsigned short timer_ter1; /* timer 1 event reg */
volatile unsigned short timer_ter2; /* timer 2 event reg */
volatile unsigned short timer_ter3; /* timer 3 event reg */
volatile unsigned short timer_ter4; /* timer 4 event reg */
volatile unsigned char RESERVED34[0x8]; /* Reserved area */
/* CP */
volatile unsigned short cp_cr; /* command register */
volatile unsigned char RESERVED35[0x2]; /* Reserved area */
volatile unsigned short cp_rccr; /* main configuration reg */
volatile unsigned char RESERVED37; /* Reserved area */
volatile unsigned char cp_rmds; /* development support status reg */
volatile unsigned long cp_rmdr; /* development support control reg */
volatile unsigned short cp_rctr1; /* ram break register 1 */
volatile unsigned short cp_rctr2; /* ram break register 2 */
volatile unsigned short cp_rctr3; /* ram break register 3 */
volatile unsigned short cp_rctr4; /* ram break register 4 */
volatile unsigned char RESERVED59[0x2]; /* Reserved area */
volatile unsigned short cp_rter; /* RISC timers event reg */
volatile unsigned char RESERVED38[0x2]; /* Reserved area */
volatile unsigned short cp_rtmr; /* RISC timers mask reg */
volatile unsigned char RESERVED39[0x14]; /* Reserved area */
/* BRG */
union {
volatile unsigned long l;
struct {
volatile unsigned short BRGC_RESERV:14;
volatile unsigned short rst:1;
volatile unsigned short en:1;
volatile unsigned short extc:2;
volatile unsigned short atb:1;
volatile unsigned short cd:12;
volatile unsigned short div16:1;
} b;
} brgc[4]; /* BRG1-BRG4 configuration regs*/
/* SCC registers */
struct scc_regs {
union {
struct {
/* Low word. */
volatile unsigned short GSMR_RESERV2:1;
volatile unsigned short edge:2;
volatile unsigned short tci:1;
volatile unsigned short tsnc:2;
volatile unsigned short rinv:1;
volatile unsigned short tinv:1;
volatile unsigned short tpl:3;
volatile unsigned short tpp:2;
volatile unsigned short tend:1;
volatile unsigned short tdcr:2;
volatile unsigned short rdcr:2;
volatile unsigned short renc:3;
volatile unsigned short tenc:3;
volatile unsigned short diag:2;
volatile unsigned short enr:1;
volatile unsigned short ent:1;
volatile unsigned short mode:4;
/* High word. */
volatile unsigned short GSMR_RESERV1:14;
volatile unsigned short pri:1;
volatile unsigned short gde:1;
volatile unsigned short tcrc:2;
volatile unsigned short revd:1;
volatile unsigned short trx:1;
volatile unsigned short ttx:1;
volatile unsigned short cdp:1;
volatile unsigned short ctsp:1;
volatile unsigned short cds:1;
volatile unsigned short ctss:1;
volatile unsigned short tfl:1;
volatile unsigned short rfw:1;
volatile unsigned short txsy:1;
volatile unsigned short synl:2;
volatile unsigned short rtsm:1;
volatile unsigned short rsyn:1;
} b;
struct {
volatile unsigned long low;
volatile unsigned long high;
} w;
} scc_gsmr; /* SCC general mode reg */
volatile unsigned short scc_psmr; /* protocol specific mode reg */
volatile unsigned char RESERVED42[0x2]; /* Reserved area */
volatile unsigned short scc_todr; /* SCC transmit on demand */
volatile unsigned short scc_dsr; /* SCC data sync reg */
volatile unsigned short scc_scce; /* SCC event reg */
volatile unsigned char RESERVED43[0x2];/* Reserved area */
volatile unsigned short scc_sccm; /* SCC mask reg */
volatile unsigned char RESERVED44[0x1];/* Reserved area */
volatile unsigned char scc_sccs; /* SCC status reg */
volatile unsigned char RESERVED45[0x8]; /* Reserved area */
} scc_regs[4];
/* SMC */
struct smc_regs {
volatile unsigned char RESERVED46[0x2]; /* Reserved area */
volatile unsigned short smc_smcmr; /* SMC mode reg */
volatile unsigned char RESERVED60[0x2]; /* Reserved area */
volatile unsigned char smc_smce; /* SMC event reg */
volatile unsigned char RESERVED47[0x3]; /* Reserved area */
volatile unsigned char smc_smcm; /* SMC mask reg */
volatile unsigned char RESERVED48[0x5]; /* Reserved area */
} smc_regs[2];
/* SPI */
volatile unsigned short spi_spmode; /* SPI mode reg */
volatile unsigned char RESERVED51[0x4]; /* Reserved area */
volatile unsigned char spi_spie; /* SPI event reg */
volatile unsigned char RESERVED52[0x3]; /* Reserved area */
volatile unsigned char spi_spim; /* SPI mask reg */
volatile unsigned char RESERVED53[0x2]; /* Reserved area */
volatile unsigned char spi_spcom; /* SPI command reg */
volatile unsigned char RESERVED54[0x4]; /* Reserved area */
/* PIP */
volatile unsigned short pip_pipc; /* pip configuration reg */
volatile unsigned char RESERVED65[0x2]; /* Reserved area */
volatile unsigned short pip_ptpr; /* pip timing parameters reg */
volatile unsigned long pip_pbdir; /* port b data direction reg */
volatile unsigned long pip_pbpar; /* port b pin assignment reg */
volatile unsigned long pip_pbodr; /* port b open drain reg */
volatile unsigned long pip_pbdat; /* port b data reg */
volatile unsigned char RESERVED71[0x18]; /* Reserved area */
/* Serial Interface */
volatile unsigned long si_simode; /* SI mode register */
volatile unsigned char si_sigmr; /* SI global mode register */
volatile unsigned char RESERVED55; /* Reserved area */
volatile unsigned char si_sistr; /* SI status register */
volatile unsigned char si_sicmr; /* SI command register */
volatile unsigned char RESERVED56[0x4]; /* Reserved area */
volatile unsigned long si_sicr; /* SI clock routing */
volatile unsigned long si_sirp; /* SI ram pointers */
volatile unsigned char RESERVED57[0xc]; /* Reserved area */
volatile unsigned short si_siram[0x80]; /* SI routing ram */
} QUICC;
#endif
/*
* Local variables:
* c-indent-level: 4
* c-basic-offset: 4
* tab-width: 4
* End:
*/

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arch/m68k/include/asm/m68360_regs.h Normal file
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/***********************************
* $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
***********************************
*
***************************************
* Definitions of the QUICC registers
***************************************
*/
#ifndef __REGISTERS_H
#define __REGISTERS_H
#define CLEAR_BIT(x, bit) x =bit
/*****************************************************************
Command Register
*****************************************************************/
/* bit fields within command register */
#define SOFTWARE_RESET 0x8000
#define CMD_OPCODE 0x0f00
#define CMD_CHANNEL 0x00f0
#define CMD_FLAG 0x0001
/* general command opcodes */
#define INIT_RXTX_PARAMS 0x0000
#define INIT_RX_PARAMS 0x0100
#define INIT_TX_PARAMS 0x0200
#define ENTER_HUNT_MODE 0x0300
#define STOP_TX 0x0400
#define GR_STOP_TX 0x0500
#define RESTART_TX 0x0600
#define CLOSE_RX_BD 0x0700
#define SET_ENET_GROUP 0x0800
#define RESET_ENET_GROUP 0x0900
/* quicc32 CP commands */
#define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */
#define ENTER_HUNT_MODE_32 0x1e00
/* quicc32 mask/event SCC register */
#define GOV 0x01
#define GUN 0x02
#define GINT 0x04
#define IQOV 0x08
/* Timer commands */
#define SET_TIMER 0x0800
/* Multi channel Interrupt structure */
#define INTR_VALID 0x8000 /* Valid interrupt entry */
#define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */
#define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */
#define INTR_MASK_BITS 0x383f
/*
* General SCC mode register (GSMR)
*/
#define MODE_HDLC 0x0
#define MODE_APPLE_TALK 0x2
#define MODE_SS7 0x3
#define MODE_UART 0x4
#define MODE_PROFIBUS 0x5
#define MODE_ASYNC_HDLC 0x6
#define MODE_V14 0x7
#define MODE_BISYNC 0x8
#define MODE_DDCMP 0x9
#define MODE_MULTI_CHANNEL 0xa
#define MODE_ETHERNET 0xc
#define DIAG_NORMAL 0x0
#define DIAG_LOCAL_LPB 0x1
#define DIAG_AUTO_ECHO 0x2
#define DIAG_LBP_ECHO 0x3
/* For RENC and TENC fields in GSMR */
#define ENC_NRZ 0x0
#define ENC_NRZI 0x1
#define ENC_FM0 0x2
#define ENC_MANCH 0x4
#define ENC_DIFF_MANC 0x6
/* For TDCR and RDCR fields in GSMR */
#define CLOCK_RATE_1 0x0
#define CLOCK_RATE_8 0x1
#define CLOCK_RATE_16 0x2
#define CLOCK_RATE_32 0x3
#define TPP_00 0x0
#define TPP_10 0x1
#define TPP_01 0x2
#define TPP_11 0x3
#define TPL_NO 0x0
#define TPL_8 0x1
#define TPL_16 0x2
#define TPL_32 0x3
#define TPL_48 0x4
#define TPL_64 0x5
#define TPL_128 0x6
#define TSNC_INFINITE 0x0
#define TSNC_14_65 0x1
#define TSNC_4_15 0x2
#define TSNC_3_1 0x3
#define EDGE_BOTH 0x0
#define EDGE_POS 0x1
#define EDGE_NEG 0x2
#define EDGE_NO 0x3
#define SYNL_NO 0x0
#define SYNL_4 0x1
#define SYNL_8 0x2
#define SYNL_16 0x3
#define TCRC_CCITT16 0x0
#define TCRC_CRC16 0x1
#define TCRC_CCITT32 0x2
/*****************************************************************
TODR (Transmit on demand) Register
*****************************************************************/
#define TODR_TOD 0x8000 /* Transmit on demand */
/*****************************************************************
CICR register settings
*****************************************************************/
/* note that relative irq priorities of the SCCs can be reordered
* if desired - see p. 7-377 of the MC68360UM */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
/*****************************************************************
Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379)
*****************************************************************/
#define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */
#define INTR_SCC1 0x40000000 /* SCC port 1 */
#define INTR_SCC2 0x20000000 /* SCC port 2 */
#define INTR_SCC3 0x10000000 /* SCC port 3 */
#define INTR_SCC4 0x08000000 /* SCC port 4 */
#define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */
#define INTR_TIMER1 0x02000000 /* timer 1 */
#define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */
#define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */
#define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */
#define INTR_DMA1 0x00200000 /* idma 1 */
#define INTR_DMA2 0x00100000 /* idma 2 */
#define INTR_TIMER2 0x00040000 /* timer 2 */
#define INTR_CP_TIMER 0x00020000 /* CP timer */
#define INTR_PIP_STATUS 0x00010000 /* PIP status */
#define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */
#define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */
#define INTR_TIMER3 0x00001000 /* timer 3 */
#define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */
#define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */
#define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */
#define INTR_TIMER4 0x00000080 /* timer 4 */
#define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */
#define INTR_SCP 0x00000020 /* SCP */
#define INTR_SMC1 0x00000010 /* SMC 1 */
#define INTR_SMC2 0x00000008 /* SMC 2 */
#define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */
#define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */
#define INTR_ERR 0x00000001 /* error */
/*****************************************************************
CPM Interrupt vector encodings (MC68360UM p. 7-376)
*****************************************************************/
#define CPMVEC_NR 32
#define CPMVEC_PIO_PC0 0x1f
#define CPMVEC_SCC1 0x1e
#define CPMVEC_SCC2 0x1d
#define CPMVEC_SCC3 0x1c
#define CPMVEC_SCC4 0x1b
#define CPMVEC_PIO_PC1 0x1a
#define CPMVEC_TIMER1 0x19
#define CPMVEC_PIO_PC2 0x18
#define CPMVEC_PIO_PC3 0x17
#define CPMVEC_SDMA_CB_ERR 0x16
#define CPMVEC_IDMA1 0x15
#define CPMVEC_IDMA2 0x14
#define CPMVEC_RESERVED3 0x13
#define CPMVEC_TIMER2 0x12
#define CPMVEC_RISCTIMER 0x11
#define CPMVEC_RESERVED2 0x10
#define CPMVEC_PIO_PC4 0x0f
#define CPMVEC_PIO_PC5 0x0e
#define CPMVEC_TIMER3 0x0c
#define CPMVEC_PIO_PC6 0x0b
#define CPMVEC_PIO_PC7 0x0a
#define CPMVEC_PIO_PC8 0x09
#define CPMVEC_RESERVED1 0x08
#define CPMVEC_TIMER4 0x07
#define CPMVEC_PIO_PC9 0x06
#define CPMVEC_SPI 0x05
#define CPMVEC_SMC1 0x04
#define CPMVEC_SMC2 0x03
#define CPMVEC_PIO_PC10 0x02
#define CPMVEC_PIO_PC11 0x01
#define CPMVEC_ERROR 0x00
/* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */
/* #define CPMVEC_SCC1 ((ushort)0x1e) */
/* #define CPMVEC_SCC2 ((ushort)0x1d) */
/* #define CPMVEC_SCC3 ((ushort)0x1c) */
/* #define CPMVEC_SCC4 ((ushort)0x1b) */
/* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */
/* #define CPMVEC_TIMER1 ((ushort)0x19) */
/* #define CPMVEC_PIO_PC2 ((ushort)0x18) */
/* #define CPMVEC_PIO_PC3 ((ushort)0x17) */
/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
/* #define CPMVEC_IDMA1 ((ushort)0x15) */
/* #define CPMVEC_IDMA2 ((ushort)0x14) */
/* #define CPMVEC_RESERVED3 ((ushort)0x13) */
/* #define CPMVEC_TIMER2 ((ushort)0x12) */
/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
/* #define CPMVEC_RESERVED2 ((ushort)0x10) */
/* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */
/* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */
/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
/* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */
/* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */
/* #define CPMVEC_PIO_PC8 ((ushort)0x09) */
/* #define CPMVEC_RESERVED1 ((ushort)0x08) */
/* #define CPMVEC_TIMER4 ((ushort)0x07) */
/* #define CPMVEC_PIO_PC9 ((ushort)0x06) */
/* #define CPMVEC_SPI ((ushort)0x05) */
/* #define CPMVEC_SMC1 ((ushort)0x04) */
/* #define CPMVEC_SMC2 ((ushort)0x03) */
/* #define CPMVEC_PIO_PC10 ((ushort)0x02) */
/* #define CPMVEC_PIO_PC11 ((ushort)0x01) */
/* #define CPMVEC_ERROR ((ushort)0x00) */
/*****************************************************************
* PIO control registers
*****************************************************************/
/* Port A - See 360UM p. 7-358
*
* Note that most of these pins have alternate functions
*/
/* The macros are nice, but there are all sorts of references to 1-indexed
* facilities on the 68360... */
/* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */
/* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */
#define PA_RXD1 ((ushort)0x0001)
#define PA_TXD1 ((ushort)0x0002)
#define PA_RXD2 ((ushort)0x0004)
#define PA_TXD2 ((ushort)0x0008)
#define PA_RXD3 ((ushort)0x0010)
#define PA_TXD3 ((ushort)0x0020)
#define PA_RXD4 ((ushort)0x0040)
#define PA_TXD4 ((ushort)0x0080)
#define PA_CLK1 ((ushort)0x0100)
#define PA_CLK2 ((ushort)0x0200)
#define PA_CLK3 ((ushort)0x0400)
#define PA_CLK4 ((ushort)0x0800)
#define PA_CLK5 ((ushort)0x1000)
#define PA_CLK6 ((ushort)0x2000)
#define PA_CLK7 ((ushort)0x4000)
#define PA_CLK8 ((ushort)0x8000)
/* Port B - See 360UM p. 7-362
*/
/* Port C - See 360UM p. 7-365
*/
#define PC_RTS1 ((ushort)0x0001)
#define PC_RTS2 ((ushort)0x0002)
#define PC__RTS3 ((ushort)0x0004) /* !RTS3 */
#define PC__RTS4 ((ushort)0x0008) /* !RTS4 */
#define PC_CTS1 ((ushort)0x0010)
#define PC_CD1 ((ushort)0x0020)
#define PC_CTS2 ((ushort)0x0040)
#define PC_CD2 ((ushort)0x0080)
#define PC_CTS3 ((ushort)0x0100)
#define PC_CD3 ((ushort)0x0200)
#define PC_CTS4 ((ushort)0x0400)
#define PC_CD4 ((ushort)0x0800)
/*****************************************************************
chip select option register
*****************************************************************/
#define DTACK 0xe000
#define ADR_MASK 0x1ffc
#define RDWR_MASK 0x0002
#define FC_MASK 0x0001
/*****************************************************************
tbase and rbase registers
*****************************************************************/
#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \
(quicc->ch_or_u.u.udata_bd_ucode + pram->tbase))
#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \
(quicc->ch_or_u.u.udata_bd_ucode + pram->rbase))
#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
(quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr))
#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
(quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr))
#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \
((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \
((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
#define INCREASE_TBD(bd,quicc,pram) { \
if((bd)->status & T_W) \
(bd) = TBD_ADDR(quicc,pram); \
else \
(bd)++; \
}
#define DECREASE_TBD(bd,quicc,pram) { \
if ((bd) == TBD_ADDR(quicc, pram)) \
while (!((bd)->status & T_W)) \
(bd)++; \
else \
(bd)--; \
}
#define INCREASE_RBD(bd,quicc,pram) { \
if((bd)->status & R_W) \
(bd) = RBD_ADDR(quicc,pram); \
else \
(bd)++; \
}
#define DECREASE_RBD(bd,quicc,pram) { \
if ((bd) == RBD_ADDR(quicc, pram)) \
while (!((bd)->status & T_W)) \
(bd)++; \
else \
(bd)--; \
}
/*****************************************************************
Macros for Multi channel
*****************************************************************/
#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page])
#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase)
#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \
(&(quicc->ch_or_u.ch_pram_tbl[channel])))
#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase)))
#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase)))
#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr)))
#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
(MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr)))
#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \
((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \
((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
#define INCREASE_TBD_32(bd,quicc,page,channel) { \
if((bd)->status & T_W) \
(bd) = TBD_32_ADDR(quicc,page,channel); \
else \
(bd)++; \
}
#define DECREASE_TBD_32(bd,quicc,page,channel) { \
if ((bd) == TBD_32_ADDR(quicc, page,channel)) \
while (!((bd)->status & T_W)) \
(bd)++; \
else \
(bd)--; \
}
#define INCREASE_RBD_32(bd,quicc,page,channel) { \
if((bd)->status & R_W) \
(bd) = RBD_32_ADDR(quicc,page,channel); \
else \
(bd)++; \
}
#define DECREASE_RBD_32(bd,quicc,page,channel) { \
if ((bd) == RBD_32_ADDR(quicc, page,channel)) \
while (!((bd)->status & T_W)) \
(bd)++; \
else \
(bd)--; \
}
#endif

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arch/m68k/include/asm/mac_asc.h Normal file
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/*
* Apple Sound Chip
*/
#ifndef __ASM_MAC_ASC_H
#define __ASM_MAC_ASC_H
/*
* ASC offsets and controls
*/
#define ASC_BUF_BASE 0x00 /* RAM buffer offset */
#define ASC_BUF_SIZE 0x800
#define ASC_CONTROL 0x800
#define ASC_CONTROL_OFF 0x00
#define ASC_FREQ(chan,byte) ((0x810)+((chan)<<3)+(byte))
#define ASC_ENABLE 0x801
#define ASC_ENABLE_SAMPLE 0x02
#define ASC_MODE 0x802
#define ASC_MODE_SAMPLE 0x02
#define ASC_VOLUME 0x806
#define ASC_CHAN 0x807 /* ??? */
#endif

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arch/m68k/include/asm/mac_baboon.h Normal file
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/*
* Definitions for the "Baboon" custom IC on the PowerBook 190.
*/
#define BABOON_BASE (0x50F1A000) /* same as IDE controller base */
#ifndef __ASSEMBLY__
struct baboon {
char pad1[208]; /* generic IDE registers, not used here */
short mb_control; /* Control register:
* bit 5 : slot 2 power control
* bit 6 : slot 1 power control
*/
char pad2[2];
short mb_status; /* (0xD4) media bay status register:
*
* bit 0: ????
* bit 1: IDE interrupt active?
* bit 2: bay status, 0 = full, 1 = empty
* bit 3: ????
*/
char pad3[2]; /* (0xD6) not used */
short mb_ifr; /* (0xD8) media bay interrupt flags register:
*
* bit 0: ????
* bit 1: IDE controller interrupt
* bit 2: media bay status change interrupt
*/
};
extern int baboon_present;
extern void baboon_register_interrupts(void);
extern void baboon_irq_enable(int);
extern void baboon_irq_disable(int);
#endif /* __ASSEMBLY **/

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arch/m68k/include/asm/mac_iop.h Normal file
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/*
* I/O Processor (IOP) defines and structures, mostly snagged from A/UX
* header files.
*
* The original header from which this was taken is copyrighted. I've done some
* rewriting (in fact my changes make this a bit more readable, IMHO) but some
* more should be done.
*/
/*
* This is the base address of the IOPs. Use this as the address of
* a "struct iop" (see below) to see where the actual registers fall.
*/
#define SCC_IOP_BASE_IIFX (0x50F04000)
#define ISM_IOP_BASE_IIFX (0x50F12000)
#define SCC_IOP_BASE_QUADRA (0x50F0C000)
#define ISM_IOP_BASE_QUADRA (0x50F1E000)
/* IOP status/control register bits: */
#define IOP_BYPASS 0x01 /* bypass-mode hardware access */
#define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */
#define IOP_RUN 0x04 /* set to 0 to reset IOP chip */
#define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */
#define IOP_INT0 0x10 /* intr priority from IOP to host */
#define IOP_INT1 0x20 /* intr priority from IOP to host */
#define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */
#define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */
#define NUM_IOPS 2
#define NUM_IOP_CHAN 7
#define NUM_IOP_MSGS NUM_IOP_CHAN*8
#define IOP_MSG_LEN 32
/* IOP reference numbers, used by the globally-visible iop_xxx functions */
#define IOP_NUM_SCC 0
#define IOP_NUM_ISM 1
/* IOP channel states */
#define IOP_MSG_IDLE 0 /* idle */
#define IOP_MSG_NEW 1 /* new message sent */
#define IOP_MSG_RCVD 2 /* message received; processing */
#define IOP_MSG_COMPLETE 3 /* message processing complete */
/* IOP message status codes */
#define IOP_MSGSTATUS_UNUSED 0 /* Unusued message structure */
#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */
#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */
#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */
#define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */
/* IOP memory addresses of the members of the mac_iop_kernel structure. */
#define IOP_ADDR_MAX_SEND_CHAN 0x0200
#define IOP_ADDR_SEND_STATE 0x0201
#define IOP_ADDR_PATCH_CTRL 0x021F
#define IOP_ADDR_SEND_MSG 0x0220
#define IOP_ADDR_MAX_RECV_CHAN 0x0300
#define IOP_ADDR_RECV_STATE 0x0301
#define IOP_ADDR_ALIVE 0x031F
#define IOP_ADDR_RECV_MSG 0x0320
#ifndef __ASSEMBLY__
/*
* IOP Control registers, staggered because in usual Apple style they were
* too lazy to decode the A0 bit. This structure is assumed to begin at
* one of the xxx_IOP_BASE addresses given above.
*/
struct mac_iop {
__u8 ram_addr_hi; /* shared RAM address hi byte */
__u8 pad0;
__u8 ram_addr_lo; /* shared RAM address lo byte */
__u8 pad1;
__u8 status_ctrl; /* status/control register */
__u8 pad2[3];
__u8 ram_data; /* RAM data byte at ramhi/lo */
__u8 pad3[23];
/* Bypass-mode hardware access registers */
union {
struct { /* SCC registers */
__u8 sccb_cmd; /* SCC B command reg */
__u8 pad4;
__u8 scca_cmd; /* SCC A command reg */
__u8 pad5;
__u8 sccb_data; /* SCC B data */
__u8 pad6;
__u8 scca_data; /* SCC A data */
} scc_regs;
struct { /* ISM registers */
__u8 wdata; /* write a data byte */
__u8 pad7;
__u8 wmark; /* write a mark byte */
__u8 pad8;
__u8 wcrc; /* write 2-byte crc to disk */
__u8 pad9;
__u8 wparams; /* write the param regs */
__u8 pad10;
__u8 wphase; /* write the phase states & dirs */
__u8 pad11;
__u8 wsetup; /* write the setup register */
__u8 pad12;
__u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */
__u8 pad13;
__u8 wones; /* mode reg: 1's set bits, 0's are x */
__u8 pad14;
__u8 rdata; /* read a data byte */
__u8 pad15;
__u8 rmark; /* read a mark byte */
__u8 pad16;
__u8 rerror; /* read the error register */
__u8 pad17;
__u8 rparams; /* read the param regs */
__u8 pad18;
__u8 rphase; /* read the phase states & dirs */
__u8 pad19;
__u8 rsetup; /* read the setup register */
__u8 pad20;
__u8 rmode; /* read the mode register */
__u8 pad21;
__u8 rhandshake; /* read the handshake register */
} ism_regs;
} b;
};
/* This structure is used to track IOP messages in the Linux kernel */
struct iop_msg {
struct iop_msg *next; /* next message in queue or NULL */
uint iop_num; /* IOP number */
uint channel; /* channel number */
void *caller_priv; /* caller private data */
int status; /* status of this message */
__u8 message[IOP_MSG_LEN]; /* the message being sent/received */
__u8 reply[IOP_MSG_LEN]; /* the reply to the message */
void (*handler)(struct iop_msg *);
/* function to call when reply recvd */
};
extern int iop_scc_present,iop_ism_present;
extern int iop_listen(uint, uint,
void (*handler)(struct iop_msg *),
const char *);
extern int iop_send_message(uint, uint, void *, uint, __u8 *,
void (*)(struct iop_msg *));
extern void iop_complete_message(struct iop_msg *);
extern void iop_upload_code(uint, __u8 *, uint, __u16);
extern void iop_download_code(uint, __u8 *, uint, __u16);
extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16);
extern void iop_register_interrupts(void);
#endif /* __ASSEMBLY__ */

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arch/m68k/include/asm/mac_oss.h Normal file
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/*
* OSS
*
* This is used in place of VIA2 on the IIfx.
*/
#define OSS_BASE (0x50f1a000)
/*
* Interrupt level offsets for mac_oss->irq_level
*/
#define OSS_NUBUS0 0
#define OSS_NUBUS1 1
#define OSS_NUBUS2 2
#define OSS_NUBUS3 3
#define OSS_NUBUS4 4
#define OSS_NUBUS5 5
#define OSS_IOPISM 6
#define OSS_IOPSCC 7
#define OSS_SOUND 8
#define OSS_SCSI 9
#define OSS_60HZ 10
#define OSS_VIA1 11
#define OSS_UNUSED1 12
#define OSS_UNUSED2 13
#define OSS_PARITY 14
#define OSS_UNUSED3 15
#define OSS_NUM_SOURCES 16
/*
* Pending interrupt bits in mac_oss->irq_pending
*/
#define OSS_IP_NUBUS0 0x0001
#define OSS_IP_NUBUS1 0x0002
#define OSS_IP_NUBUS2 0x0004
#define OSS_IP_NUBUS3 0x0008
#define OSS_IP_NUBUS4 0x0010
#define OSS_IP_NUBUS5 0x0020
#define OSS_IP_IOPISM 0x0040
#define OSS_IP_IOPSCC 0x0080
#define OSS_IP_SOUND 0x0100
#define OSS_IP_SCSI 0x0200
#define OSS_IP_60HZ 0x0400
#define OSS_IP_VIA1 0x0800
#define OSS_IP_UNUSED1 0x1000
#define OSS_IP_UNUSED2 0x2000
#define OSS_IP_PARITY 0x4000
#define OSS_IP_UNUSED3 0x8000
#define OSS_IP_NUBUS (OSS_IP_NUBUS0|OSS_IP_NUBUS1|OSS_IP_NUBUS2|OSS_IP_NUBUS3|OSS_IP_NUBUS4|OSS_IP_NUBUS5)
/*
* Rom Control Register
*/
#define OSS_POWEROFF 0x80
#ifndef __ASSEMBLY__
struct mac_oss {
__u8 irq_level[0x10]; /* [0x000-0x00f] Interrupt levels */
__u8 padding0[0x1F2]; /* [0x010-0x201] IO space filler */
__u16 irq_pending; /* [0x202-0x203] pending interrupts bits */
__u8 rom_ctrl; /* [0x204-0x204] ROM cntl reg (for poweroff) */
__u8 padding1[0x2]; /* [0x205-0x206] currently unused by A/UX */
__u8 ack_60hz; /* [0x207-0x207] 60 Hz ack. */
};
extern volatile struct mac_oss *oss;
extern int oss_present;
extern void oss_register_interrupts(void);
extern void oss_irq_enable(int);
extern void oss_irq_disable(int);
#endif /* __ASSEMBLY__ */

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arch/m68k/include/asm/mac_psc.h Normal file
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/*
* Apple Peripheral System Controller (PSC)
*
* The PSC is used on the AV Macs to control IO functions not handled
* by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
* channels.
*
* The first seven DMA channels appear to be "one-shot" and are actually
* sets of two channels; one member is active while the other is being
* configured, and then you flip the active member and start all over again.
* The one-shot channels are grouped together and are:
*
* 1. SCSI
* 2. Ethernet Read
* 3. Ethernet Write
* 4. Floppy Disk Controller
* 5. SCC Channel A Receive
* 6. SCC Channel B Receive
* 7. SCC Channel A Transmit
*
* The remaining two channels are handled somewhat differently. They appear
* to be closely tied and share one set of registers. They also seem to run
* continuously, although how you keep the buffer filled in this scenario is
* not understood as there seems to be only one input and one output buffer
* pointer.
*
* Much of this was extrapolated from what was known about the Ethernet
* registers and subsequently confirmed using MacsBug (ie by pinging the
* machine with easy-to-find patterns and looking for them in the DMA
* buffers, or by sending a file over the serial ports and finding the
* file in the buffers.)
*
* 1999-05-25 (jmt)
*/
#define PSC_BASE (0x50F31000)
/*
* The IER/IFR registers work like the VIA, except that it has 4
* of them each on different interrupt levels, and each register
* set only seems to handle four interrupts instead of seven.
*
* To access a particular set of registers, add 0xn0 to the base
* where n = 3,4,5 or 6.
*/
#define pIFRbase 0x100
#define pIERbase 0x104
/*
* One-shot DMA control registers
*/
#define PSC_MYSTERY 0x804
#define PSC_CTL_BASE 0xC00
#define PSC_SCSI_CTL 0xC00
#define PSC_ENETRD_CTL 0xC10
#define PSC_ENETWR_CTL 0xC20
#define PSC_FDC_CTL 0xC30
#define PSC_SCCA_CTL 0xC40
#define PSC_SCCB_CTL 0xC50
#define PSC_SCCATX_CTL 0xC60
/*
* DMA channels. Add +0x10 for the second channel in the set.
* You're supposed to use one channel while the other runs and
* then flip channels and do the whole thing again.
*/
#define PSC_ADDR_BASE 0x1000
#define PSC_LEN_BASE 0x1004
#define PSC_CMD_BASE 0x1008
#define PSC_SET0 0x00
#define PSC_SET1 0x10
#define PSC_SCSI_ADDR 0x1000 /* confirmed */
#define PSC_SCSI_LEN 0x1004 /* confirmed */
#define PSC_SCSI_CMD 0x1008 /* confirmed */
#define PSC_ENETRD_ADDR 0x1020 /* confirmed */
#define PSC_ENETRD_LEN 0x1024 /* confirmed */
#define PSC_ENETRD_CMD 0x1028 /* confirmed */
#define PSC_ENETWR_ADDR 0x1040 /* confirmed */
#define PSC_ENETWR_LEN 0x1044 /* confirmed */
#define PSC_ENETWR_CMD 0x1048 /* confirmed */
#define PSC_FDC_ADDR 0x1060 /* strongly suspected */
#define PSC_FDC_LEN 0x1064 /* strongly suspected */
#define PSC_FDC_CMD 0x1068 /* strongly suspected */
#define PSC_SCCA_ADDR 0x1080 /* confirmed */
#define PSC_SCCA_LEN 0x1084 /* confirmed */
#define PSC_SCCA_CMD 0x1088 /* confirmed */
#define PSC_SCCB_ADDR 0x10A0 /* confirmed */
#define PSC_SCCB_LEN 0x10A4 /* confirmed */
#define PSC_SCCB_CMD 0x10A8 /* confirmed */
#define PSC_SCCATX_ADDR 0x10C0 /* confirmed */
#define PSC_SCCATX_LEN 0x10C4 /* confirmed */
#define PSC_SCCATX_CMD 0x10C8 /* confirmed */
/*
* Free-running DMA registers. The only part known for sure are the bits in
* the control register, the buffer addresses and the buffer length. Everything
* else is anybody's guess.
*
* These registers seem to be mirrored every thirty-two bytes up until offset
* 0x300. It's safe to assume then that a new set of registers starts there.
*/
#define PSC_SND_CTL 0x200 /*
* [ 16-bit ]
* Sound (Singer?) control register.
*
* bit 0 : ????
* bit 1 : ????
* bit 2 : Set to one to enable sound
* output. Possibly a mute flag.
* bit 3 : ????
* bit 4 : ????
* bit 5 : ????
* bit 6 : Set to one to enable pass-thru
* audio. In this mode the audio data
* seems to appear in both the input
* buffer and the output buffer.
* bit 7 : Set to one to activate the
* sound input DMA or zero to
* disable it.
* bit 8 : Set to one to activate the
* sound output DMA or zero to
* disable it.
* bit 9 : \
* bit 11 : |
* These two bits control the sample
* rate. Usually set to binary 10 and
* MacOS 8.0 says I'm at 48 KHz. Using
* a binary value of 01 makes things
* sound about 1/2 speed (24 KHz?) and
* binary 00 is slower still (22 KHz?)
*
* Setting this to 0x0000 is a good way to
* kill all DMA at boot time so that the
* PSC won't overwrite the kernel image
* with sound data.
*/
/*
* 0x0202 - 0x0203 is unused. Writing there
* seems to clobber the control register.
*/
#define PSC_SND_SOURCE 0x204 /*
* [ 32-bit ]
* Controls input source and volume:
*
* bits 12-15 : input source volume, 0 - F
* bits 16-19 : unknown, always 0x5
* bits 20-23 : input source selection:
* 0x3 = CD Audio
* 0x4 = External Audio
*
* The volume is definitely not the general
* output volume as it doesn't affect the
* alert sound volume.
*/
#define PSC_SND_STATUS1 0x208 /*
* [ 32-bit ]
* Appears to be a read-only status register.
* The usual value is 0x00400002.
*/
#define PSC_SND_HUH3 0x20C /*
* [ 16-bit ]
* Unknown 16-bit value, always 0x0000.
*/
#define PSC_SND_BITS2GO 0x20E /*
* [ 16-bit ]
* Counts down to zero from some constant
* value. The value appears to be the
* number of _bits_ remaining before the
* buffer is full, which would make sense
* since Apple's docs say the sound DMA
* channels are 1 bit wide.
*/
#define PSC_SND_INADDR 0x210 /*
* [ 32-bit ]
* Address of the sound input DMA buffer
*/
#define PSC_SND_OUTADDR 0x214 /*
* [ 32-bit ]
* Address of the sound output DMA buffer
*/
#define PSC_SND_LEN 0x218 /*
* [ 16-bit ]
* Length of both buffers in eight-byte units.
*/
#define PSC_SND_HUH4 0x21A /*
* [ 16-bit ]
* Unknown, always 0x0000.
*/
#define PSC_SND_STATUS2 0x21C /*
* [ 16-bit ]
* Appears to e a read-only status register.
* The usual value is 0x0200.
*/
#define PSC_SND_HUH5 0x21E /*
* [ 16-bit ]
* Unknown, always 0x0000.
*/
#ifndef __ASSEMBLY__
extern volatile __u8 *psc;
extern int psc_present;
extern void psc_register_interrupts(void);
extern void psc_irq_enable(int);
extern void psc_irq_disable(int);
/*
* Access functions
*/
static inline void psc_write_byte(int offset, __u8 data)
{
*((volatile __u8 *)(psc + offset)) = data;
}
static inline void psc_write_word(int offset, __u16 data)
{
*((volatile __u16 *)(psc + offset)) = data;
}
static inline void psc_write_long(int offset, __u32 data)
{
*((volatile __u32 *)(psc + offset)) = data;
}
static inline u8 psc_read_byte(int offset)
{
return *((volatile __u8 *)(psc + offset));
}
static inline u16 psc_read_word(int offset)
{
return *((volatile __u16 *)(psc + offset));
}
static inline u32 psc_read_long(int offset)
{
return *((volatile __u32 *)(psc + offset));
}
#endif /* __ASSEMBLY__ */

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/*
* 6522 Versatile Interface Adapter (VIA)
*
* There are two of these on the Mac II. Some IRQ's are vectored
* via them as are assorted bits and bobs - eg rtc, adb. The picture
* is a bit incomplete as the Mac documentation doesn't cover this well
*/
#ifndef _ASM_MAC_VIA_H_
#define _ASM_MAC_VIA_H_
/*
* Base addresses for the VIAs. There are two in every machine,
* although on some machines the second is an RBV or an OSS.
* The OSS is different enough that it's handled separately.
*
* Do not use these values directly; use the via1 and via2 variables
* instead (and don't forget to check rbv_present when using via2!)
*/
#define VIA1_BASE (0x50F00000)
#define VIA2_BASE (0x50F02000)
#define RBV_BASE (0x50F26000)
/*
* Not all of these are true post MacII I think.
* CSA: probably the ones CHRP marks as 'unused' change purposes
* when the IWM becomes the SWIM.
* http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html
* ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
*
* also, http://developer.apple.com/technotes/hw/hw_09.html claims the
* following changes for IIfx:
* VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
* Also, "All of the functionality of VIA2 has been moved to other chips".
*/
#define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
* [CHRP] SCC WREQ: Reflects the state of the
* Wait/Request pins from the SCC.
* [Macintosh Family Hardware]
* as CHRP on SE/30,II,IIx,IIcx,IIci.
* on IIfx, "0 means an active request"
*/
#define VIA1A_vRev8 0x40 /* Revision 8 board ???
* [CHRP] En WaitReqB: Lets the WaitReq_L
* signal from port B of the SCC appear on
* the PA7 input pin. Output.
* [Macintosh Family] On the SE/30, this
* is the bit to flip screen buffers.
* 0=alternate, 1=main.
* on II,IIx,IIcx,IIci,IIfx this is a bit
* for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
*/
#define VIA1A_vHeadSel 0x20 /* Head select for IWM.
* [CHRP] unused.
* [Macintosh Family] "Floppy disk
* state-control line SEL" on all but IIfx
*/
#define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx
* this bit enables the "Overlay" address
* map in the address decoders as it is on
* reset for mapping the ROM over the reset
* vector. 1=use overlay map.
* On the IIci,IIfx it is another bit of the
* CPU ID: 0=normal IIci, 1=IIci with parity
* feature or IIfx.
* [CHRP] En WaitReqA: Lets the WaitReq_L
* signal from port A of the SCC appear
* on the PA7 input pin (CHRP). Output.
* [MkLinux] "Drive Select"
* (with 0x20 being 'disk head select')
*/
#define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select:
* 1: select the external serial clock to
* drive the SCC's /RTxCA pin.
* 0: Select the 3.6864MHz clock to drive
* the SCC cell.
* [Macintosh Family] Correct on all but IIfx
*/
/* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
* on Macs which had the PWM sound hardware. Reserved on newer models.
* On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
* bit 2: 1=IIci, 0=IIfx
* bit 1: 1 on both IIci and IIfx.
* MkLinux sez bit 0 is 'burnin flag' in this case.
* CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
* inputs, these bits will read 0.
*/
#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
/* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
* CHRP offers no info. */
#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
* PWM hardware) 0=enabled.
* Also, on IIci w/parity, shows parity error
* 0=error, 1=OK. */
#define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
* On SE/30, vertical sync interrupt enable.
* 0=enabled. This vSync interrupt shows up
* as a slot $E interrupt. */
#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/
#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */
#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
/* MkLinux defines the following "VIA1 Register B contents where they
* differ from standard VIA1". From the naming scheme, we assume they
* correspond to a VIA work-alike named 'EVR'. */
#define EVRB_XCVR 0x08 /* XCVR_SESSION* */
#define EVRB_FULL 0x10 /* VIA_FULL */
#define EVRB_SYSES 0x20 /* SYS_SESSION */
#define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */
#define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */
#define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */
#define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */
/*
* VIA2 A register is the interrupt lines raised off the nubus
* slots.
* The below info is from 'Macintosh Family Hardware.'
* MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
* It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and
* defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
* Perhaps OSS uses vRAM1 and vRAM2 for ADB.
*/
#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */
#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */
#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */
#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */
#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */
/* RAM size bits decoded as follows:
* bit1 bit0 size of ICs in bank A
* 0 0 256 kbit
* 0 1 1 Mbit
* 1 0 4 Mbit
* 1 1 16 Mbit
*/
/*
* Register B has the fun stuff in it
*/
#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
* timer T1.
* on IIci, parity test: 0=test mode.
* [MkLinux] RBV_PARODD: 1=odd,0=even. */
#define VIA2B_vSndJck 0x40 /* External sound jack status.
* 0=plug is inserted. On SE/30, always 0 */
#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
#define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
* on II, AMU/PMMU control.
* if AMU, 0=24bit to 32bit translation
* if PMMU, 1=PMMU is accessing page table.
* on SE/30 tied low.
* on IIx,IIcx,IIfx, unused.
* on IIci/RBV, cache control. 0=flush cache.
*/
#define VIA2B_vPower 0x04 /* Power off, 0=shut off power.
* on SE/30 this signal sent to PDS card. */
#define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked.
* on SE/30 sent to PDS card. */
#define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
* on others, 0=disable processor's instruction
* and data caches. */
/* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html
* Another example of a valid function that has no ROM support is the use
* of the alternate video page for page-flipping animation. Since there
* is no ROM call to flip pages, it is necessary to go play with the
* right bit in the VIA chip (6522 Versatile Interface Adapter).
* [CSA: don't know which one this is, but it's one of 'em!]
*/
/*
* 6522 registers - see databook.
* CSA: Assignments for VIA1 confirmed from CHRP spec.
*/
/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
/* Note: 15 VIA regs, 8 RBV regs */
#define vBufB 0x0000 /* [VIA/RBV] Register B */
#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
#define vSR 0x1400 /* [VIA only] Shift register. */
#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
/* CHRP sez never ever to *write* this.
* Mac family says never to *change* this.
* In fact we need to initialize it once at start. */
#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
/* The RBV only decodes the bottom eight address lines; the VIA doesn't
* decode the bottom eight -- so vBufB | rBufB will always get you BufB */
/* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
* BUT note the values for rIER and rIFR, where the top 8 bits *do* seem
* to matter. In fact *all* of the top 8 bits seem to matter;
* setting rIER=0x1813 and rIFR=0x1803 doesn't work, either.
* Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
*/
#define rBufB 0x0000 /* [VIA/RBV] Register B */
#define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
#define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
#define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */
#define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
#define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
#define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
#define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */
#define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */
/*
* Video monitor parameters, for rMonP:
*/
#define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */
#define RBV_MONID 0x38 /* monitor type, as below. */
#define RBV_VIDOFF 0x40 /* 1 turns off onboard video */
/* Supported monitor types: */
#define MON_15BW (1<<3) /* 15" BW portrait. */
#define MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */
#define MON_15RGB (5<<3) /* 15" RGB portrait. */
#define MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */
#define MON_NONE (7<<3) /* No monitor attached. */
/* To clarify IER manipulations */
#define IER_SET_BIT(b) (0x80 | (1<<(b)) )
#define IER_CLR_BIT(b) (0x7F & (1<<(b)) )
#ifndef __ASSEMBLY__
extern volatile __u8 *via1,*via2;
extern int rbv_present,via_alt_mapping;
struct irq_desc;
extern void via_register_interrupts(void);
extern void via_irq_enable(int);
extern void via_irq_disable(int);
extern void via_nubus_irq_startup(int irq);
extern void via_nubus_irq_shutdown(int irq);
extern void via1_irq(unsigned int irq, struct irq_desc *desc);
extern void via1_set_head(int);
extern int via2_scsi_drq_pending(void);
static inline int rbv_set_video_bpp(int bpp)
{
char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1;
if (!rbv_present || val<0) return -1;
via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val;
return 0;
}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_MAC_VIA_H_ */

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#ifndef _M68K_MACHDEP_H
#define _M68K_MACHDEP_H
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/time.h>
struct pt_regs;
struct mktime;
struct rtc_time;
struct rtc_pll_info;
struct buffer_head;
extern void (*mach_sched_init) (irq_handler_t handler);
/* machine dependent irq functions */
extern void (*mach_init_IRQ) (void);
extern void (*mach_get_model) (char *model);
extern void (*mach_get_hardware_list) (struct seq_file *m);
/* machine dependent timer functions */
extern int (*mach_hwclk)(int, struct rtc_time*);
extern unsigned int (*mach_get_ss)(void);
extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
extern int (*mach_set_clock_mmss)(unsigned long);
extern void (*mach_reset)( void );
extern void (*mach_halt)( void );
extern void (*mach_power_off)( void );
extern unsigned long (*mach_hd_init) (unsigned long, unsigned long);
extern void (*mach_hd_setup)(char *, int *);
extern long mach_max_dma_address;
extern void (*mach_heartbeat) (int);
extern void (*mach_l2_flush) (int);
extern void (*mach_beep) (unsigned int, unsigned int);
/* Hardware clock functions */
extern void hw_timer_init(irq_handler_t handler);
extern unsigned long hw_timer_offset(void);
extern void config_BSP(char *command, int len);
#endif /* _M68K_MACHDEP_H */

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/*
* machines.h: Defines for taking apart the machine type value in the
* idprom and determining the kind of machine we are on.
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Sun3/3x models added by David Monro (davidm@psrg.cs.usyd.edu.au)
*/
#ifndef _SPARC_MACHINES_H
#define _SPARC_MACHINES_H
struct Sun_Machine_Models {
char *name;
unsigned char id_machtype;
};
/* Current number of machines we know about that has an IDPROM
* machtype entry including one entry for the 0x80 OBP machines.
*/
// reduced along with table in arch/m68k/sun3/idprom.c
// sun3 port doesn't need to know about sparc machines.
//#define NUM_SUN_MACHINES 23
#define NUM_SUN_MACHINES 8
/* The machine type in the idprom area looks like this:
*
* ---------------
* | ARCH | MACH |
* ---------------
* 7 4 3 0
*
* The ARCH field determines the architecture line (sun4, sun4c, etc).
* The MACH field determines the machine make within that architecture.
*/
#define SM_ARCH_MASK 0xf0
#define SM_SUN3 0x10
#define SM_SUN4 0x20
#define SM_SUN3X 0x40
#define SM_SUN4C 0x50
#define SM_SUN4M 0x70
#define SM_SUN4M_OBP 0x80
#define SM_TYP_MASK 0x0f
/* Sun3 machines */
#define SM_3_160 0x01 /* Sun 3/160 series */
#define SM_3_50 0x02 /* Sun 3/50 series */
#define SM_3_260 0x03 /* Sun 3/260 series */
#define SM_3_110 0x04 /* Sun 3/110 series */
#define SM_3_60 0x07 /* Sun 3/60 series */
#define SM_3_E 0x08 /* Sun 3/E series */
/* Sun3x machines */
#define SM_3_460 0x01 /* Sun 3/460 (460,470,480) series */
#define SM_3_80 0x02 /* Sun 3/80 series */
/* Sun4 machines */
#define SM_4_260 0x01 /* Sun 4/200 series */
#define SM_4_110 0x02 /* Sun 4/100 series */
#define SM_4_330 0x03 /* Sun 4/300 series */
#define SM_4_470 0x04 /* Sun 4/400 series */
/* Sun4c machines Full Name - PROM NAME */
#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
/* Sun4m machines, these predate the OpenBoot. These values only mean
* something if the value in the ARCH field is SM_SUN4M, if it is
* SM_SUN4M_OBP then you have the following situation:
* 1) You either have a sun4d, a sun4e, or a recently made sun4m.
* 2) You have to consult OpenBoot to determine which machine this is.
*/
#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
/* Sun4d machines -- N/A */
/* Sun4e machines -- N/A */
/* Sun4u machines -- N/A */
#endif /* !(_SPARC_MACHINES_H) */

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/*
** linux/machw.h -- This header defines some macros and pointers for
** the various Macintosh custom hardware registers.
**
** Copyright 1997 by Michael Schmitz
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _ASM_MACHW_H_
#define _ASM_MACHW_H_
/*
* head.S maps the videomem to VIDEOMEMBASE
*/
#define VIDEOMEMBASE 0xf0000000
#define VIDEOMEMSIZE (4096*1024)
#define VIDEOMEMMASK (-4096*1024)
#endif /* linux/machw.h */

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#ifndef __ASM_MACINTOSH_H
#define __ASM_MACINTOSH_H
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <asm/bootinfo-mac.h>
/*
* Apple Macintoshisms
*/
extern void mac_reset(void);
extern void mac_poweroff(void);
extern void mac_init_IRQ(void);
extern void mac_irq_enable(struct irq_data *data);
extern void mac_irq_disable(struct irq_data *data);
/*
* Macintosh Table
*/
struct mac_model
{
short ident;
char *name;
char adb_type;
char via_type;
char scsi_type;
char ide_type;
char scc_type;
char ether_type;
char nubus_type;
char floppy_type;
};
#define MAC_ADB_NONE 0
#define MAC_ADB_II 1
#define MAC_ADB_IISI 2
#define MAC_ADB_CUDA 3
#define MAC_ADB_PB1 4
#define MAC_ADB_PB2 5
#define MAC_ADB_IOP 6
#define MAC_VIA_II 1
#define MAC_VIA_IICI 2
#define MAC_VIA_QUADRA 3
#define MAC_SCSI_NONE 0
#define MAC_SCSI_OLD 1
#define MAC_SCSI_QUADRA 2
#define MAC_SCSI_QUADRA2 3
#define MAC_SCSI_QUADRA3 4
#define MAC_IDE_NONE 0
#define MAC_IDE_QUADRA 1
#define MAC_IDE_PB 2
#define MAC_IDE_BABOON 3
#define MAC_SCC_II 1
#define MAC_SCC_IOP 2
#define MAC_SCC_QUADRA 3
#define MAC_SCC_PSC 4
#define MAC_ETHER_NONE 0
#define MAC_ETHER_SONIC 1
#define MAC_ETHER_MACE 2
#define MAC_NO_NUBUS 0
#define MAC_NUBUS 1
#define MAC_FLOPPY_IWM 0
#define MAC_FLOPPY_SWIM_ADDR1 1
#define MAC_FLOPPY_SWIM_ADDR2 2
#define MAC_FLOPPY_SWIM_IOP 3
#define MAC_FLOPPY_AV 4
extern struct mac_model *macintosh_config;
/*
* Internal representation of the Mac hardware, filled in from bootinfo
*/
struct mac_booter_data
{
unsigned long videoaddr;
unsigned long videorow;
unsigned long videodepth;
unsigned long dimensions;
unsigned long boottime;
unsigned long gmtbias;
unsigned long videological;
unsigned long sccbase;
unsigned long id;
unsigned long memsize;
unsigned long cpuid;
unsigned long rombase;
};
extern struct mac_booter_data mac_bi_data;
#endif

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/*
** macints.h -- Macintosh Linux interrupt handling structs and prototypes
**
** Copyright 1997 by Michael Schmitz
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
*/
#ifndef _ASM_MACINTS_H_
#define _ASM_MACINTS_H_
#include <asm/irq.h>
/* Setting this prints debugging info for unclaimed interrupts */
#define DEBUG_SPURIOUS
/* Setting this prints debugging info on each autovector interrupt */
/* #define DEBUG_IRQS */
/* Setting this prints debugging info on each Nubus interrupt */
/* #define DEBUG_NUBUS_INT */
/* Setting this prints debugging info on irqs as they enabled and disabled. */
/* #define DEBUG_IRQUSE */
/*
* Base IRQ number for all Mac68K interrupt sources. Each source
* has eight indexes (base -> base+7).
*/
#define VIA1_SOURCE_BASE 8
#define VIA2_SOURCE_BASE 16
#define PSC3_SOURCE_BASE 24
#define PSC4_SOURCE_BASE 32
#define PSC5_SOURCE_BASE 40
#define PSC6_SOURCE_BASE 48
#define NUBUS_SOURCE_BASE 56
#define BABOON_SOURCE_BASE 64
/*
* Maximum IRQ number is BABOON_SOURCE_BASE + 7,
* giving us IRQs up through 71
*/
#define NUM_MAC_SOURCES 72
/*
* clean way to separate IRQ into its source and index
*/
#define IRQ_SRC(irq) (irq >> 3)
#define IRQ_IDX(irq) (irq & 7)
/* VIA1 interrupts */
#define IRQ_VIA1_0 (8) /* one second int. */
#define IRQ_VIA1_1 (9) /* VBlank int. */
#define IRQ_MAC_VBL IRQ_VIA1_1
#define IRQ_VIA1_2 (10) /* ADB SR shifts complete */
#define IRQ_MAC_ADB IRQ_VIA1_2
#define IRQ_MAC_ADB_SR IRQ_VIA1_2
#define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */
#define IRQ_MAC_ADB_SD IRQ_VIA1_3
#define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */
#define IRQ_MAC_ADB_CL IRQ_VIA1_4
#define IRQ_VIA1_5 (13)
#define IRQ_MAC_TIMER_2 IRQ_VIA1_5
#define IRQ_VIA1_6 (14)
#define IRQ_MAC_TIMER_1 IRQ_VIA1_6
#define IRQ_VIA1_7 (15)
/* VIA2/RBV interrupts */
#define IRQ_VIA2_0 (16)
#define IRQ_MAC_SCSIDRQ IRQ_VIA2_0
#define IRQ_VIA2_1 (17)
#define IRQ_MAC_NUBUS IRQ_VIA2_1
#define IRQ_VIA2_2 (18)
#define IRQ_VIA2_3 (19)
#define IRQ_MAC_SCSI IRQ_VIA2_3
#define IRQ_VIA2_4 (20)
#define IRQ_VIA2_5 (21)
#define IRQ_VIA2_6 (22)
#define IRQ_VIA2_7 (23)
/* Level 3 (PSC, AV Macs only) interrupts */
#define IRQ_PSC3_0 (24)
#define IRQ_MAC_MACE IRQ_PSC3_0
#define IRQ_PSC3_1 (25)
#define IRQ_PSC3_2 (26)
#define IRQ_PSC3_3 (27)
/* Level 4 (PSC, AV Macs only) interrupts */
#define IRQ_PSC4_0 (32)
#define IRQ_PSC4_1 (33)
#define IRQ_MAC_SCC_A IRQ_PSC4_1
#define IRQ_PSC4_2 (34)
#define IRQ_MAC_SCC_B IRQ_PSC4_2
#define IRQ_PSC4_3 (35)
#define IRQ_MAC_MACE_DMA IRQ_PSC4_3
/* OSS Level 4 interrupts */
#define IRQ_MAC_SCC (33)
/* Level 5 (PSC, AV Macs only) interrupts */
#define IRQ_PSC5_0 (40)
#define IRQ_PSC5_1 (41)
#define IRQ_PSC5_2 (42)
#define IRQ_PSC5_3 (43)
/* Level 6 (PSC, AV Macs only) interrupts */
#define IRQ_PSC6_0 (48)
#define IRQ_PSC6_1 (49)
#define IRQ_PSC6_2 (50)
#define IRQ_PSC6_3 (51)
/* Nubus interrupts (cascaded to VIA2) */
#define IRQ_NUBUS_9 (56)
#define IRQ_NUBUS_A (57)
#define IRQ_NUBUS_B (58)
#define IRQ_NUBUS_C (59)
#define IRQ_NUBUS_D (60)
#define IRQ_NUBUS_E (61)
#define IRQ_NUBUS_F (62)
/* Baboon interrupts (cascaded to nubus slot $C) */
#define IRQ_BABOON_0 (64)
#define IRQ_BABOON_1 (65)
#define IRQ_BABOON_2 (66)
#define IRQ_BABOON_3 (67)
#define SLOT2IRQ(x) (x + 47)
#define IRQ2SLOT(x) (x - 47)
#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
#endif /* asm/macints.h */

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