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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
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commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
50
arch/m68k/include/asm/mcfclk.h
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arch/m68k/include/asm/mcfclk.h
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/*
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* mcfclk.h -- coldfire specific clock structure
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*/
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#ifndef mcfclk_h
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#define mcfclk_h
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struct clk;
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struct clk_ops {
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void (*enable)(struct clk *);
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void (*disable)(struct clk *);
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};
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struct clk {
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const char *name;
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struct clk_ops *clk_ops;
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unsigned long rate;
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unsigned long enabled;
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u8 slot;
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};
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extern struct clk *mcf_clks[];
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#ifdef MCFPM_PPMCR0
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extern struct clk_ops clk_ops0;
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#ifdef MCFPM_PPMCR1
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extern struct clk_ops clk_ops1;
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#endif /* MCFPM_PPMCR1 */
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#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
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static struct clk __clk_##clk_bank##_##clk_slot = { \
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.name = clk_name, \
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.clk_ops = &clk_ops##clk_bank, \
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.rate = clk_rate, \
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.slot = clk_slot, \
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}
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void __clk_init_enabled(struct clk *);
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void __clk_init_disabled(struct clk *);
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#else
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#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
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static struct clk clk_##clk_ref = { \
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.name = clk_name, \
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.rate = clk_rate, \
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}
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#endif /* MCFPM_PPMCR0 */
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#endif /* mcfclk_h */
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