mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 15:48:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
61
arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
Normal file
61
arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
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@ -0,0 +1,61 @@
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/*
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* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __ASM_BCM47XX_H
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#define __ASM_BCM47XX_H
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#include <linux/ssb/ssb.h>
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#include <linux/bcma/bcma.h>
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#include <linux/bcma/bcma_soc.h>
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enum bcm47xx_bus_type {
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#ifdef CONFIG_BCM47XX_SSB
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BCM47XX_BUS_TYPE_SSB,
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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BCM47XX_BUS_TYPE_BCMA,
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#endif
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};
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union bcm47xx_bus {
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#ifdef CONFIG_BCM47XX_SSB
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struct ssb_bus ssb;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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struct bcma_soc bcma;
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#endif
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};
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extern union bcm47xx_bus bcm47xx_bus;
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extern enum bcm47xx_bus_type bcm47xx_bus_type;
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void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
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bool fallback);
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#ifdef CONFIG_BCM47XX_SSB
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void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
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const char *prefix);
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
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const char *prefix);
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#endif
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void bcm47xx_set_system_type(u16 chip_id);
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#endif /* __ASM_BCM47XX_H */
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122
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
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122
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
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@ -0,0 +1,122 @@
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#ifndef __BCM47XX_BOARD_H
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#define __BCM47XX_BOARD_H
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enum bcm47xx_board {
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BCM47XX_BOARD_ASUS_RTAC66U,
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BCM47XX_BOARD_ASUS_RTN10,
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BCM47XX_BOARD_ASUS_RTN10D,
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BCM47XX_BOARD_ASUS_RTN10U,
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BCM47XX_BOARD_ASUS_RTN12,
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BCM47XX_BOARD_ASUS_RTN12B1,
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BCM47XX_BOARD_ASUS_RTN12C1,
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BCM47XX_BOARD_ASUS_RTN12D1,
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BCM47XX_BOARD_ASUS_RTN12HP,
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BCM47XX_BOARD_ASUS_RTN15U,
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BCM47XX_BOARD_ASUS_RTN16,
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BCM47XX_BOARD_ASUS_RTN53,
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BCM47XX_BOARD_ASUS_RTN66U,
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BCM47XX_BOARD_ASUS_WL300G,
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BCM47XX_BOARD_ASUS_WL320GE,
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BCM47XX_BOARD_ASUS_WL330GE,
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BCM47XX_BOARD_ASUS_WL500G,
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BCM47XX_BOARD_ASUS_WL500GD,
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BCM47XX_BOARD_ASUS_WL500GPV1,
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BCM47XX_BOARD_ASUS_WL500GPV2,
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BCM47XX_BOARD_ASUS_WL500W,
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BCM47XX_BOARD_ASUS_WL520GC,
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BCM47XX_BOARD_ASUS_WL520GU,
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BCM47XX_BOARD_ASUS_WL700GE,
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BCM47XX_BOARD_ASUS_WLHDD,
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BCM47XX_BOARD_BELKIN_F7D3301,
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BCM47XX_BOARD_BELKIN_F7D3302,
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BCM47XX_BOARD_BELKIN_F7D4301,
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BCM47XX_BOARD_BELKIN_F7D4302,
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BCM47XX_BOARD_BELKIN_F7D4401,
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BCM47XX_BOARD_BUFFALO_WBR2_G54,
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BCM47XX_BOARD_BUFFALO_WHR2_A54G54,
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BCM47XX_BOARD_BUFFALO_WHR_G125,
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BCM47XX_BOARD_BUFFALO_WHR_G54S,
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BCM47XX_BOARD_BUFFALO_WHR_HP_G54,
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BCM47XX_BOARD_BUFFALO_WLA2_G54L,
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BCM47XX_BOARD_BUFFALO_WZR_G300N,
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BCM47XX_BOARD_BUFFALO_WZR_RS_G54,
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BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP,
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BCM47XX_BOARD_CISCO_M10V1,
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BCM47XX_BOARD_CISCO_M20V1,
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BCM47XX_BOARD_DELL_TM2300,
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BCM47XX_BOARD_DLINK_DIR130,
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BCM47XX_BOARD_DLINK_DIR330,
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BCM47XX_BOARD_HUAWEI_E970,
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BCM47XX_BOARD_LINKSYS_E900V1,
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BCM47XX_BOARD_LINKSYS_E1000V1,
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BCM47XX_BOARD_LINKSYS_E1000V2,
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BCM47XX_BOARD_LINKSYS_E1000V21,
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BCM47XX_BOARD_LINKSYS_E1200V2,
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BCM47XX_BOARD_LINKSYS_E2000V1,
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BCM47XX_BOARD_LINKSYS_E3000V1,
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BCM47XX_BOARD_LINKSYS_E3200V1,
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BCM47XX_BOARD_LINKSYS_E4200V1,
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BCM47XX_BOARD_LINKSYS_WRT150NV1,
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BCM47XX_BOARD_LINKSYS_WRT150NV11,
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BCM47XX_BOARD_LINKSYS_WRT160NV1,
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BCM47XX_BOARD_LINKSYS_WRT160NV3,
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BCM47XX_BOARD_LINKSYS_WRT300NV11,
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BCM47XX_BOARD_LINKSYS_WRT310NV1,
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BCM47XX_BOARD_LINKSYS_WRT310NV2,
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BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
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BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
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BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
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BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708,
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BCM47XX_BOARD_LINKSYS_WRT610NV1,
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BCM47XX_BOARD_LINKSYS_WRT610NV2,
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BCM47XX_BOARD_LINKSYS_WRTSL54GS,
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BCM47XX_BOARD_MICROSOFT_MN700,
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BCM47XX_BOARD_MOTOROLA_WE800G,
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BCM47XX_BOARD_MOTOROLA_WR850GP,
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BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
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BCM47XX_BOARD_NETGEAR_WGR614V8,
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BCM47XX_BOARD_NETGEAR_WGR614V9,
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BCM47XX_BOARD_NETGEAR_WNDR3300,
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BCM47XX_BOARD_NETGEAR_WNDR3400V1,
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BCM47XX_BOARD_NETGEAR_WNDR3400V2,
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BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
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BCM47XX_BOARD_NETGEAR_WNDR3700V3,
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BCM47XX_BOARD_NETGEAR_WNDR4000,
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BCM47XX_BOARD_NETGEAR_WNDR4500V1,
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BCM47XX_BOARD_NETGEAR_WNDR4500V2,
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BCM47XX_BOARD_NETGEAR_WNR2000,
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BCM47XX_BOARD_NETGEAR_WNR3500L,
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BCM47XX_BOARD_NETGEAR_WNR3500U,
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BCM47XX_BOARD_NETGEAR_WNR3500V2,
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BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
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BCM47XX_BOARD_NETGEAR_WNR834BV2,
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BCM47XX_BOARD_PHICOMM_M1,
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BCM47XX_BOARD_SIEMENS_SE505V2,
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BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE,
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BCM47XX_BOARD_ZTE_H218N,
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BCM47XX_BOARD_UNKNOWN,
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BCM47XX_BOARD_NO,
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};
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#define BCM47XX_BOARD_MAX_NAME 30
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void bcm47xx_board_detect(void);
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enum bcm47xx_board bcm47xx_board_get(void);
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const char *bcm47xx_board_get_name(void);
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#endif /* __BCM47XX_BOARD_H */
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53
arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
Normal file
53
arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
Normal file
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@ -0,0 +1,53 @@
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/*
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* Copyright (C) 2005, Broadcom Corporation
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* Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __BCM47XX_NVRAM_H
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#define __BCM47XX_NVRAM_H
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#include <linux/types.h>
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#include <linux/kernel.h>
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struct nvram_header {
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u32 magic;
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u32 len;
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u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
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u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
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u32 config_ncdl; /* ncdl values for memc */
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};
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#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
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#define NVRAM_VERSION 1
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#define NVRAM_HEADER_SIZE 20
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#define NVRAM_SPACE 0x8000
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#define FLASH_MIN 0x00020000 /* Minimum flash size */
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#define NVRAM_MAX_VALUE_LEN 255
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#define NVRAM_MAX_PARAM_LEN 64
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extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
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static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
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{
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if (strchr(buf, ':'))
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sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
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&macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
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&macaddr[5]);
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else if (strchr(buf, '-'))
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sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
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&macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
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&macaddr[5]);
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else
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printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
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}
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int bcm47xx_nvram_gpio_pin(const char *name);
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#endif /* __BCM47XX_NVRAM_H */
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82
arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
Normal file
82
arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
Normal file
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@ -0,0 +1,82 @@
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#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_fpu 0
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#define cpu_has_32fpr 0
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#define cpu_has_counter 1
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#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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#define cpu_has_watch 1
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#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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#define cpu_has_watch 0
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#endif
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_prefetch 1
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#define cpu_has_mcheck 1
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#define cpu_has_ejtag 1
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#define cpu_has_llsc 1
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/* cpu_has_mips16 */
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_rixi 0
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#define cpu_has_mmips 0
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#define cpu_has_smartmips 0
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#define cpu_has_vtag_icache 0
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/* cpu_has_dc_aliases */
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_pindexed_dcache 0
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#define cpu_icache_snoops_remote_store 0
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#define cpu_has_mips_2 1
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#define cpu_has_mips_3 0
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#define cpu_has_mips32r1 1
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#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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#define cpu_has_mips32r2 1
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#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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#define cpu_has_mips32r2 0
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#endif
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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#define cpu_has_dsp 1
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#define cpu_has_dsp2 1
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#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#endif
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#define cpu_has_mipsmt 0
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/* cpu_has_userlocal */
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#define cpu_has_nofpuex 0
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#define cpu_has_64bits 0
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#define cpu_has_64bit_zero_reg 0
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#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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#define cpu_has_vint 1
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#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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#define cpu_has_vint 0
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#endif
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#define cpu_has_veic 0
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#define cpu_has_inclusive_pcaches 0
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#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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#define cpu_has_perf_cntr_intr_bit 1
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#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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#define cpu_dcache_line_size() 16
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#define cpu_icache_line_size() 16
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#define cpu_has_perf_cntr_intr_bit 0
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#endif
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#define cpu_scache_line_size() 0
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#define cpu_has_vz 0
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|
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#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
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17
arch/mips/include/asm/mach-bcm47xx/gpio.h
Normal file
17
arch/mips/include/asm/mach-bcm47xx/gpio.h
Normal file
|
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@ -0,0 +1,17 @@
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#ifndef __ASM_MIPS_MACH_BCM47XX_GPIO_H
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#define __ASM_MIPS_MACH_BCM47XX_GPIO_H
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#include <asm-generic/gpio.h>
|
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|
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#define gpio_get_value __gpio_get_value
|
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#define gpio_set_value __gpio_set_value
|
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#define gpio_cansleep __gpio_cansleep
|
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#define gpio_to_irq __gpio_to_irq
|
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|
||||
static inline int irq_to_gpio(unsigned int irq)
|
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{
|
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return -EINVAL;
|
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}
|
||||
|
||||
#endif
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24
arch/mips/include/asm/mach-bcm47xx/war.h
Normal file
24
arch/mips/include/asm/mach-bcm47xx/war.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
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#ifndef __ASM_MIPS_MACH_BCM47XX_WAR_H
|
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#define __ASM_MIPS_MACH_BCM47XX_WAR_H
|
||||
|
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
||||
#define R4600_V1_HIT_CACHEOP_WAR 0
|
||||
#define R4600_V2_HIT_CACHEOP_WAR 0
|
||||
#define R5432_CP0_INTERRUPT_WAR 0
|
||||
#define BCM1250_M3_WAR 0
|
||||
#define SIBYTE_1956_WAR 0
|
||||
#define MIPS4K_ICACHE_REFILL_WAR 0
|
||||
#define MIPS_CACHE_SYNC_WAR 0
|
||||
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
||||
#define R10000_LLSC_WAR 0
|
||||
#define MIPS34K_MISSED_ITLB_WAR 0
|
||||
|
||||
#endif /* __ASM_MIPS_MACH_BCM47XX_WAR_H */
|
||||
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