mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 17:02:46 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
18
arch/mips/include/asm/mach-lantiq/xway/irq.h
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18
arch/mips/include/asm/mach-lantiq/xway/irq.h
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef __LANTIQ_IRQ_H
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#define __LANTIQ_IRQ_H
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#include <lantiq_irq.h>
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#define NR_IRQS 256
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#include_next <irq.h>
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#endif
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26
arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LANTIQ_XWAY_IRQ_H__
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#define _LANTIQ_XWAY_IRQ_H__
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#define INT_NUM_IRQ0 8
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#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
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#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
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#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
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#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
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#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
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#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
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#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define MIPS_CPU_TIMER_IRQ 7
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#define MAX_IM 5
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#endif
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94
arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LTQ_XWAY_H__
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#define _LTQ_XWAY_H__
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#ifdef CONFIG_SOC_TYPE_XWAY
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#include <lantiq.h>
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/* Chip IDs */
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#define SOC_ID_DANUBE1 0x129
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#define SOC_ID_DANUBE2 0x12B
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#define SOC_ID_TWINPASS 0x12D
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#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
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#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
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#define SOC_ID_ARX188 0x16C
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#define SOC_ID_ARX168_1 0x16D
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#define SOC_ID_ARX168_2 0x16E
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#define SOC_ID_ARX182 0x16F
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#define SOC_ID_GRX188 0x170
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#define SOC_ID_GRX168 0x171
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#define SOC_ID_VRX288 0x1C0 /* v1.1 */
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#define SOC_ID_VRX282 0x1C1 /* v1.1 */
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#define SOC_ID_VRX268 0x1C2 /* v1.1 */
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#define SOC_ID_GRX268 0x1C8 /* v1.1 */
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#define SOC_ID_GRX288 0x1C9 /* v1.1 */
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#define SOC_ID_VRX288_2 0x00B /* v1.2 */
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#define SOC_ID_VRX268_2 0x00C /* v1.2 */
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#define SOC_ID_GRX288_2 0x00D /* v1.2 */
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#define SOC_ID_GRX282_2 0x00E /* v1.2 */
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/* SoC Types */
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#define SOC_TYPE_DANUBE 0x01
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#define SOC_TYPE_TWINPASS 0x02
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#define SOC_TYPE_AR9 0x03
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#define SOC_TYPE_VR9 0x04 /* v1.1 */
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#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
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#define SOC_TYPE_AMAZON_SE 0x06
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/* BOOT_SEL - find what boot media we have */
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#define BS_EXT_ROM 0x0
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#define BS_FLASH 0x1
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#define BS_MII0 0x2
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#define BS_PCI 0x3
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#define BS_UART1 0x4
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#define BS_SPI 0x5
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#define BS_NAND 0x6
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#define BS_RMII0 0x7
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/* helpers used to access the cgu */
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#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
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#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
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extern __iomem void *ltq_cgu_membase;
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/*
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* during early_printk no ioremap is possible
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* lets use KSEG1 instead
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*/
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#define LTQ_ASC1_BASE_ADDR 0x1E100C00
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#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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/* EBU - external bus unit */
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#define LTQ_EBU_BUSCON0 0x0060
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#define LTQ_EBU_PCC_CON 0x0090
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#define LTQ_EBU_PCC_IEN 0x00A4
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#define LTQ_EBU_PCC_ISTAT 0x00A0
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#define LTQ_EBU_BUSCON1 0x0064
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#define LTQ_EBU_ADDRSEL1 0x0024
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#define EBU_WRDIS 0x80000000
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/* WDT */
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#define LTQ_RST_CAUSE_WDTRST 0x20
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/* MPS - multi processor unit (voice) */
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#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
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/* allow booting xrx200 phys */
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int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
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/* request a non-gpio and set the PIO config */
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#define PMU_PPE BIT(13)
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extern void ltq_pmu_enable(unsigned int module);
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extern void ltq_pmu_disable(unsigned int module);
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#endif /* CONFIG_SOC_TYPE_XWAY */
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#endif /* _LTQ_XWAY_H__ */
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60
arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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60
arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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*/
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#ifndef LTQ_DMA_H__
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#define LTQ_DMA_H__
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#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */
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#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */
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#define LTQ_DMA_OWN BIT(31) /* owner bit */
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#define LTQ_DMA_C BIT(30) /* complete bit */
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#define LTQ_DMA_SOP BIT(29) /* start of packet */
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#define LTQ_DMA_EOP BIT(28) /* end of packet */
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#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */
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#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */
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#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */
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struct ltq_dma_desc {
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u32 ctl;
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u32 addr;
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};
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struct ltq_dma_channel {
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int nr; /* the channel number */
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int irq; /* the mapped irq */
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int desc; /* the current descriptor */
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struct ltq_dma_desc *desc_base; /* the descriptor base */
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int phys; /* physical addr */
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};
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enum {
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DMA_PORT_ETOP = 0,
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DMA_PORT_DEU,
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};
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extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
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extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
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extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
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extern void ltq_dma_open(struct ltq_dma_channel *ch);
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extern void ltq_dma_close(struct ltq_dma_channel *ch);
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extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
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extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
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extern void ltq_dma_free(struct ltq_dma_channel *ch);
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extern void ltq_dma_init_port(int p);
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#endif
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