mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 15:48:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
186
arch/mips/include/asm/netlogic/xlp-hal/bridge.h
Normal file
186
arch/mips/include/asm/netlogic/xlp-hal/bridge.h
Normal file
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@ -0,0 +1,186 @@
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|||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __NLM_HAL_BRIDGE_H__
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#define __NLM_HAL_BRIDGE_H__
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/**
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* @file_name mio.h
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* @author Netlogic Microsystems
|
||||
* @brief Basic definitions of XLP memory and io subsystem
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*/
|
||||
|
||||
/*
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* BRIDGE specific registers
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*
|
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* These registers start after the PCIe header, which has 0x40
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* standard entries
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*/
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#define BRIDGE_MODE 0x00
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#define BRIDGE_PCI_CFG_BASE 0x01
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#define BRIDGE_PCI_CFG_LIMIT 0x02
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#define BRIDGE_PCIE_CFG_BASE 0x03
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#define BRIDGE_PCIE_CFG_LIMIT 0x04
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#define BRIDGE_BUSNUM_BAR0 0x05
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#define BRIDGE_BUSNUM_BAR1 0x06
|
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#define BRIDGE_BUSNUM_BAR2 0x07
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||||
#define BRIDGE_BUSNUM_BAR3 0x08
|
||||
#define BRIDGE_BUSNUM_BAR4 0x09
|
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#define BRIDGE_BUSNUM_BAR5 0x0a
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#define BRIDGE_BUSNUM_BAR6 0x0b
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#define BRIDGE_FLASH_BAR0 0x0c
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#define BRIDGE_FLASH_BAR1 0x0d
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#define BRIDGE_FLASH_BAR2 0x0e
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#define BRIDGE_FLASH_BAR3 0x0f
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#define BRIDGE_FLASH_LIMIT0 0x10
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#define BRIDGE_FLASH_LIMIT1 0x11
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#define BRIDGE_FLASH_LIMIT2 0x12
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#define BRIDGE_FLASH_LIMIT3 0x13
|
||||
|
||||
#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
|
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#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
|
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#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
|
||||
#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
|
||||
|
||||
#define BRIDGE_PCIEMEM_BASE0 0x34
|
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#define BRIDGE_PCIEMEM_BASE1 0x35
|
||||
#define BRIDGE_PCIEMEM_BASE2 0x36
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||||
#define BRIDGE_PCIEMEM_BASE3 0x37
|
||||
#define BRIDGE_PCIEMEM_LIMIT0 0x38
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#define BRIDGE_PCIEMEM_LIMIT1 0x39
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#define BRIDGE_PCIEMEM_LIMIT2 0x3a
|
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#define BRIDGE_PCIEMEM_LIMIT3 0x3b
|
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#define BRIDGE_PCIEIO_BASE0 0x3c
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#define BRIDGE_PCIEIO_BASE1 0x3d
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#define BRIDGE_PCIEIO_BASE2 0x3e
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#define BRIDGE_PCIEIO_BASE3 0x3f
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#define BRIDGE_PCIEIO_LIMIT0 0x40
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#define BRIDGE_PCIEIO_LIMIT1 0x41
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#define BRIDGE_PCIEIO_LIMIT2 0x42
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#define BRIDGE_PCIEIO_LIMIT3 0x43
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#define BRIDGE_PCIEMEM_BASE4 0x44
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#define BRIDGE_PCIEMEM_BASE5 0x45
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#define BRIDGE_PCIEMEM_BASE6 0x46
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#define BRIDGE_PCIEMEM_LIMIT4 0x47
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#define BRIDGE_PCIEMEM_LIMIT5 0x48
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#define BRIDGE_PCIEMEM_LIMIT6 0x49
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#define BRIDGE_PCIEIO_BASE4 0x4a
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#define BRIDGE_PCIEIO_BASE5 0x4b
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#define BRIDGE_PCIEIO_BASE6 0x4c
|
||||
#define BRIDGE_PCIEIO_LIMIT4 0x4d
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||||
#define BRIDGE_PCIEIO_LIMIT5 0x4e
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||||
#define BRIDGE_PCIEIO_LIMIT6 0x4f
|
||||
#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
|
||||
#define BRIDGE_EVNTCTR1_LOW 0x51
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||||
#define BRIDGE_EVNTCTR1_HI 0x52
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||||
#define BRIDGE_EVNT_CNT_CTL2 0x53
|
||||
#define BRIDGE_EVNTCTR2_LOW 0x54
|
||||
#define BRIDGE_EVNTCTR2_HI 0x55
|
||||
#define BRIDGE_TRACEBUF_MATCH0 0x56
|
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#define BRIDGE_TRACEBUF_MATCH1 0x57
|
||||
#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
|
||||
#define BRIDGE_TRACEBUF_MATCH_HI 0x59
|
||||
#define BRIDGE_TRACEBUF_CTRL 0x5a
|
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#define BRIDGE_TRACEBUF_INIT 0x5b
|
||||
#define BRIDGE_TRACEBUF_ACCESS 0x5c
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||||
#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
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#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
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||||
#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
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#define BRIDGE_TRACEBUF_READ_DATA3 0x60
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#define BRIDGE_TRACEBUF_STATUS 0x61
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#define BRIDGE_ADDRESS_ERROR0 0x62
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#define BRIDGE_ADDRESS_ERROR1 0x63
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||||
#define BRIDGE_ADDRESS_ERROR2 0x64
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#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
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#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
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#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
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#define BRIDGE_LINE_FLUSH0 0x68
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||||
#define BRIDGE_LINE_FLUSH1 0x69
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#define BRIDGE_NODE_ID 0x6a
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#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
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#define BRIDGE_PCIE0_WEIGHT 0x2c0
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#define BRIDGE_PCIE1_WEIGHT 0x2c1
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#define BRIDGE_PCIE2_WEIGHT 0x2c2
|
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#define BRIDGE_PCIE3_WEIGHT 0x2c3
|
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#define BRIDGE_USB_WEIGHT 0x2c4
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#define BRIDGE_NET_WEIGHT 0x2c5
|
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#define BRIDGE_POE_WEIGHT 0x2c6
|
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#define BRIDGE_CMS_WEIGHT 0x2c7
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#define BRIDGE_DMAENG_WEIGHT 0x2c8
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#define BRIDGE_SEC_WEIGHT 0x2c9
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#define BRIDGE_COMP_WEIGHT 0x2ca
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#define BRIDGE_GIO_WEIGHT 0x2cb
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#define BRIDGE_FLASH_WEIGHT 0x2cc
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||||
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/* FIXME verify */
|
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#define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i))
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#define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i))
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#define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i))
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||||
#define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i))
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#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
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#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
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#define BRIDGE_9XX_ADDRESS_ERROR0 0x9d
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#define BRIDGE_9XX_ADDRESS_ERROR1 0x9e
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#define BRIDGE_9XX_ADDRESS_ERROR2 0x9f
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||||
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#define BRIDGE_9XX_PCIEMEM_BASE0 0x59
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#define BRIDGE_9XX_PCIEMEM_BASE1 0x5a
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#define BRIDGE_9XX_PCIEMEM_BASE2 0x5b
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#define BRIDGE_9XX_PCIEMEM_BASE3 0x5c
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#define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d
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#define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e
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#define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f
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#define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60
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#define BRIDGE_9XX_PCIEIO_BASE0 0x61
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||||
#define BRIDGE_9XX_PCIEIO_BASE1 0x62
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#define BRIDGE_9XX_PCIEIO_BASE2 0x63
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#define BRIDGE_9XX_PCIEIO_BASE3 0x64
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#define BRIDGE_9XX_PCIEIO_LIMIT0 0x65
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#define BRIDGE_9XX_PCIEIO_LIMIT1 0x66
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#define BRIDGE_9XX_PCIEIO_LIMIT2 0x67
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#define BRIDGE_9XX_PCIEIO_LIMIT3 0x68
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#ifndef __ASSEMBLY__
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#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
|
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#define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
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XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
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#define nlm_get_bridge_regbase(node) \
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(nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
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#endif /* __ASSEMBLY__ */
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#endif /* __NLM_HAL_BRIDGE_H__ */
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87
arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
Normal file
87
arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
Normal file
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@ -0,0 +1,87 @@
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|||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __NLM_HAL_CPUCONTROL_H__
|
||||
#define __NLM_HAL_CPUCONTROL_H__
|
||||
|
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#define CPU_BLOCKID_IFU 0
|
||||
#define CPU_BLOCKID_ICU 1
|
||||
#define CPU_BLOCKID_IEU 2
|
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#define CPU_BLOCKID_LSU 3
|
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#define CPU_BLOCKID_MMU 4
|
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#define CPU_BLOCKID_PRF 5
|
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#define CPU_BLOCKID_SCH 7
|
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#define CPU_BLOCKID_SCU 8
|
||||
#define CPU_BLOCKID_FPU 9
|
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#define CPU_BLOCKID_MAP 10
|
||||
|
||||
#define ICU_DEFEATURE 0x100
|
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|
||||
#define LSU_DEFEATURE 0x304
|
||||
#define LSU_DEBUG_ADDR 0x305
|
||||
#define LSU_DEBUG_DATA0 0x306
|
||||
#define LSU_CERRLOG_REGID 0x309
|
||||
#define SCHED_DEFEATURE 0x700
|
||||
|
||||
/* Offsets of interest from the 'MAP' Block */
|
||||
#define MAP_THREADMODE 0x00
|
||||
#define MAP_EXT_EBASE_ENABLE 0x04
|
||||
#define MAP_CCDI_CONFIG 0x08
|
||||
#define MAP_THRD0_CCDI_STATUS 0x0c
|
||||
#define MAP_THRD1_CCDI_STATUS 0x10
|
||||
#define MAP_THRD2_CCDI_STATUS 0x14
|
||||
#define MAP_THRD3_CCDI_STATUS 0x18
|
||||
#define MAP_THRD0_DEBUG_MODE 0x1c
|
||||
#define MAP_THRD1_DEBUG_MODE 0x20
|
||||
#define MAP_THRD2_DEBUG_MODE 0x24
|
||||
#define MAP_THRD3_DEBUG_MODE 0x28
|
||||
#define MAP_MISC_STATE 0x60
|
||||
#define MAP_DEBUG_READ_CTL 0x64
|
||||
#define MAP_DEBUG_READ_REG0 0x68
|
||||
#define MAP_DEBUG_READ_REG1 0x6c
|
||||
|
||||
#define MMU_SETUP 0x400
|
||||
#define MMU_LFSRSEED 0x401
|
||||
#define MMU_HPW_NUM_PAGE_LVL 0x410
|
||||
#define MMU_PGWKR_PGDBASE 0x411
|
||||
#define MMU_PGWKR_PGDSHFT 0x412
|
||||
#define MMU_PGWKR_PGDMASK 0x413
|
||||
#define MMU_PGWKR_PUDSHFT 0x414
|
||||
#define MMU_PGWKR_PUDMASK 0x415
|
||||
#define MMU_PGWKR_PMDSHFT 0x416
|
||||
#define MMU_PGWKR_PMDMASK 0x417
|
||||
#define MMU_PGWKR_PTESHFT 0x418
|
||||
#define MMU_PGWKR_PTEMASK 0x419
|
||||
|
||||
#endif /* __NLM_CPUCONTROL_H__ */
|
||||
214
arch/mips/include/asm/netlogic/xlp-hal/iomap.h
Normal file
214
arch/mips/include/asm/netlogic/xlp-hal/iomap.h
Normal file
|
|
@ -0,0 +1,214 @@
|
|||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __NLM_HAL_IOMAP_H__
|
||||
#define __NLM_HAL_IOMAP_H__
|
||||
|
||||
#define XLP_DEFAULT_IO_BASE 0x18000000
|
||||
#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
|
||||
#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000
|
||||
|
||||
#define NMI_BASE 0xbfc00000
|
||||
#define XLP_IO_CLK 133333333
|
||||
|
||||
#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
|
||||
#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
|
||||
#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
|
||||
#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
|
||||
#define XLP_IO_PCI_HDRSZ 0x100
|
||||
#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
|
||||
#define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12))
|
||||
|
||||
#define XLP_HDR_OFFSET(node, bus, dev, fn) \
|
||||
XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
|
||||
|
||||
#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
|
||||
/* coherent inter chip */
|
||||
#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
|
||||
#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
|
||||
#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
|
||||
#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
|
||||
|
||||
#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
|
||||
#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
|
||||
#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
|
||||
#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
|
||||
#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
|
||||
|
||||
#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
|
||||
#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
|
||||
#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
|
||||
#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
|
||||
#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
|
||||
#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
|
||||
#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
|
||||
|
||||
#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2)
|
||||
|
||||
/* XLP2xx has an updated USB block */
|
||||
#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i)
|
||||
#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1)
|
||||
#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2)
|
||||
#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3)
|
||||
|
||||
#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
|
||||
#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
|
||||
|
||||
#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
|
||||
|
||||
#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
|
||||
#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
|
||||
#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
|
||||
|
||||
#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
|
||||
#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
|
||||
#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
|
||||
#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
|
||||
#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
|
||||
#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
|
||||
#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
|
||||
/* on 2XX, all I2C busses are on the same block */
|
||||
#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7)
|
||||
|
||||
/* system management */
|
||||
#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
|
||||
#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
|
||||
|
||||
/* Flash */
|
||||
#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
|
||||
#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
|
||||
#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
|
||||
#define XLP_IO_MMC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
|
||||
|
||||
/* Things have changed drastically in XLP 9XX */
|
||||
#define XLP9XX_HDR_OFFSET(n, d, f) \
|
||||
XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
|
||||
|
||||
#define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node)
|
||||
#define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0)
|
||||
#define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2)
|
||||
#define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0)
|
||||
#define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1)
|
||||
#define XLP9XX_IO_CLOCK_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 2)
|
||||
#define XLP9XX_IO_POWER_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 3)
|
||||
#define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4)
|
||||
|
||||
#define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i)
|
||||
#define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0)
|
||||
#define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2)
|
||||
#define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3)
|
||||
|
||||
/* XLP9xx USB block */
|
||||
#define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i)
|
||||
#define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1)
|
||||
#define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2)
|
||||
|
||||
/* XLP9XX on-chip SATA controller */
|
||||
#define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2)
|
||||
|
||||
/* Flash */
|
||||
#define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0)
|
||||
#define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1)
|
||||
#define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2)
|
||||
#define XLP9XX_IO_MMC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3)
|
||||
|
||||
/* PCI config header register id's */
|
||||
#define XLP_PCI_CFGREG0 0x00
|
||||
#define XLP_PCI_CFGREG1 0x01
|
||||
#define XLP_PCI_CFGREG2 0x02
|
||||
#define XLP_PCI_CFGREG3 0x03
|
||||
#define XLP_PCI_CFGREG4 0x04
|
||||
#define XLP_PCI_CFGREG5 0x05
|
||||
#define XLP_PCI_DEVINFO_REG0 0x30
|
||||
#define XLP_PCI_DEVINFO_REG1 0x31
|
||||
#define XLP_PCI_DEVINFO_REG2 0x32
|
||||
#define XLP_PCI_DEVINFO_REG3 0x33
|
||||
#define XLP_PCI_DEVINFO_REG4 0x34
|
||||
#define XLP_PCI_DEVINFO_REG5 0x35
|
||||
#define XLP_PCI_DEVINFO_REG6 0x36
|
||||
#define XLP_PCI_DEVINFO_REG7 0x37
|
||||
#define XLP_PCI_DEVSCRATCH_REG0 0x38
|
||||
#define XLP_PCI_DEVSCRATCH_REG1 0x39
|
||||
#define XLP_PCI_DEVSCRATCH_REG2 0x3a
|
||||
#define XLP_PCI_DEVSCRATCH_REG3 0x3b
|
||||
#define XLP_PCI_MSGSTN_REG 0x3c
|
||||
#define XLP_PCI_IRTINFO_REG 0x3d
|
||||
#define XLP_PCI_UCODEINFO_REG 0x3e
|
||||
#define XLP_PCI_SBB_WT_REG 0x3f
|
||||
|
||||
/* PCI IDs for SoC device */
|
||||
#define PCI_VENDOR_NETLOGIC 0x184e
|
||||
|
||||
#define PCI_DEVICE_ID_NLM_ROOT 0x1001
|
||||
#define PCI_DEVICE_ID_NLM_ICI 0x1002
|
||||
#define PCI_DEVICE_ID_NLM_PIC 0x1003
|
||||
#define PCI_DEVICE_ID_NLM_PCIE 0x1004
|
||||
#define PCI_DEVICE_ID_NLM_EHCI 0x1007
|
||||
#define PCI_DEVICE_ID_NLM_OHCI 0x1008
|
||||
#define PCI_DEVICE_ID_NLM_NAE 0x1009
|
||||
#define PCI_DEVICE_ID_NLM_POE 0x100A
|
||||
#define PCI_DEVICE_ID_NLM_FMN 0x100B
|
||||
#define PCI_DEVICE_ID_NLM_RAID 0x100D
|
||||
#define PCI_DEVICE_ID_NLM_SAE 0x100D
|
||||
#define PCI_DEVICE_ID_NLM_RSA 0x100E
|
||||
#define PCI_DEVICE_ID_NLM_CMP 0x100F
|
||||
#define PCI_DEVICE_ID_NLM_UART 0x1010
|
||||
#define PCI_DEVICE_ID_NLM_I2C 0x1011
|
||||
#define PCI_DEVICE_ID_NLM_NOR 0x1015
|
||||
#define PCI_DEVICE_ID_NLM_NAND 0x1016
|
||||
#define PCI_DEVICE_ID_NLM_MMC 0x1018
|
||||
#define PCI_DEVICE_ID_NLM_SATA 0x101A
|
||||
#define PCI_DEVICE_ID_NLM_XHCI 0x101D
|
||||
|
||||
#define PCI_DEVICE_ID_XLP9XX_MMC 0x9018
|
||||
#define PCI_DEVICE_ID_XLP9XX_SATA 0x901A
|
||||
#define PCI_DEVICE_ID_XLP9XX_XHCI 0x901D
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
|
||||
#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
|
||||
|
||||
static inline int xlp9xx_get_socbus(int node)
|
||||
{
|
||||
uint64_t socbridge;
|
||||
|
||||
if (node == 0)
|
||||
return 1;
|
||||
socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
|
||||
return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
|
||||
}
|
||||
#endif /* !__ASSEMBLY */
|
||||
|
||||
#endif /* __NLM_HAL_IOMAP_H__ */
|
||||
113
arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
Normal file
113
arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright (c) 2003-2012 Broadcom Corporation
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the Broadcom
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __NLM_HAL_PCIBUS_H__
|
||||
#define __NLM_HAL_PCIBUS_H__
|
||||
|
||||
/* PCIE Memory and IO regions */
|
||||
#define PCIE_MEM_BASE 0xd0000000ULL
|
||||
#define PCIE_MEM_LIMIT 0xdfffffffULL
|
||||
#define PCIE_IO_BASE 0x14000000ULL
|
||||
#define PCIE_IO_LIMIT 0x15ffffffULL
|
||||
|
||||
#define PCIE_BRIDGE_CMD 0x1
|
||||
#define PCIE_BRIDGE_MSI_CAP 0x14
|
||||
#define PCIE_BRIDGE_MSI_ADDRL 0x15
|
||||
#define PCIE_BRIDGE_MSI_ADDRH 0x16
|
||||
#define PCIE_BRIDGE_MSI_DATA 0x17
|
||||
|
||||
/* XLP Global PCIE configuration space registers */
|
||||
#define PCIE_BYTE_SWAP_MEM_BASE 0x247
|
||||
#define PCIE_BYTE_SWAP_MEM_LIM 0x248
|
||||
#define PCIE_BYTE_SWAP_IO_BASE 0x249
|
||||
#define PCIE_BYTE_SWAP_IO_LIM 0x24A
|
||||
|
||||
#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F
|
||||
#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250
|
||||
#define PCIE_MSI_STATUS 0x25A
|
||||
#define PCIE_MSI_EN 0x25B
|
||||
#define PCIE_MSIX_STATUS 0x25D
|
||||
#define PCIE_INT_STATUS0 0x25F
|
||||
#define PCIE_INT_STATUS1 0x260
|
||||
#define PCIE_INT_EN0 0x261
|
||||
#define PCIE_INT_EN1 0x262
|
||||
|
||||
/* XLP9XX has basic changes */
|
||||
#define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c
|
||||
#define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d
|
||||
#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e
|
||||
#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f
|
||||
|
||||
#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE 0x264
|
||||
#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265
|
||||
#define PCIE_9XX_MSI_STATUS 0x283
|
||||
#define PCIE_9XX_MSI_EN 0x284
|
||||
/* 128 MSIX vectors available in 9xx */
|
||||
#define PCIE_9XX_MSIX_STATUS0 0x286
|
||||
#define PCIE_9XX_MSIX_STATUSX(n) (n + 0x286)
|
||||
#define PCIE_9XX_MSIX_VEC 0x296
|
||||
#define PCIE_9XX_MSIX_VECX(n) (n + 0x296)
|
||||
#define PCIE_9XX_INT_STATUS0 0x397
|
||||
#define PCIE_9XX_INT_STATUS1 0x398
|
||||
#define PCIE_9XX_INT_EN0 0x399
|
||||
#define PCIE_9XX_INT_EN1 0x39a
|
||||
|
||||
/* other */
|
||||
#define PCIE_NLINKS 4
|
||||
|
||||
/* MSI addresses */
|
||||
#define MSI_ADDR_BASE 0xfffee00000ULL
|
||||
#define MSI_ADDR_SZ 0x10000
|
||||
#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \
|
||||
(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
|
||||
#define MSIX_ADDR_BASE 0xfffef00000ULL
|
||||
#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \
|
||||
(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
|
||||
#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
|
||||
#define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
|
||||
XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
void xlp_init_node_msi_irqs(int node, int link);
|
||||
#else
|
||||
static inline void xlp_init_node_msi_irqs(int node, int link) {}
|
||||
#endif
|
||||
|
||||
struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
|
||||
|
||||
#endif
|
||||
#endif /* __NLM_HAL_PCIBUS_H__ */
|
||||
366
arch/mips/include/asm/netlogic/xlp-hal/pic.h
Normal file
366
arch/mips/include/asm/netlogic/xlp-hal/pic.h
Normal file
|
|
@ -0,0 +1,366 @@
|
|||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _NLM_HAL_PIC_H
|
||||
#define _NLM_HAL_PIC_H
|
||||
|
||||
/* PIC Specific registers */
|
||||
#define PIC_CTRL 0x00
|
||||
|
||||
/* PIC control register defines */
|
||||
#define PIC_CTRL_ITV 32 /* interrupt timeout value */
|
||||
#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
|
||||
#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
|
||||
#define PIC_CTRL_STE 10 /* system timer interrupt enable */
|
||||
#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
|
||||
#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
|
||||
#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
|
||||
#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
|
||||
#define PIC_CTRL_WTE 0 /* watchdog timer enable */
|
||||
|
||||
/* PIC Status register defines */
|
||||
#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
|
||||
#define PIC_ITE_STATUS 32 /* interrupt timeout status */
|
||||
#define PIC_STS_STATUS 4 /* System timer interrupt status */
|
||||
#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
|
||||
#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
|
||||
|
||||
/* PIC IPI control register offsets */
|
||||
#define PIC_IPICTRL_NMI 32
|
||||
#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
|
||||
#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
|
||||
#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
|
||||
|
||||
/* PIC IRT register offsets */
|
||||
#define PIC_IRT_ENABLE 31
|
||||
#define PIC_IRT_NMI 29
|
||||
#define PIC_IRT_SCH 28 /* Scheduling scheme */
|
||||
#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
|
||||
#define PIC_IRT_DT 19 /* Destination type */
|
||||
#define PIC_IRT_DB 16 /* Destination base */
|
||||
#define PIC_IRT_DTE 0 /* Destination thread enables */
|
||||
|
||||
#define PIC_BYTESWAP 0x02
|
||||
#define PIC_STATUS 0x04
|
||||
#define PIC_INTR_TIMEOUT 0x06
|
||||
#define PIC_ICI0_INTR_TIMEOUT 0x08
|
||||
#define PIC_ICI1_INTR_TIMEOUT 0x0a
|
||||
#define PIC_ICI2_INTR_TIMEOUT 0x0c
|
||||
#define PIC_IPI_CTL 0x0e
|
||||
#define PIC_INT_ACK 0x10
|
||||
#define PIC_INT_PENDING0 0x12
|
||||
#define PIC_INT_PENDING1 0x14
|
||||
#define PIC_INT_PENDING2 0x16
|
||||
|
||||
#define PIC_WDOG0_MAXVAL 0x18
|
||||
#define PIC_WDOG0_COUNT 0x1a
|
||||
#define PIC_WDOG0_ENABLE0 0x1c
|
||||
#define PIC_WDOG0_ENABLE1 0x1e
|
||||
#define PIC_WDOG0_BEATCMD 0x20
|
||||
#define PIC_WDOG0_BEAT0 0x22
|
||||
#define PIC_WDOG0_BEAT1 0x24
|
||||
|
||||
#define PIC_WDOG1_MAXVAL 0x26
|
||||
#define PIC_WDOG1_COUNT 0x28
|
||||
#define PIC_WDOG1_ENABLE0 0x2a
|
||||
#define PIC_WDOG1_ENABLE1 0x2c
|
||||
#define PIC_WDOG1_BEATCMD 0x2e
|
||||
#define PIC_WDOG1_BEAT0 0x30
|
||||
#define PIC_WDOG1_BEAT1 0x32
|
||||
|
||||
#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
|
||||
#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
|
||||
#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
|
||||
#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
|
||||
#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
|
||||
#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
|
||||
#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
|
||||
|
||||
#define PIC_TIMER0_MAXVAL 0x34
|
||||
#define PIC_TIMER1_MAXVAL 0x36
|
||||
#define PIC_TIMER2_MAXVAL 0x38
|
||||
#define PIC_TIMER3_MAXVAL 0x3a
|
||||
#define PIC_TIMER4_MAXVAL 0x3c
|
||||
#define PIC_TIMER5_MAXVAL 0x3e
|
||||
#define PIC_TIMER6_MAXVAL 0x40
|
||||
#define PIC_TIMER7_MAXVAL 0x42
|
||||
#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
|
||||
|
||||
#define PIC_TIMER0_COUNT 0x44
|
||||
#define PIC_TIMER1_COUNT 0x46
|
||||
#define PIC_TIMER2_COUNT 0x48
|
||||
#define PIC_TIMER3_COUNT 0x4a
|
||||
#define PIC_TIMER4_COUNT 0x4c
|
||||
#define PIC_TIMER5_COUNT 0x4e
|
||||
#define PIC_TIMER6_COUNT 0x50
|
||||
#define PIC_TIMER7_COUNT 0x52
|
||||
#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
|
||||
|
||||
#define PIC_ITE0_N0_N1 0x54
|
||||
#define PIC_ITE1_N0_N1 0x58
|
||||
#define PIC_ITE2_N0_N1 0x5c
|
||||
#define PIC_ITE3_N0_N1 0x60
|
||||
#define PIC_ITE4_N0_N1 0x64
|
||||
#define PIC_ITE5_N0_N1 0x68
|
||||
#define PIC_ITE6_N0_N1 0x6c
|
||||
#define PIC_ITE7_N0_N1 0x70
|
||||
#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
|
||||
|
||||
#define PIC_ITE0_N2_N3 0x56
|
||||
#define PIC_ITE1_N2_N3 0x5a
|
||||
#define PIC_ITE2_N2_N3 0x5e
|
||||
#define PIC_ITE3_N2_N3 0x62
|
||||
#define PIC_ITE4_N2_N3 0x66
|
||||
#define PIC_ITE5_N2_N3 0x6a
|
||||
#define PIC_ITE6_N2_N3 0x6e
|
||||
#define PIC_ITE7_N2_N3 0x72
|
||||
#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
|
||||
|
||||
#define PIC_IRT0 0x74
|
||||
#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
|
||||
|
||||
#define PIC_9XX_PENDING_0 0x6
|
||||
#define PIC_9XX_PENDING_1 0x8
|
||||
#define PIC_9XX_PENDING_2 0xa
|
||||
#define PIC_9XX_PENDING_3 0xc
|
||||
|
||||
#define PIC_9XX_IRT0 0x1c0
|
||||
#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2))
|
||||
|
||||
/*
|
||||
* IRT Map
|
||||
*/
|
||||
#define PIC_NUM_IRTS 160
|
||||
#define PIC_9XX_NUM_IRTS 256
|
||||
|
||||
#define PIC_IRT_WD_0_INDEX 0
|
||||
#define PIC_IRT_WD_1_INDEX 1
|
||||
#define PIC_IRT_WD_NMI_0_INDEX 2
|
||||
#define PIC_IRT_WD_NMI_1_INDEX 3
|
||||
#define PIC_IRT_TIMER_0_INDEX 4
|
||||
#define PIC_IRT_TIMER_1_INDEX 5
|
||||
#define PIC_IRT_TIMER_2_INDEX 6
|
||||
#define PIC_IRT_TIMER_3_INDEX 7
|
||||
#define PIC_IRT_TIMER_4_INDEX 8
|
||||
#define PIC_IRT_TIMER_5_INDEX 9
|
||||
#define PIC_IRT_TIMER_6_INDEX 10
|
||||
#define PIC_IRT_TIMER_7_INDEX 11
|
||||
#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
|
||||
#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
|
||||
|
||||
|
||||
/* 11 and 12 */
|
||||
#define PIC_NUM_MSG_Q_IRTS 32
|
||||
#define PIC_IRT_MSG_Q0_INDEX 12
|
||||
#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
|
||||
/* 12 to 43 */
|
||||
#define PIC_IRT_MSG_0_INDEX 44
|
||||
#define PIC_IRT_MSG_1_INDEX 45
|
||||
/* 44 and 45 */
|
||||
#define PIC_NUM_PCIE_MSIX_IRTS 32
|
||||
#define PIC_IRT_PCIE_MSIX_0_INDEX 46
|
||||
#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
|
||||
/* 46 to 77 */
|
||||
#define PIC_NUM_PCIE_LINK_IRTS 4
|
||||
#define PIC_IRT_PCIE_LINK_0_INDEX 78
|
||||
#define PIC_IRT_PCIE_LINK_1_INDEX 79
|
||||
#define PIC_IRT_PCIE_LINK_2_INDEX 80
|
||||
#define PIC_IRT_PCIE_LINK_3_INDEX 81
|
||||
#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
|
||||
|
||||
#define PIC_9XX_IRT_PCIE_LINK_0_INDEX 191
|
||||
#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \
|
||||
((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX)
|
||||
|
||||
#define PIC_CLOCK_TIMER 7
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
|
||||
/*
|
||||
* Misc
|
||||
*/
|
||||
#define PIC_IRT_VALID 1
|
||||
#define PIC_LOCAL_SCHEDULING 1
|
||||
#define PIC_GLOBAL_SCHEDULING 0
|
||||
|
||||
#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
|
||||
#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
|
||||
#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
|
||||
XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
|
||||
#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
|
||||
|
||||
/* We use PIC on node 0 as a timer */
|
||||
#define pic_timer_freq() nlm_get_pic_frequency(0)
|
||||
|
||||
/* IRT and h/w interrupt routines */
|
||||
static inline void
|
||||
nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
|
||||
int sch, int vec, int dt, int db, int cpu)
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
|
||||
((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
|
||||
((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
|
||||
(cpu & 0x3ff);
|
||||
|
||||
nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
|
||||
int sch, int vec, int dt, int db, int dte)
|
||||
{
|
||||
uint64_t val;
|
||||
|
||||
val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
|
||||
((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
|
||||
((dt & 0x1) << 19) | ((db & 0x7) << 16) |
|
||||
(dte & 0xffff);
|
||||
|
||||
nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
|
||||
int sch, int vec, int cpu)
|
||||
{
|
||||
if (cpu_is_xlp9xx())
|
||||
nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
|
||||
1, 0, cpu);
|
||||
else
|
||||
nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
|
||||
(cpu >> 4), /* thread group */
|
||||
1 << (cpu & 0xf)); /* thread mask */
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
nlm_pic_read_timer(uint64_t base, int timer)
|
||||
{
|
||||
return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
|
||||
}
|
||||
|
||||
static inline uint32_t
|
||||
nlm_pic_read_timer32(uint64_t base, int timer)
|
||||
{
|
||||
return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
|
||||
{
|
||||
nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
|
||||
{
|
||||
uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
|
||||
int en;
|
||||
|
||||
en = (irq > 0);
|
||||
nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
|
||||
nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
|
||||
en, 0, 0, irq, cpu);
|
||||
|
||||
/* enable the timer */
|
||||
pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
|
||||
nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_enable_irt(uint64_t base, int irt)
|
||||
{
|
||||
uint64_t reg;
|
||||
|
||||
if (cpu_is_xlp9xx()) {
|
||||
reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
|
||||
nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
|
||||
} else {
|
||||
reg = nlm_read_pic_reg(base, PIC_IRT(irt));
|
||||
nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_disable_irt(uint64_t base, int irt)
|
||||
{
|
||||
uint64_t reg;
|
||||
|
||||
if (cpu_is_xlp9xx()) {
|
||||
reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
|
||||
reg &= ~((uint64_t)1 << 22);
|
||||
nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
|
||||
} else {
|
||||
reg = nlm_read_pic_reg(base, PIC_IRT(irt));
|
||||
reg &= ~((uint64_t)1 << 31);
|
||||
nlm_write_pic_reg(base, PIC_IRT(irt), reg);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
|
||||
{
|
||||
uint64_t ipi;
|
||||
|
||||
if (cpu_is_xlp9xx())
|
||||
ipi = (nmi << 23) | (irq << 24) |
|
||||
(0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
|
||||
else
|
||||
ipi = ((uint64_t)nmi << 31) | (irq << 20) |
|
||||
((hwt >> 4) << 16) | (1 << (hwt & 0xf));
|
||||
|
||||
nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_ack(uint64_t base, int irt_num)
|
||||
{
|
||||
nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
|
||||
|
||||
/* Ack the Status register for Watchdog & System timers */
|
||||
if (irt_num < 12)
|
||||
nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
|
||||
{
|
||||
nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
|
||||
}
|
||||
|
||||
int nlm_irq_to_irt(int irq);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _NLM_HAL_PIC_H */
|
||||
210
arch/mips/include/asm/netlogic/xlp-hal/sys.h
Normal file
210
arch/mips/include/asm/netlogic/xlp-hal/sys.h
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __NLM_HAL_SYS_H__
|
||||
#define __NLM_HAL_SYS_H__
|
||||
|
||||
/**
|
||||
* @file_name sys.h
|
||||
* @author Netlogic Microsystems
|
||||
* @brief HAL for System configuration registers
|
||||
*/
|
||||
#define SYS_CHIP_RESET 0x00
|
||||
#define SYS_POWER_ON_RESET_CFG 0x01
|
||||
#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
|
||||
#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
|
||||
#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
|
||||
#define SYS_EFUSE_DEVICE_CFG3 0x05
|
||||
#define SYS_EFUSE_DEVICE_CFG4 0x06
|
||||
#define SYS_EFUSE_DEVICE_CFG5 0x07
|
||||
#define SYS_EFUSE_DEVICE_CFG6 0x08
|
||||
#define SYS_EFUSE_DEVICE_CFG7 0x09
|
||||
#define SYS_PLL_CTRL 0x0a
|
||||
#define SYS_CPU_RESET 0x0b
|
||||
#define SYS_CPU_NONCOHERENT_MODE 0x0d
|
||||
#define SYS_CORE_DFS_DIS_CTRL 0x0e
|
||||
#define SYS_CORE_DFS_RST_CTRL 0x0f
|
||||
#define SYS_CORE_DFS_BYP_CTRL 0x10
|
||||
#define SYS_CORE_DFS_PHA_CTRL 0x11
|
||||
#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
|
||||
#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
|
||||
#define SYS_CORE_DFS_DIV_VALUE 0x14
|
||||
#define SYS_RESET 0x15
|
||||
#define SYS_DFS_DIS_CTRL 0x16
|
||||
#define SYS_DFS_RST_CTRL 0x17
|
||||
#define SYS_DFS_BYP_CTRL 0x18
|
||||
#define SYS_DFS_DIV_INC_CTRL 0x19
|
||||
#define SYS_DFS_DIV_DEC_CTRL 0x1a
|
||||
#define SYS_DFS_DIV_VALUE0 0x1b
|
||||
#define SYS_DFS_DIV_VALUE1 0x1c
|
||||
#define SYS_SENSE_AMP_DLY 0x1d
|
||||
#define SYS_SOC_SENSE_AMP_DLY 0x1e
|
||||
#define SYS_CTRL0 0x1f
|
||||
#define SYS_CTRL1 0x20
|
||||
#define SYS_TIMEOUT_BS1 0x21
|
||||
#define SYS_BYTE_SWAP 0x22
|
||||
#define SYS_VRM_VID 0x23
|
||||
#define SYS_PWR_RAM_CMD 0x24
|
||||
#define SYS_PWR_RAM_ADDR 0x25
|
||||
#define SYS_PWR_RAM_DATA0 0x26
|
||||
#define SYS_PWR_RAM_DATA1 0x27
|
||||
#define SYS_PWR_RAM_DATA2 0x28
|
||||
#define SYS_PWR_UCODE 0x29
|
||||
#define SYS_CPU0_PWR_STATUS 0x2a
|
||||
#define SYS_CPU1_PWR_STATUS 0x2b
|
||||
#define SYS_CPU2_PWR_STATUS 0x2c
|
||||
#define SYS_CPU3_PWR_STATUS 0x2d
|
||||
#define SYS_CPU4_PWR_STATUS 0x2e
|
||||
#define SYS_CPU5_PWR_STATUS 0x2f
|
||||
#define SYS_CPU6_PWR_STATUS 0x30
|
||||
#define SYS_CPU7_PWR_STATUS 0x31
|
||||
#define SYS_STATUS 0x32
|
||||
#define SYS_INT_POL 0x33
|
||||
#define SYS_INT_TYPE 0x34
|
||||
#define SYS_INT_STATUS 0x35
|
||||
#define SYS_INT_MASK0 0x36
|
||||
#define SYS_INT_MASK1 0x37
|
||||
#define SYS_UCO_S_ECC 0x38
|
||||
#define SYS_UCO_M_ECC 0x39
|
||||
#define SYS_UCO_ADDR 0x3a
|
||||
#define SYS_UCO_INSTR 0x3b
|
||||
#define SYS_MEM_BIST0 0x3c
|
||||
#define SYS_MEM_BIST1 0x3d
|
||||
#define SYS_MEM_BIST2 0x3e
|
||||
#define SYS_MEM_BIST3 0x3f
|
||||
#define SYS_MEM_BIST4 0x40
|
||||
#define SYS_MEM_BIST5 0x41
|
||||
#define SYS_MEM_BIST6 0x42
|
||||
#define SYS_MEM_BIST7 0x43
|
||||
#define SYS_MEM_BIST8 0x44
|
||||
#define SYS_MEM_BIST9 0x45
|
||||
#define SYS_MEM_BIST10 0x46
|
||||
#define SYS_MEM_BIST11 0x47
|
||||
#define SYS_MEM_BIST12 0x48
|
||||
#define SYS_SCRTCH0 0x49
|
||||
#define SYS_SCRTCH1 0x4a
|
||||
#define SYS_SCRTCH2 0x4b
|
||||
#define SYS_SCRTCH3 0x4c
|
||||
|
||||
/* PLL registers XLP2XX */
|
||||
#define SYS_CPU_PLL_CTRL0(core) (0x1c0 + (core * 4))
|
||||
#define SYS_CPU_PLL_CTRL1(core) (0x1c1 + (core * 4))
|
||||
#define SYS_CPU_PLL_CTRL2(core) (0x1c2 + (core * 4))
|
||||
#define SYS_CPU_PLL_CTRL3(core) (0x1c3 + (core * 4))
|
||||
#define SYS_PLL_CTRL0 0x240
|
||||
#define SYS_PLL_CTRL1 0x241
|
||||
#define SYS_PLL_CTRL2 0x242
|
||||
#define SYS_PLL_CTRL3 0x243
|
||||
#define SYS_DMC_PLL_CTRL0 0x244
|
||||
#define SYS_DMC_PLL_CTRL1 0x245
|
||||
#define SYS_DMC_PLL_CTRL2 0x246
|
||||
#define SYS_DMC_PLL_CTRL3 0x247
|
||||
|
||||
#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4)
|
||||
#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4)
|
||||
#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4)
|
||||
#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4)
|
||||
|
||||
#define SYS_CPU_PLL_CHG_CTRL 0x288
|
||||
#define SYS_PLL_CHG_CTRL 0x289
|
||||
#define SYS_CLK_DEV_DIS 0x28a
|
||||
#define SYS_CLK_DEV_SEL 0x28b
|
||||
#define SYS_CLK_DEV_DIV 0x28c
|
||||
#define SYS_CLK_DEV_CHG 0x28d
|
||||
#define SYS_CLK_DEV_SEL_REG 0x28e
|
||||
#define SYS_CLK_DEV_DIV_REG 0x28f
|
||||
#define SYS_CPU_PLL_LOCK 0x29f
|
||||
#define SYS_SYS_PLL_LOCK 0x2a0
|
||||
#define SYS_PLL_MEM_CMD 0x2a1
|
||||
#define SYS_CPU_PLL_MEM_REQ 0x2a2
|
||||
#define SYS_SYS_PLL_MEM_REQ 0x2a3
|
||||
#define SYS_PLL_MEM_STAT 0x2a4
|
||||
|
||||
/* PLL registers XLP9XX */
|
||||
#define SYS_9XX_CPU_PLL_CTRL0(core) (0xc0 + (core * 4))
|
||||
#define SYS_9XX_CPU_PLL_CTRL1(core) (0xc1 + (core * 4))
|
||||
#define SYS_9XX_CPU_PLL_CTRL2(core) (0xc2 + (core * 4))
|
||||
#define SYS_9XX_CPU_PLL_CTRL3(core) (0xc3 + (core * 4))
|
||||
#define SYS_9XX_DMC_PLL_CTRL0 0x140
|
||||
#define SYS_9XX_DMC_PLL_CTRL1 0x141
|
||||
#define SYS_9XX_DMC_PLL_CTRL2 0x142
|
||||
#define SYS_9XX_DMC_PLL_CTRL3 0x143
|
||||
#define SYS_9XX_PLL_CTRL0 0x144
|
||||
#define SYS_9XX_PLL_CTRL1 0x145
|
||||
#define SYS_9XX_PLL_CTRL2 0x146
|
||||
#define SYS_9XX_PLL_CTRL3 0x147
|
||||
|
||||
#define SYS_9XX_PLL_CTRL0_DEVX(x) (0x148 + (x) * 4)
|
||||
#define SYS_9XX_PLL_CTRL1_DEVX(x) (0x149 + (x) * 4)
|
||||
#define SYS_9XX_PLL_CTRL2_DEVX(x) (0x14a + (x) * 4)
|
||||
#define SYS_9XX_PLL_CTRL3_DEVX(x) (0x14b + (x) * 4)
|
||||
|
||||
#define SYS_9XX_CPU_PLL_CHG_CTRL 0x188
|
||||
#define SYS_9XX_PLL_CHG_CTRL 0x189
|
||||
#define SYS_9XX_CLK_DEV_DIS 0x18a
|
||||
#define SYS_9XX_CLK_DEV_SEL 0x18b
|
||||
#define SYS_9XX_CLK_DEV_DIV 0x18d
|
||||
#define SYS_9XX_CLK_DEV_CHG 0x18f
|
||||
|
||||
/* Registers changed on 9XX */
|
||||
#define SYS_9XX_POWER_ON_RESET_CFG 0x00
|
||||
#define SYS_9XX_CHIP_RESET 0x01
|
||||
#define SYS_9XX_CPU_RESET 0x02
|
||||
#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03
|
||||
|
||||
/* XLP 9XX fuse block registers */
|
||||
#define FUSE_9XX_DEVCFG6 0xc6
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
|
||||
#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
|
||||
#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
|
||||
XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
|
||||
#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
|
||||
|
||||
/* XLP9XX fuse block */
|
||||
#define nlm_get_fuse_pcibase(node) \
|
||||
nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
|
||||
#define nlm_get_fuse_regbase(node) \
|
||||
(nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
|
||||
|
||||
#define nlm_get_clock_pcibase(node) \
|
||||
nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node))
|
||||
#define nlm_get_clock_regbase(node) \
|
||||
(nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ)
|
||||
|
||||
unsigned int nlm_get_pic_frequency(int node);
|
||||
#endif
|
||||
#endif
|
||||
192
arch/mips/include/asm/netlogic/xlp-hal/uart.h
Normal file
192
arch/mips/include/asm/netlogic/xlp-hal/uart.h
Normal file
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __XLP_HAL_UART_H__
|
||||
#define __XLP_HAL_UART_H__
|
||||
|
||||
/* UART Specific registers */
|
||||
#define UART_RX_DATA 0x00
|
||||
#define UART_TX_DATA 0x00
|
||||
|
||||
#define UART_INT_EN 0x01
|
||||
#define UART_INT_ID 0x02
|
||||
#define UART_FIFO_CTL 0x02
|
||||
#define UART_LINE_CTL 0x03
|
||||
#define UART_MODEM_CTL 0x04
|
||||
#define UART_LINE_STS 0x05
|
||||
#define UART_MODEM_STS 0x06
|
||||
|
||||
#define UART_DIVISOR0 0x00
|
||||
#define UART_DIVISOR1 0x01
|
||||
|
||||
#define BASE_BAUD (XLP_IO_CLK/16)
|
||||
#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
|
||||
|
||||
/* LCR mask values */
|
||||
#define LCR_5BITS 0x00
|
||||
#define LCR_6BITS 0x01
|
||||
#define LCR_7BITS 0x02
|
||||
#define LCR_8BITS 0x03
|
||||
#define LCR_STOPB 0x04
|
||||
#define LCR_PENAB 0x08
|
||||
#define LCR_PODD 0x00
|
||||
#define LCR_PEVEN 0x10
|
||||
#define LCR_PONE 0x20
|
||||
#define LCR_PZERO 0x30
|
||||
#define LCR_SBREAK 0x40
|
||||
#define LCR_EFR_ENABLE 0xbf
|
||||
#define LCR_DLAB 0x80
|
||||
|
||||
/* MCR mask values */
|
||||
#define MCR_DTR 0x01
|
||||
#define MCR_RTS 0x02
|
||||
#define MCR_DRS 0x04
|
||||
#define MCR_IE 0x08
|
||||
#define MCR_LOOPBACK 0x10
|
||||
|
||||
/* FCR mask values */
|
||||
#define FCR_RCV_RST 0x02
|
||||
#define FCR_XMT_RST 0x04
|
||||
#define FCR_RX_LOW 0x00
|
||||
#define FCR_RX_MEDL 0x40
|
||||
#define FCR_RX_MEDH 0x80
|
||||
#define FCR_RX_HIGH 0xc0
|
||||
|
||||
/* IER mask values */
|
||||
#define IER_ERXRDY 0x1
|
||||
#define IER_ETXRDY 0x2
|
||||
#define IER_ERLS 0x4
|
||||
#define IER_EMSC 0x8
|
||||
|
||||
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
|
||||
|
||||
#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
|
||||
#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
|
||||
#define nlm_get_uart_pcibase(node, inst) \
|
||||
nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \
|
||||
XLP_IO_UART_OFFSET(node, inst))
|
||||
#define nlm_get_uart_regbase(node, inst) \
|
||||
(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
|
||||
|
||||
static inline void
|
||||
nlm_uart_set_baudrate(uint64_t base, int baud)
|
||||
{
|
||||
uint32_t lcr;
|
||||
|
||||
lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
|
||||
|
||||
/* enable divisor register, and write baud values */
|
||||
nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
|
||||
nlm_write_uart_reg(base, UART_DIVISOR0,
|
||||
(BAUD_DIVISOR(baud) & 0xff));
|
||||
nlm_write_uart_reg(base, UART_DIVISOR1,
|
||||
((BAUD_DIVISOR(baud) >> 8) & 0xff));
|
||||
|
||||
/* restore default lcr */
|
||||
nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nlm_uart_outbyte(uint64_t base, char c)
|
||||
{
|
||||
uint32_t lsr;
|
||||
|
||||
for (;;) {
|
||||
lsr = nlm_read_uart_reg(base, UART_LINE_STS);
|
||||
if (lsr & 0x20)
|
||||
break;
|
||||
}
|
||||
|
||||
nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
|
||||
}
|
||||
|
||||
static inline char
|
||||
nlm_uart_inbyte(uint64_t base)
|
||||
{
|
||||
int data, lsr;
|
||||
|
||||
for (;;) {
|
||||
lsr = nlm_read_uart_reg(base, UART_LINE_STS);
|
||||
if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
|
||||
data = 0;
|
||||
break;
|
||||
}
|
||||
if (lsr & 0x01) { /* Rx data */
|
||||
data = nlm_read_uart_reg(base, UART_RX_DATA);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (char)data;
|
||||
}
|
||||
|
||||
static inline int
|
||||
nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
|
||||
int parity, int int_en, int loopback)
|
||||
{
|
||||
uint32_t lcr;
|
||||
|
||||
lcr = 0;
|
||||
if (databits >= 8)
|
||||
lcr |= LCR_8BITS;
|
||||
else if (databits == 7)
|
||||
lcr |= LCR_7BITS;
|
||||
else if (databits == 6)
|
||||
lcr |= LCR_6BITS;
|
||||
else
|
||||
lcr |= LCR_5BITS;
|
||||
|
||||
if (stopbits > 1)
|
||||
lcr |= LCR_STOPB;
|
||||
|
||||
lcr |= parity << 3;
|
||||
|
||||
/* setup default lcr */
|
||||
nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
|
||||
|
||||
/* Reset the FIFOs */
|
||||
nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
|
||||
|
||||
nlm_uart_set_baudrate(base, baud);
|
||||
|
||||
if (loopback)
|
||||
nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
|
||||
|
||||
if (int_en)
|
||||
nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* !LOCORE && !__ASSEMBLY__ */
|
||||
#endif /* __XLP_HAL_UART_H__ */
|
||||
118
arch/mips/include/asm/netlogic/xlp-hal/xlp.h
Normal file
118
arch/mips/include/asm/netlogic/xlp-hal/xlp.h
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _NLM_HAL_XLP_H
|
||||
#define _NLM_HAL_XLP_H
|
||||
|
||||
#define PIC_UART_0_IRQ 17
|
||||
#define PIC_UART_1_IRQ 18
|
||||
|
||||
#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
|
||||
#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
|
||||
|
||||
#define PIC_EHCI_0_IRQ 23
|
||||
#define PIC_EHCI_1_IRQ 24
|
||||
#define PIC_OHCI_0_IRQ 25
|
||||
#define PIC_OHCI_1_IRQ 26
|
||||
#define PIC_OHCI_2_IRQ 27
|
||||
#define PIC_OHCI_3_IRQ 28
|
||||
#define PIC_2XX_XHCI_0_IRQ 23
|
||||
#define PIC_2XX_XHCI_1_IRQ 24
|
||||
#define PIC_2XX_XHCI_2_IRQ 25
|
||||
#define PIC_9XX_XHCI_0_IRQ 23
|
||||
#define PIC_9XX_XHCI_1_IRQ 24
|
||||
|
||||
#define PIC_MMC_IRQ 29
|
||||
#define PIC_I2C_0_IRQ 30
|
||||
#define PIC_I2C_1_IRQ 31
|
||||
#define PIC_I2C_2_IRQ 32
|
||||
#define PIC_I2C_3_IRQ 33
|
||||
#define PIC_SPI_IRQ 34
|
||||
#define PIC_NAND_IRQ 37
|
||||
#define PIC_SATA_IRQ 38
|
||||
#define PIC_GPIO_IRQ 39
|
||||
|
||||
#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
|
||||
#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
|
||||
|
||||
/* MSI-X with second link-level dispatch */
|
||||
#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
|
||||
#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
|
||||
|
||||
/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
|
||||
#define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */
|
||||
#define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */
|
||||
|
||||
#define NLM_PIC_INDIRECT_VEC_BASE 512
|
||||
#define NLM_GPIO_VEC_BASE 768
|
||||
|
||||
#define PIC_IRQ_BASE 8
|
||||
#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
|
||||
#define PIC_IRT_LAST_IRQ 63
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* SMP support functions */
|
||||
void xlp_boot_core0_siblings(void);
|
||||
void xlp_wakeup_secondary_cpus(void);
|
||||
|
||||
void xlp_mmu_init(void);
|
||||
void nlm_hal_init(void);
|
||||
int xlp_get_dram_map(int n, uint64_t *dram_map);
|
||||
|
||||
struct pci_dev;
|
||||
int xlp_socdev_to_node(const struct pci_dev *dev);
|
||||
|
||||
/* Device tree related */
|
||||
void xlp_early_init_devtree(void);
|
||||
void *xlp_dt_init(void *fdtp);
|
||||
|
||||
static inline int cpu_is_xlpii(void)
|
||||
{
|
||||
int chip = read_c0_prid() & PRID_IMP_MASK;
|
||||
|
||||
return chip == PRID_IMP_NETLOGIC_XLP2XX ||
|
||||
chip == PRID_IMP_NETLOGIC_XLP9XX ||
|
||||
chip == PRID_IMP_NETLOGIC_XLP5XX;
|
||||
}
|
||||
|
||||
static inline int cpu_is_xlp9xx(void)
|
||||
{
|
||||
int chip = read_c0_prid() & PRID_IMP_MASK;
|
||||
|
||||
return chip == PRID_IMP_NETLOGIC_XLP9XX ||
|
||||
chip == PRID_IMP_NETLOGIC_XLP5XX;
|
||||
}
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* _ASM_NLM_XLP_H */
|
||||
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Add table
Add a link
Reference in a new issue