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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
299
arch/mips/include/asm/octeon/cvmx-fpa.h
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299
arch/mips/include/asm/octeon/cvmx-fpa.h
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the hardware Free Pool Allocator.
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*
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*
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*/
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#ifndef __CVMX_FPA_H__
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#define __CVMX_FPA_H__
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#include <asm/octeon/cvmx-address.h>
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#include <asm/octeon/cvmx-fpa-defs.h>
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#define CVMX_FPA_NUM_POOLS 8
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#define CVMX_FPA_MIN_BLOCK_SIZE 128
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#define CVMX_FPA_ALIGNMENT 128
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/**
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* Structure describing the data format used for stores to the FPA.
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*/
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typedef union {
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uint64_t u64;
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struct {
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/*
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* the (64-bit word) location in scratchpad to write
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* to (if len != 0)
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*/
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uint64_t scraddr:8;
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/* the number of words in the response (0 => no response) */
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uint64_t len:8;
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/* the ID of the device on the non-coherent bus */
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uint64_t did:8;
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/*
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* the address that will appear in the first tick on
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* the NCB bus.
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*/
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uint64_t addr:40;
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} s;
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} cvmx_fpa_iobdma_data_t;
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/**
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* Structure describing the current state of a FPA pool.
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*/
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typedef struct {
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/* Name it was created under */
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const char *name;
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/* Size of each block */
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uint64_t size;
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/* The base memory address of whole block */
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void *base;
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/* The number of elements in the pool at creation */
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uint64_t starting_element_count;
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} cvmx_fpa_pool_info_t;
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/**
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* Current state of all the pools. Use access functions
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* instead of using it directly.
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*/
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extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
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/* CSR typedefs have been moved to cvmx-csr-*.h */
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/**
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* Return the name of the pool
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*
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* @pool: Pool to get the name of
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* Returns The name
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*/
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static inline const char *cvmx_fpa_get_name(uint64_t pool)
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{
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return cvmx_fpa_pool_info[pool].name;
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}
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/**
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* Return the base of the pool
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*
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* @pool: Pool to get the base of
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* Returns The base
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*/
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static inline void *cvmx_fpa_get_base(uint64_t pool)
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{
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return cvmx_fpa_pool_info[pool].base;
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}
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/**
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* Check if a pointer belongs to an FPA pool. Return non-zero
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* if the supplied pointer is inside the memory controlled by
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* an FPA pool.
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*
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* @pool: Pool to check
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* @ptr: Pointer to check
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* Returns Non-zero if pointer is in the pool. Zero if not
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*/
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static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
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{
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return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
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((char *)ptr <
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((char *)(cvmx_fpa_pool_info[pool].base)) +
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cvmx_fpa_pool_info[pool].size *
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cvmx_fpa_pool_info[pool].starting_element_count));
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}
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/**
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* Enable the FPA for use. Must be performed after any CSR
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* configuration but before any other FPA functions.
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*/
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static inline void cvmx_fpa_enable(void)
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{
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union cvmx_fpa_ctl_status status;
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status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
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if (status.s.enb) {
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cvmx_dprintf
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("Warning: Enabling FPA when FPA already enabled.\n");
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}
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/*
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* Do runtime check as we allow pass1 compiled code to run on
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* pass2 chips.
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*/
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if (cvmx_octeon_is_pass1()) {
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union cvmx_fpa_fpfx_marks marks;
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int i;
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for (i = 1; i < 8; i++) {
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marks.u64 =
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cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
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marks.s.fpf_wr = 0xe0;
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cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
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marks.u64);
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}
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/* Enforce a 10 cycle delay between config and enable */
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cvmx_wait(10);
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}
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/* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
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status.u64 = 0;
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status.s.enb = 1;
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cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
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}
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/**
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* Get a new block from the FPA
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*
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* @pool: Pool to get the block from
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* Returns Pointer to the block or NULL on failure
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*/
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static inline void *cvmx_fpa_alloc(uint64_t pool)
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{
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uint64_t address =
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cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
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if (address)
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return cvmx_phys_to_ptr(address);
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else
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return NULL;
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}
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/**
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* Asynchronously get a new block from the FPA
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*
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* @scr_addr: Local scratch address to put response in. This is a byte address,
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* but must be 8 byte aligned.
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* @pool: Pool to get the block from
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*/
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static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
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{
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cvmx_fpa_iobdma_data_t data;
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/*
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* Hardware only uses 64 bit aligned locations, so convert
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* from byte address to 64-bit index
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*/
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data.s.scraddr = scr_addr >> 3;
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data.s.len = 1;
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data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
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data.s.addr = 0;
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cvmx_send_single(data.u64);
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}
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/**
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* Free a block allocated with a FPA pool. Does NOT provide memory
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* ordering in cases where the memory block was modified by the core.
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*
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* @ptr: Block to free
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* @pool: Pool to put it in
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* @num_cache_lines:
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* Cache lines to invalidate
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*/
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static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
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uint64_t num_cache_lines)
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{
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cvmx_addr_t newptr;
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newptr.u64 = cvmx_ptr_to_phys(ptr);
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newptr.sfilldidspace.didspace =
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CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
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/* Prevent GCC from reordering around free */
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barrier();
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/* value written is number of cache lines not written back */
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cvmx_write_io(newptr.u64, num_cache_lines);
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}
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/**
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* Free a block allocated with a FPA pool. Provides required memory
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* ordering in cases where memory block was modified by core.
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*
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* @ptr: Block to free
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* @pool: Pool to put it in
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* @num_cache_lines:
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* Cache lines to invalidate
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*/
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static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
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uint64_t num_cache_lines)
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{
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cvmx_addr_t newptr;
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newptr.u64 = cvmx_ptr_to_phys(ptr);
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newptr.sfilldidspace.didspace =
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CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
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/*
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* Make sure that any previous writes to memory go out before
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* we free this buffer. This also serves as a barrier to
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* prevent GCC from reordering operations to after the
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* free.
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*/
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CVMX_SYNCWS;
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/* value written is number of cache lines not written back */
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cvmx_write_io(newptr.u64, num_cache_lines);
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}
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/**
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* Setup a FPA pool to control a new block of memory.
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* This can only be called once per pool. Make sure proper
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* locking enforces this.
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*
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* @pool: Pool to initialize
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* 0 <= pool < 8
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* @name: Constant character string to name this pool.
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* String is not copied.
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* @buffer: Pointer to the block of memory to use. This must be
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* accessible by all processors and external hardware.
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* @block_size: Size for each block controlled by the FPA
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* @num_blocks: Number of blocks
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*
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* Returns 0 on Success,
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* -1 on failure
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*/
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extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
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uint64_t block_size, uint64_t num_blocks);
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/**
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* Shutdown a Memory pool and validate that it had all of
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* the buffers originally placed in it. This should only be
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* called by one processor after all hardware has finished
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* using the pool.
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*
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* @pool: Pool to shutdown
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* Returns Zero on success
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* - Positive is count of missing buffers
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* - Negative is too many buffers or corrupted pointers
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*/
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extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
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/**
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* Get the size of blocks controlled by the pool
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* This is resolved to a constant at compile time.
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*
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* @pool: Pool to access
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* Returns Size of the block in bytes
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*/
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uint64_t cvmx_fpa_get_block_size(uint64_t pool);
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#endif /* __CVM_FPA_H__ */
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