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Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
170
arch/mips/include/uapi/asm/kvm.h
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170
arch/mips/include/uapi/asm/kvm.h
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2013 Cavium, Inc.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#ifndef __LINUX_KVM_MIPS_H
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#define __LINUX_KVM_MIPS_H
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#include <linux/types.h>
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/*
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* KVM MIPS specific structures and definitions.
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*
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* Some parts derived from the x86 version of this file.
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*/
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/*
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* for KVM_GET_REGS and KVM_SET_REGS
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*
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* If Config[AT] is zero (32-bit CPU), the register contents are
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* stored in the lower 32-bits of the struct kvm_regs fields and sign
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* extended to 64-bits.
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*/
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struct kvm_regs {
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/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
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__u64 gpr[32];
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__u64 hi;
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__u64 lo;
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__u64 pc;
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};
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/*
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* for KVM_GET_FPU and KVM_SET_FPU
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*
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* If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs
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* are zero filled.
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*/
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struct kvm_fpu {
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__u64 fpr[32];
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__u32 fir;
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__u32 fccr;
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__u32 fexr;
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__u32 fenr;
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__u32 fcsr;
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__u32 pad;
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};
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/*
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* For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0
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* registers. The id field is broken down as follows:
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*
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* bits[2..0] - Register 'sel' index.
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* bits[7..3] - Register 'rd' index.
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* bits[15..8] - Must be zero.
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* bits[31..16] - 1 -> CP0 registers.
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* bits[51..32] - Must be zero.
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* bits[63..52] - As per linux/kvm.h
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*
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* Other sets registers may be added in the future. Each set would
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* have its own identifier in bits[31..16].
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*
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* The registers defined in struct kvm_regs are also accessible, the
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* id values for these are below.
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*/
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#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
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#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
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#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
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#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
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#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
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#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
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#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
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#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
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#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
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#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
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#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
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#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
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#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
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#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
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#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
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#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
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#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
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#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
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#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
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#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
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#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
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#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
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#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
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#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
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#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
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#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
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#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
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#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
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#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
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#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
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#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
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#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
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#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
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#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
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#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
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/* KVM specific control registers */
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/*
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* CP0_Count control
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* DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now
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* Set 1: Master re-enable CP0_Count with unchanged bias, handling timer
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* interrupts since COUNT_RESUME
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* This can be used to freeze the timer to get a consistent snapshot of
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* the CP0_Count and timer interrupt pending state, while also resuming
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* safely without losing time or guest timer interrupts.
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* Other: Reserved, do not change.
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*/
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#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 0)
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#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001
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/*
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* CP0_Count resume monotonic nanoseconds
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* The monotonic nanosecond time of the last set of COUNT_CTL.DC (master
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* disable). Any reads and writes of Count related registers while
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* COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is
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* cleared again (master enable) any timer interrupts since this time will be
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* emulated.
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* Modifications to times in the future are rejected.
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*/
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#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 1)
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/*
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* CP0_Count rate in Hz
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* Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
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* discontinuities in CP0_Count.
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*/
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#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 2)
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/*
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* KVM MIPS specific structures and definitions
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*
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*/
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struct kvm_debug_exit_arch {
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__u64 epc;
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};
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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/* dummy definition */
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struct kvm_sregs {
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};
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struct kvm_mips_interrupt {
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/* in */
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__u32 cpu;
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__u32 irq;
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};
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#endif /* __LINUX_KVM_MIPS_H */
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