mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 07:38:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
315
arch/mips/kernel/mips-mt.c
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315
arch/mips/kernel/mips-mt.c
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/*
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* General MIPS MT support routines, usable in AP/SP and SMVP.
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* Copyright (C) 2005 Mips Technologies, Inc
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/security.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <linux/atomic.h>
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#include <asm/hardirq.h>
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#include <asm/mmu_context.h>
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#include <asm/mipsmtregs.h>
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#include <asm/r4kcache.h>
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#include <asm/cacheflush.h>
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int vpelimit;
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static int __init maxvpes(char *str)
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{
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get_option(&str, &vpelimit);
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return 1;
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}
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__setup("maxvpes=", maxvpes);
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int tclimit;
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static int __init maxtcs(char *str)
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{
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get_option(&str, &tclimit);
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return 1;
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}
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__setup("maxtcs=", maxtcs);
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/*
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* Dump new MIPS MT state for the core. Does not leave TCs halted.
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* Takes an argument which taken to be a pre-call MVPControl value.
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*/
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void mips_mt_regdump(unsigned long mvpctl)
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{
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unsigned long flags;
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unsigned long vpflags;
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unsigned long mvpconf0;
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int nvpe;
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int ntc;
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int i;
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int tc;
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unsigned long haltval;
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unsigned long tcstatval;
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local_irq_save(flags);
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vpflags = dvpe();
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printk("=== MIPS MT State Dump ===\n");
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printk("-- Global State --\n");
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printk(" MVPControl Passed: %08lx\n", mvpctl);
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printk(" MVPControl Read: %08lx\n", vpflags);
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printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
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nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
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printk("-- per-VPE State --\n");
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for (i = 0; i < nvpe; i++) {
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for (tc = 0; tc < ntc; tc++) {
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settc(tc);
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if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
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printk(" VPE %d\n", i);
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printk(" VPEControl : %08lx\n",
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read_vpe_c0_vpecontrol());
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printk(" VPEConf0 : %08lx\n",
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read_vpe_c0_vpeconf0());
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printk(" VPE%d.Status : %08lx\n",
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i, read_vpe_c0_status());
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printk(" VPE%d.EPC : %08lx %pS\n",
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i, read_vpe_c0_epc(),
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(void *) read_vpe_c0_epc());
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printk(" VPE%d.Cause : %08lx\n",
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i, read_vpe_c0_cause());
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printk(" VPE%d.Config7 : %08lx\n",
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i, read_vpe_c0_config7());
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break; /* Next VPE */
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}
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}
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}
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printk("-- per-TC State --\n");
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for (tc = 0; tc < ntc; tc++) {
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settc(tc);
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if (read_tc_c0_tcbind() == read_c0_tcbind()) {
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/* Are we dumping ourself? */
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haltval = 0; /* Then we're not halted, and mustn't be */
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tcstatval = flags; /* And pre-dump TCStatus is flags */
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printk(" TC %d (current TC with VPE EPC above)\n", tc);
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} else {
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haltval = read_tc_c0_tchalt();
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write_tc_c0_tchalt(1);
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tcstatval = read_tc_c0_tcstatus();
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printk(" TC %d\n", tc);
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}
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printk(" TCStatus : %08lx\n", tcstatval);
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printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
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printk(" TCRestart : %08lx %pS\n",
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read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
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printk(" TCHalt : %08lx\n", haltval);
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printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
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if (!haltval)
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write_tc_c0_tchalt(0);
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}
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printk("===========================\n");
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evpe(vpflags);
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local_irq_restore(flags);
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}
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static int mt_opt_norps;
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static int mt_opt_rpsctl = -1;
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static int mt_opt_nblsu = -1;
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static int mt_opt_forceconfig7;
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static int mt_opt_config7 = -1;
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static int __init rps_disable(char *s)
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{
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mt_opt_norps = 1;
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return 1;
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}
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__setup("norps", rps_disable);
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static int __init rpsctl_set(char *str)
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{
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get_option(&str, &mt_opt_rpsctl);
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return 1;
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}
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__setup("rpsctl=", rpsctl_set);
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static int __init nblsu_set(char *str)
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{
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get_option(&str, &mt_opt_nblsu);
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return 1;
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}
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__setup("nblsu=", nblsu_set);
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static int __init config7_set(char *str)
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{
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get_option(&str, &mt_opt_config7);
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mt_opt_forceconfig7 = 1;
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return 1;
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}
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__setup("config7=", config7_set);
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/* Experimental cache flush control parameters that should go away some day */
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int mt_protiflush;
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int mt_protdflush;
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int mt_n_iflushes = 1;
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int mt_n_dflushes = 1;
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static int __init set_protiflush(char *s)
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{
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mt_protiflush = 1;
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return 1;
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}
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__setup("protiflush", set_protiflush);
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static int __init set_protdflush(char *s)
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{
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mt_protdflush = 1;
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return 1;
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}
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__setup("protdflush", set_protdflush);
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static int __init niflush(char *s)
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{
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get_option(&s, &mt_n_iflushes);
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return 1;
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}
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__setup("niflush=", niflush);
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static int __init ndflush(char *s)
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{
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get_option(&s, &mt_n_dflushes);
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return 1;
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}
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__setup("ndflush=", ndflush);
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static unsigned int itc_base;
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static int __init set_itc_base(char *str)
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{
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get_option(&str, &itc_base);
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return 1;
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}
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__setup("itcbase=", set_itc_base);
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void mips_mt_set_cpuoptions(void)
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{
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unsigned int oconfig7 = read_c0_config7();
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unsigned int nconfig7 = oconfig7;
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if (mt_opt_norps) {
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printk("\"norps\" option deprecated: use \"rpsctl=\"\n");
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}
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if (mt_opt_rpsctl >= 0) {
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printk("34K return prediction stack override set to %d.\n",
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mt_opt_rpsctl);
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if (mt_opt_rpsctl)
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nconfig7 |= (1 << 2);
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else
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nconfig7 &= ~(1 << 2);
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}
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if (mt_opt_nblsu >= 0) {
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printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
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if (mt_opt_nblsu)
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nconfig7 |= (1 << 5);
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else
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nconfig7 &= ~(1 << 5);
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}
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if (mt_opt_forceconfig7) {
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printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
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nconfig7 = mt_opt_config7;
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}
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if (oconfig7 != nconfig7) {
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__asm__ __volatile("sync");
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write_c0_config7(nconfig7);
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ehb();
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printk("Config7: 0x%08x\n", read_c0_config7());
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}
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/* Report Cache management debug options */
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if (mt_protiflush)
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printk("I-cache flushes single-threaded\n");
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if (mt_protdflush)
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printk("D-cache flushes single-threaded\n");
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if (mt_n_iflushes != 1)
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printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
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if (mt_n_dflushes != 1)
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printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
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if (itc_base != 0) {
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/*
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* Configure ITC mapping. This code is very
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* specific to the 34K core family, which uses
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* a special mode bit ("ITC") in the ErrCtl
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* register to enable access to ITC control
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* registers via cache "tag" operations.
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*/
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unsigned long ectlval;
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unsigned long itcblkgrn;
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/* ErrCtl register is known as "ecc" to Linux */
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ectlval = read_c0_ecc();
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write_c0_ecc(ectlval | (0x1 << 26));
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ehb();
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#define INDEX_0 (0x80000000)
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#define INDEX_8 (0x80000008)
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/* Read "cache tag" for Dcache pseudo-index 8 */
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cache_op(Index_Load_Tag_D, INDEX_8);
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ehb();
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itcblkgrn = read_c0_dtaglo();
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itcblkgrn &= 0xfffe0000;
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/* Set for 128 byte pitch of ITC cells */
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itcblkgrn |= 0x00000c00;
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/* Stage in Tag register */
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write_c0_dtaglo(itcblkgrn);
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ehb();
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/* Write out to ITU with CACHE op */
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cache_op(Index_Store_Tag_D, INDEX_8);
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/* Now set base address, and turn ITC on with 0x1 bit */
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write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
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ehb();
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/* Write out to ITU with CACHE op */
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cache_op(Index_Store_Tag_D, INDEX_0);
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write_c0_ecc(ectlval);
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ehb();
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printk("Mapped %ld ITC cells starting at 0x%08x\n",
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((itcblkgrn & 0x7fe00000) >> 20), itc_base);
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}
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}
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/*
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* Function to protect cache flushes from concurrent execution
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* depends on MP software model chosen.
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*/
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void mt_cflush_lockdown(void)
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{
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/* FILL IN VSMP and AP/SP VERSIONS HERE */
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}
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void mt_cflush_release(void)
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{
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/* FILL IN VSMP and AP/SP VERSIONS HERE */
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}
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struct class *mt_class;
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static int __init mt_init(void)
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{
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struct class *mtc;
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mtc = class_create(THIS_MODULE, "mt");
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if (IS_ERR(mtc))
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return PTR_ERR(mtc);
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mt_class = mtc;
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return 0;
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}
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subsys_initcall(mt_init);
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