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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 23:58:51 +01:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
167
arch/mips/loongson/common/env.c
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167
arch/mips/loongson/common/env.c
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/*
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* Based on Ocelot Linux port, which is
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* Copyright 2003 ICT CAS
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* Author: Michael Guo <guoyi@ict.ac.cn>
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*
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* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* Copyright (C) 2009 Lemote Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <loongson.h>
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#include <boot_param.h>
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u32 cpu_clock_freq;
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EXPORT_SYMBOL(cpu_clock_freq);
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struct efi_memory_map_loongson *loongson_memmap;
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struct loongson_system_configuration loongson_sysconf;
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u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
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u64 loongson_freqctrl[MAX_PACKAGES];
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unsigned long long smp_group[4];
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int cpuhotplug_workaround = 0;
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#define parse_even_earlier(res, option, p) \
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do { \
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unsigned int tmp __maybe_unused; \
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\
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if (strncmp(option, (char *)p, strlen(option)) == 0) \
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tmp = kstrtou32((char *)p + strlen(option"="), 10, &res); \
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} while (0)
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void __init prom_init_env(void)
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{
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/* pmon passes arguments in 32bit pointers */
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unsigned int processor_id;
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#ifndef CONFIG_LEFI_FIRMWARE_INTERFACE
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int *_prom_envp;
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long l;
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/* firmware arguments are initialized in head.S */
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_prom_envp = (int *)fw_arg2;
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l = (long)*_prom_envp;
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while (l != 0) {
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parse_even_earlier(cpu_clock_freq, "cpuclock", l);
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parse_even_earlier(memsize, "memsize", l);
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parse_even_earlier(highmemsize, "highmemsize", l);
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_prom_envp++;
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l = (long)*_prom_envp;
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}
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if (memsize == 0)
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memsize = 256;
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pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize);
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#else
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struct boot_params *boot_p;
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struct loongson_params *loongson_p;
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struct efi_cpuinfo_loongson *ecpu;
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struct irq_source_routing_table *eirq_source;
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/* firmware arguments are initialized in head.S */
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boot_p = (struct boot_params *)fw_arg2;
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loongson_p = &(boot_p->efi.smbios.lp);
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ecpu = (struct efi_cpuinfo_loongson *)
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((u64)loongson_p + loongson_p->cpu_offset);
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eirq_source = (struct irq_source_routing_table *)
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((u64)loongson_p + loongson_p->irq_offset);
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loongson_memmap = (struct efi_memory_map_loongson *)
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((u64)loongson_p + loongson_p->memory_offset);
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cpu_clock_freq = ecpu->cpu_clock_freq;
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loongson_sysconf.cputype = ecpu->cputype;
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if (ecpu->cputype == Loongson_3A) {
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loongson_sysconf.cores_per_node = 4;
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loongson_sysconf.cores_per_package = 4;
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smp_group[0] = 0x900000003ff01000;
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smp_group[1] = 0x900010003ff01000;
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smp_group[2] = 0x900020003ff01000;
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smp_group[3] = 0x900030003ff01000;
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loongson_chipcfg[0] = 0x900000001fe00180;
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loongson_chipcfg[1] = 0x900010001fe00180;
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loongson_chipcfg[2] = 0x900020001fe00180;
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loongson_chipcfg[3] = 0x900030001fe00180;
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loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
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} else if (ecpu->cputype == Loongson_3B) {
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loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
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loongson_sysconf.cores_per_package = 8;
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smp_group[0] = 0x900000003ff01000;
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smp_group[1] = 0x900010003ff05000;
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smp_group[2] = 0x900020003ff09000;
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smp_group[3] = 0x900030003ff0d000;
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loongson_chipcfg[0] = 0x900000001fe00180;
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loongson_chipcfg[1] = 0x900020001fe00180;
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loongson_chipcfg[2] = 0x900040001fe00180;
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loongson_chipcfg[3] = 0x900060001fe00180;
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loongson_freqctrl[0] = 0x900000001fe001d0;
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loongson_freqctrl[1] = 0x900020001fe001d0;
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loongson_freqctrl[2] = 0x900040001fe001d0;
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loongson_freqctrl[3] = 0x900060001fe001d0;
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loongson_sysconf.ht_control_base = 0x90001EFDFB000000;
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cpuhotplug_workaround = 1;
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} else {
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loongson_sysconf.cores_per_node = 1;
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loongson_sysconf.cores_per_package = 1;
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loongson_chipcfg[0] = 0x900000001fe00180;
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}
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loongson_sysconf.nr_cpus = ecpu->nr_cpus;
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if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
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loongson_sysconf.nr_cpus = NR_CPUS;
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loongson_sysconf.nr_nodes = (loongson_sysconf.nr_cpus +
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loongson_sysconf.cores_per_node - 1) /
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loongson_sysconf.cores_per_node;
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loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
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loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
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loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
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loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
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if (loongson_sysconf.dma_mask_bits < 32 ||
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loongson_sysconf.dma_mask_bits > 64)
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loongson_sysconf.dma_mask_bits = 32;
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loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
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loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
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loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;
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loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
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pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
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loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
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loongson_sysconf.vgabios_addr);
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#endif
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if (cpu_clock_freq == 0) {
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processor_id = (¤t_cpu_data)->processor_id;
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switch (processor_id & PRID_REV_MASK) {
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case PRID_REV_LOONGSON2E:
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cpu_clock_freq = 533080000;
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break;
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case PRID_REV_LOONGSON2F:
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cpu_clock_freq = 797000000;
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break;
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case PRID_REV_LOONGSON3A:
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cpu_clock_freq = 900000000;
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break;
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case PRID_REV_LOONGSON3B_R1:
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case PRID_REV_LOONGSON3B_R2:
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cpu_clock_freq = 1000000000;
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break;
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default:
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cpu_clock_freq = 100000000;
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break;
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}
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}
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pr_info("CpuClock = %u\n", cpu_clock_freq);
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}
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