mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 16:48:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
440
arch/mips/mm/c-tx39.c
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440
arch/mips/mm/c-tx39.c
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@ -0,0 +1,440 @@
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/*
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* r2300.c: R2000 and R3000 specific mmu/cache code.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*
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* with a lot of changes to make this thing work for R3000s
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* Tx39XX R4k style caches added. HK
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* Copyright (C) 1998, 1999, 2000 Harald Koerfgen
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* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <asm/cacheops.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/mmu_context.h>
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#include <asm/isadep.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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/* For R3000 cores with R4000 style caches */
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static unsigned long icache_size, dcache_size; /* Size in bytes */
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#include <asm/r4kcache.h>
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extern int r3k_have_wired_reg; /* in r3k-tlb.c */
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/* This sequence is required to ensure icache is disabled immediately */
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#define TX39_STOP_STREAMING() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"b 1f\n\t" \
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"nop\n\t" \
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"1:\n\t" \
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".set pop" \
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)
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/* TX39H-style cache flush routines. */
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static void tx39h_flush_icache_all(void)
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{
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unsigned long flags, config;
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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blast_icache16();
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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/* Catch bad driver code */
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BUG_ON(size == 0);
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iob();
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blast_inv_dcache_range(addr, addr + size);
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}
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/* TX39H2,TX39H3 */
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static inline void tx39_blast_dcache_page(unsigned long addr)
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{
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if (current_cpu_type() != CPU_TX3912)
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blast_dcache16_page(addr);
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}
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static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
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{
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blast_dcache16_page_indexed(addr);
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}
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static inline void tx39_blast_dcache(void)
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{
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blast_dcache16();
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}
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static inline void tx39_blast_icache_page(unsigned long addr)
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{
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unsigned long flags, config;
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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blast_icache16_page(addr);
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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static inline void tx39_blast_icache_page_indexed(unsigned long addr)
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{
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unsigned long flags, config;
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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blast_icache16_page_indexed(addr);
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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static inline void tx39_blast_icache(void)
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{
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unsigned long flags, config;
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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blast_icache16();
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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static void tx39__flush_cache_vmap(void)
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{
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tx39_blast_dcache();
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}
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static void tx39__flush_cache_vunmap(void)
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{
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tx39_blast_dcache();
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}
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static inline void tx39_flush_cache_all(void)
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{
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if (!cpu_has_dc_aliases)
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return;
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tx39_blast_dcache();
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}
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static inline void tx39___flush_cache_all(void)
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{
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tx39_blast_dcache();
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tx39_blast_icache();
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}
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static void tx39_flush_cache_mm(struct mm_struct *mm)
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{
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if (!cpu_has_dc_aliases)
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return;
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if (cpu_context(smp_processor_id(), mm) != 0)
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tx39_blast_dcache();
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}
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static void tx39_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (!cpu_has_dc_aliases)
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return;
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if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
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return;
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tx39_blast_dcache();
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}
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static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
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{
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int exec = vma->vm_flags & VM_EXEC;
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struct mm_struct *mm = vma->vm_mm;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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/*
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* If ownes no valid ASID yet, cannot possibly have gotten
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* this page into the cache.
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*/
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if (cpu_context(smp_processor_id(), mm) == 0)
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return;
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page &= PAGE_MASK;
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pgdp = pgd_offset(mm, page);
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pudp = pud_offset(pgdp, page);
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pmdp = pmd_offset(pudp, page);
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ptep = pte_offset(pmdp, page);
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/*
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* If the page isn't marked valid, the page cannot possibly be
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* in the cache.
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*/
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if (!(pte_val(*ptep) & _PAGE_PRESENT))
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return;
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/*
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* Doing flushes for another ASID than the current one is
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* too difficult since stupid R4k caches do a TLB translation
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* for every cache flush operation. So we do indexed flushes
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* in that case, which doesn't overly flush the cache too much.
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*/
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if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
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if (cpu_has_dc_aliases || exec)
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tx39_blast_dcache_page(page);
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if (exec)
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tx39_blast_icache_page(page);
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return;
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}
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/*
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* Do indexed flush, too much work to get the (possible) TLB refills
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* to work correctly.
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*/
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if (cpu_has_dc_aliases || exec)
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tx39_blast_dcache_page_indexed(page);
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if (exec)
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tx39_blast_icache_page_indexed(page);
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}
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static void local_tx39_flush_data_cache_page(void * addr)
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{
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tx39_blast_dcache_page((unsigned long)addr);
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}
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static void tx39_flush_data_cache_page(unsigned long addr)
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{
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tx39_blast_dcache_page(addr);
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}
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static void tx39_flush_icache_range(unsigned long start, unsigned long end)
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{
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if (end - start > dcache_size)
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tx39_blast_dcache();
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else
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protected_blast_dcache_range(start, end);
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if (end - start > icache_size)
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tx39_blast_icache();
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else {
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unsigned long flags, config;
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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protected_blast_icache_range(start, end);
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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}
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static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
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{
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BUG();
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}
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static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end;
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if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
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end = addr + size;
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do {
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tx39_blast_dcache_page(addr);
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addr += PAGE_SIZE;
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} while(addr != end);
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} else if (size > dcache_size) {
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tx39_blast_dcache();
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} else {
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blast_dcache_range(addr, addr + size);
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}
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}
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static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
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{
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unsigned long end;
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if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
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end = addr + size;
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do {
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tx39_blast_dcache_page(addr);
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addr += PAGE_SIZE;
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} while(addr != end);
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} else if (size > dcache_size) {
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tx39_blast_dcache();
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} else {
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blast_inv_dcache_range(addr, addr + size);
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}
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}
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static void tx39_flush_cache_sigtramp(unsigned long addr)
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{
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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unsigned long config;
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unsigned long flags;
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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/* disable icache (set ICE#) */
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local_irq_save(flags);
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config = read_c0_conf();
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write_c0_conf(config & ~TX39_CONF_ICE);
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TX39_STOP_STREAMING();
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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write_c0_conf(config);
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local_irq_restore(flags);
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}
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static __init void tx39_probe_cache(void)
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{
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unsigned long config;
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config = read_c0_conf();
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icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
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TX39_CONF_ICS_SHIFT));
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dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
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TX39_CONF_DCS_SHIFT));
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current_cpu_data.icache.linesz = 16;
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switch (current_cpu_type()) {
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case CPU_TX3912:
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current_cpu_data.icache.ways = 1;
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current_cpu_data.dcache.ways = 1;
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current_cpu_data.dcache.linesz = 4;
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break;
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case CPU_TX3927:
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current_cpu_data.icache.ways = 2;
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current_cpu_data.dcache.ways = 2;
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current_cpu_data.dcache.linesz = 16;
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break;
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case CPU_TX3922:
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default:
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current_cpu_data.icache.ways = 1;
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current_cpu_data.dcache.ways = 1;
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current_cpu_data.dcache.linesz = 16;
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break;
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}
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}
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void tx39_cache_init(void)
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{
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extern void build_clear_page(void);
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extern void build_copy_page(void);
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unsigned long config;
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config = read_c0_conf();
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config &= ~TX39_CONF_WBON;
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write_c0_conf(config);
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tx39_probe_cache();
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switch (current_cpu_type()) {
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case CPU_TX3912:
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/* TX39/H core (writethru direct-map cache) */
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__flush_cache_vmap = tx39__flush_cache_vmap;
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__flush_cache_vunmap = tx39__flush_cache_vunmap;
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flush_cache_all = tx39h_flush_icache_all;
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__flush_cache_all = tx39h_flush_icache_all;
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flush_cache_mm = (void *) tx39h_flush_icache_all;
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flush_cache_range = (void *) tx39h_flush_icache_all;
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flush_cache_page = (void *) tx39h_flush_icache_all;
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flush_icache_range = (void *) tx39h_flush_icache_all;
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local_flush_icache_range = (void *) tx39h_flush_icache_all;
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flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
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local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
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flush_data_cache_page = (void *) tx39h_flush_icache_all;
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_dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
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shm_align_mask = PAGE_SIZE - 1;
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break;
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case CPU_TX3922:
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case CPU_TX3927:
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default:
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/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
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r3k_have_wired_reg = 1;
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write_c0_wired(0); /* set 8 on reset... */
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/* board-dependent init code may set WBON */
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__flush_cache_vmap = tx39__flush_cache_vmap;
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__flush_cache_vunmap = tx39__flush_cache_vunmap;
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flush_cache_all = tx39_flush_cache_all;
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__flush_cache_all = tx39___flush_cache_all;
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flush_cache_mm = tx39_flush_cache_mm;
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flush_cache_range = tx39_flush_cache_range;
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flush_cache_page = tx39_flush_cache_page;
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flush_icache_range = tx39_flush_icache_range;
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local_flush_icache_range = tx39_flush_icache_range;
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__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
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flush_cache_sigtramp = tx39_flush_cache_sigtramp;
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local_flush_data_cache_page = local_tx39_flush_data_cache_page;
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flush_data_cache_page = tx39_flush_data_cache_page;
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_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
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_dma_cache_wback = tx39_dma_cache_wback_inv;
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_dma_cache_inv = tx39_dma_cache_inv;
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shm_align_mask = max_t(unsigned long,
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(dcache_size / current_cpu_data.dcache.ways) - 1,
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PAGE_SIZE - 1);
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break;
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}
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current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
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current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
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current_cpu_data.icache.sets =
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current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
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current_cpu_data.dcache.sets =
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current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
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if (current_cpu_data.dcache.waysize > PAGE_SIZE)
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current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
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current_cpu_data.icache.waybit = 0;
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current_cpu_data.dcache.waybit = 0;
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printk("Primary instruction cache %ldkB, linesize %d bytes\n",
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icache_size >> 10, current_cpu_data.icache.linesz);
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printk("Primary data cache %ldkB, linesize %d bytes\n",
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dcache_size >> 10, current_cpu_data.dcache.linesz);
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build_clear_page();
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build_copy_page();
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tx39h_flush_icache_all();
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}
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