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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 07:38:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
289
arch/mips/mti-malta/malta-setup.c
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289
arch/mips/mti-malta/malta-setup.c
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2008 Dmitri Vorobiev
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/screen_info.h>
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#include <linux/time.h>
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#include <asm/fw/fw.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/dma.h>
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#include <asm/traps.h>
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#ifdef CONFIG_VT
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#include <linux/console.h>
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#endif
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extern void malta_be_init(void);
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extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
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static struct resource standard_io_resources[] = {
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{
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.name = "dma1",
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.start = 0x00,
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.end = 0x1f,
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.flags = IORESOURCE_BUSY
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},
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{
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.name = "timer",
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.start = 0x40,
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.end = 0x5f,
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.flags = IORESOURCE_BUSY
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},
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{
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.name = "keyboard",
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.start = 0x60,
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.end = 0x6f,
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.flags = IORESOURCE_BUSY
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},
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{
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.name = "dma page reg",
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.start = 0x80,
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.end = 0x8f,
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.flags = IORESOURCE_BUSY
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},
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{
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.name = "dma2",
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.start = 0xc0,
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.end = 0xdf,
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.flags = IORESOURCE_BUSY
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},
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};
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const char *get_system_type(void)
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{
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return "MIPS Malta";
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}
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const char display_string[] = " LINUX ON MALTA ";
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#ifdef CONFIG_BLK_DEV_FD
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static void __init fd_activate(void)
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{
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/*
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* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
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* Controller.
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* Done by YAMON 2.00 onwards
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*/
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/* Entering config state. */
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SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
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/* Activate floppy controller. */
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SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
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SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
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SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
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SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
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/* Exit config state. */
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SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
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}
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#endif
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static int __init plat_enable_iocoherency(void)
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{
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int supported = 0;
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if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
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if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
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pr_info("Enabled Bonito CPU coherency\n");
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supported = 1;
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}
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if (strstr(fw_getcmdline(), "iobcuncached")) {
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BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
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~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Disabled Bonito IOBC coherency\n");
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} else {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG |=
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(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Enabled Bonito IOBC coherency\n");
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}
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} else if (mips_cm_numiocu() != 0) {
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/* Nothing special needs to be done to enable coherency */
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pr_info("CMP IOCU detected\n");
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if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
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pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
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return 0;
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}
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supported = 1;
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}
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hw_coherentio = supported;
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return supported;
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}
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static void __init plat_setup_iocoherency(void)
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{
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#ifdef CONFIG_DMA_NONCOHERENT
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/*
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* Kernel has been configured with software coherency
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* but we might choose to turn it off and use hardware
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* coherency instead.
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*/
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if (plat_enable_iocoherency()) {
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if (coherentio == 0)
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pr_info("Hardware DMA cache coherency disabled\n");
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else
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pr_info("Hardware DMA cache coherency enabled\n");
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} else {
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if (coherentio == 1)
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pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
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else
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pr_info("Software DMA cache coherency enabled\n");
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}
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#else
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if (!plat_enable_iocoherency())
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panic("Hardware DMA cache coherency not supported!");
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#endif
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}
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static void __init pci_clock_check(void)
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{
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unsigned int __iomem *jmpr_p =
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(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
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int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
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static const int pciclocks[] __initconst = {
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33, 20, 25, 30, 12, 16, 37, 10
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};
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int pciclock = pciclocks[jmpr];
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char *optptr, *argptr = fw_getcmdline();
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/*
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* If user passed a pci_clock= option, don't tack on another one
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*/
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optptr = strstr(argptr, "pci_clock=");
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if (optptr && (optptr == argptr || optptr[-1] == ' '))
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return;
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if (pciclock != 33) {
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pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
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pciclock);
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argptr += strlen(argptr);
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sprintf(argptr, " pci_clock=%d", pciclock);
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if (pciclock < 20 || pciclock > 66)
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pr_warn("WARNING: IDE timing calculations will be "
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"incorrect\n");
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}
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}
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#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
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static void __init screen_info_setup(void)
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{
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screen_info = (struct screen_info) {
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.orig_x = 0,
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.orig_y = 25,
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.ext_mem_k = 0,
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.orig_video_page = 0,
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.orig_video_mode = 0,
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.orig_video_cols = 80,
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.unused2 = 0,
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.orig_video_ega_bx = 0,
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.unused3 = 0,
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.orig_video_lines = 25,
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.orig_video_isVGA = VIDEO_TYPE_VGAC,
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.orig_video_points = 16
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};
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}
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#endif
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static void __init bonito_quirks_setup(void)
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{
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char *argptr;
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argptr = fw_getcmdline();
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if (strstr(argptr, "debug")) {
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BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
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pr_info("Enabled Bonito debug mode\n");
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} else
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BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
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#ifdef CONFIG_DMA_COHERENT
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if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
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pr_info("Enabled Bonito CPU coherency\n");
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argptr = fw_getcmdline();
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if (strstr(argptr, "iobcuncached")) {
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BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
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~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Disabled Bonito IOBC coherency\n");
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} else {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG |=
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(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Enabled Bonito IOBC coherency\n");
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}
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} else
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panic("Hardware DMA cache coherency not supported");
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#endif
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}
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void __init plat_mem_setup(void)
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{
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unsigned int i;
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if (config_enabled(CONFIG_EVA))
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/* EVA has already been configured in mach-malta/kernel-init.h */
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pr_info("Enhanced Virtual Addressing (EVA) activated\n");
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mips_pcibios_init();
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/* Request I/O space for devices used on the Malta board. */
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for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
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request_resource(&ioport_resource, standard_io_resources+i);
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/*
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* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
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*/
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enable_dma(4);
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#ifdef CONFIG_DMA_COHERENT
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if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
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panic("Hardware DMA cache coherency not supported");
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#endif
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if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
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bonito_quirks_setup();
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plat_setup_iocoherency();
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pci_clock_check();
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#ifdef CONFIG_BLK_DEV_FD
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fd_activate();
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#endif
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#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
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screen_info_setup();
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#endif
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board_be_init = malta_be_init;
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board_be_handler = malta_be_handler;
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}
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