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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
368
arch/mips/paravirt/paravirt-irq.c
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368
arch/mips/paravirt/paravirt-irq.c
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2013 Cavium, Inc.
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*/
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#include <linux/interrupt.h>
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#include <linux/cpumask.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <asm/io.h>
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#define MBOX_BITS_PER_CPU 2
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static int cpunum_for_cpu(int cpu)
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{
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#ifdef CONFIG_SMP
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return cpu_logical_map(cpu);
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#else
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return get_ebase_cpunum();
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#endif
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}
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struct core_chip_data {
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struct mutex core_irq_mutex;
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bool current_en;
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bool desired_en;
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u8 bit;
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};
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static struct core_chip_data irq_core_chip_data[8];
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static void irq_core_ack(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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unsigned int bit = cd->bit;
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/*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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* interrupt code.
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*/
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clear_c0_status(0x100 << bit);
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/* The two user interrupts must be cleared manually. */
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if (bit < 2)
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clear_c0_cause(0x100 << bit);
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}
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static void irq_core_eoi(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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/*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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* interrupt code.
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*/
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set_c0_status(0x100 << cd->bit);
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}
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static void irq_core_set_enable_local(void *arg)
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{
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struct irq_data *data = arg;
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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unsigned int mask = 0x100 << cd->bit;
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/*
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* Interrupts are already disabled, so these are atomic.
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*/
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if (cd->desired_en)
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set_c0_status(mask);
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else
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clear_c0_status(mask);
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}
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static void irq_core_disable(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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cd->desired_en = false;
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}
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static void irq_core_enable(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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cd->desired_en = true;
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}
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static void irq_core_bus_lock(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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mutex_lock(&cd->core_irq_mutex);
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}
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static void irq_core_bus_sync_unlock(struct irq_data *data)
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{
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struct core_chip_data *cd = irq_data_get_irq_chip_data(data);
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if (cd->desired_en != cd->current_en) {
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on_each_cpu(irq_core_set_enable_local, data, 1);
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cd->current_en = cd->desired_en;
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}
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mutex_unlock(&cd->core_irq_mutex);
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}
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static struct irq_chip irq_chip_core = {
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.name = "Core",
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.irq_enable = irq_core_enable,
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.irq_disable = irq_core_disable,
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.irq_ack = irq_core_ack,
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.irq_eoi = irq_core_eoi,
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.irq_bus_lock = irq_core_bus_lock,
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.irq_bus_sync_unlock = irq_core_bus_sync_unlock,
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.irq_cpu_online = irq_core_eoi,
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.irq_cpu_offline = irq_core_ack,
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.flags = IRQCHIP_ONOFFLINE_ENABLED,
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};
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static void __init irq_init_core(void)
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{
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int i;
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int irq;
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struct core_chip_data *cd;
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/* Start with a clean slate */
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clear_c0_status(ST0_IM);
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clear_c0_cause(CAUSEF_IP0 | CAUSEF_IP1);
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for (i = 0; i < ARRAY_SIZE(irq_core_chip_data); i++) {
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cd = irq_core_chip_data + i;
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cd->current_en = false;
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cd->desired_en = false;
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cd->bit = i;
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mutex_init(&cd->core_irq_mutex);
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irq = MIPS_CPU_IRQ_BASE + i;
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switch (i) {
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case 0: /* SW0 */
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case 1: /* SW1 */
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case 5: /* IP5 */
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case 6: /* IP6 */
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case 7: /* IP7 */
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irq_set_chip_data(irq, cd);
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irq_set_chip_and_handler(irq, &irq_chip_core,
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handle_percpu_irq);
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break;
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default:
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break;
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}
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}
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}
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static void __iomem *mips_irq_chip;
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#define MIPS_IRQ_CHIP_NUM_BITS 0
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#define MIPS_IRQ_CHIP_REGS 8
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static int mips_irq_cpu_stride;
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static int mips_irq_chip_reg_raw;
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static int mips_irq_chip_reg_src;
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static int mips_irq_chip_reg_en;
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static int mips_irq_chip_reg_raw_w1s;
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static int mips_irq_chip_reg_raw_w1c;
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static int mips_irq_chip_reg_en_w1s;
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static int mips_irq_chip_reg_en_w1c;
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static void irq_pci_enable(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);
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}
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static void irq_pci_disable(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);
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}
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static void irq_pci_ack(struct irq_data *data)
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{
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}
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static void irq_pci_mask(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);
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}
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static void irq_pci_unmask(struct irq_data *data)
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{
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u32 mask = 1u << data->irq;
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);
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}
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static struct irq_chip irq_chip_pci = {
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.name = "PCI",
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.irq_enable = irq_pci_enable,
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.irq_disable = irq_pci_disable,
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.irq_ack = irq_pci_ack,
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.irq_mask = irq_pci_mask,
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.irq_unmask = irq_pci_unmask,
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};
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static void irq_mbox_all(struct irq_data *data, void __iomem *base)
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{
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int cpu;
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unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
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u32 mask;
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WARN_ON(mbox >= MBOX_BITS_PER_CPU);
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for_each_online_cpu(cpu) {
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unsigned int cpuid = cpunum_for_cpu(cpu);
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mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);
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__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));
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}
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}
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static void irq_mbox_enable(struct irq_data *data)
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{
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irq_mbox_all(data, mips_irq_chip + mips_irq_chip_reg_en_w1s + sizeof(u32));
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}
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static void irq_mbox_disable(struct irq_data *data)
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{
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irq_mbox_all(data, mips_irq_chip + mips_irq_chip_reg_en_w1c + sizeof(u32));
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}
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static void irq_mbox_ack(struct irq_data *data)
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{
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u32 mask;
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unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
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WARN_ON(mbox >= MBOX_BITS_PER_CPU);
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mask = 1 << (get_ebase_cpunum() * MBOX_BITS_PER_CPU + mbox);
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1c + sizeof(u32));
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}
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void irq_mbox_ipi(int cpu, unsigned int actions)
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{
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unsigned int cpuid = cpunum_for_cpu(cpu);
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u32 mask;
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WARN_ON(actions >= (1 << MBOX_BITS_PER_CPU));
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mask = actions << (cpuid * MBOX_BITS_PER_CPU);
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__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1s + sizeof(u32));
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}
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static void irq_mbox_cpu_onoffline(struct irq_data *data, void __iomem *base)
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{
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unsigned int mbox = data->irq - MIPS_IRQ_MBOX0;
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unsigned int cpuid = get_ebase_cpunum();
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u32 mask;
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WARN_ON(mbox >= MBOX_BITS_PER_CPU);
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mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);
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__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));
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}
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static void irq_mbox_cpu_online(struct irq_data *data)
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{
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irq_mbox_cpu_onoffline(data, mips_irq_chip + mips_irq_chip_reg_en_w1s + sizeof(u32));
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}
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static void irq_mbox_cpu_offline(struct irq_data *data)
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{
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irq_mbox_cpu_onoffline(data, mips_irq_chip + mips_irq_chip_reg_en_w1c + sizeof(u32));
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}
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static struct irq_chip irq_chip_mbox = {
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.name = "MBOX",
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.irq_enable = irq_mbox_enable,
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.irq_disable = irq_mbox_disable,
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.irq_ack = irq_mbox_ack,
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.irq_cpu_online = irq_mbox_cpu_online,
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.irq_cpu_offline = irq_mbox_cpu_offline,
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.flags = IRQCHIP_ONOFFLINE_ENABLED,
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};
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static void __init irq_pci_init(void)
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{
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int i, stride;
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u32 num_bits;
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mips_irq_chip = ioremap(0x1e010000, 4096);
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num_bits = __raw_readl(mips_irq_chip + MIPS_IRQ_CHIP_NUM_BITS);
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stride = 8 * (1 + ((num_bits - 1) / 64));
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pr_notice("mips_irq_chip: %u bits, reg stride: %d\n", num_bits, stride);
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mips_irq_chip_reg_raw = MIPS_IRQ_CHIP_REGS + 0 * stride;
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mips_irq_chip_reg_raw_w1s = MIPS_IRQ_CHIP_REGS + 1 * stride;
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mips_irq_chip_reg_raw_w1c = MIPS_IRQ_CHIP_REGS + 2 * stride;
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mips_irq_chip_reg_src = MIPS_IRQ_CHIP_REGS + 3 * stride;
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mips_irq_chip_reg_en = MIPS_IRQ_CHIP_REGS + 4 * stride;
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mips_irq_chip_reg_en_w1s = MIPS_IRQ_CHIP_REGS + 5 * stride;
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mips_irq_chip_reg_en_w1c = MIPS_IRQ_CHIP_REGS + 6 * stride;
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mips_irq_cpu_stride = stride * 4;
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for (i = 0; i < 4; i++)
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irq_set_chip_and_handler(i + MIPS_IRQ_PCIA, &irq_chip_pci, handle_level_irq);
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for (i = 0; i < 2; i++)
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irq_set_chip_and_handler(i + MIPS_IRQ_MBOX0, &irq_chip_mbox, handle_percpu_irq);
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set_c0_status(STATUSF_IP2);
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}
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static void irq_pci_dispatch(void)
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{
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unsigned int cpuid = get_ebase_cpunum();
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u32 en;
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en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src +
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(cpuid * mips_irq_cpu_stride));
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if (!en) {
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en = __raw_readl(mips_irq_chip + mips_irq_chip_reg_src + (cpuid * mips_irq_cpu_stride) + sizeof(u32));
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en = (en >> (2 * cpuid)) & 3;
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if (!en)
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spurious_interrupt();
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else
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do_IRQ(__ffs(en) + MIPS_IRQ_MBOX0); /* MBOX type */
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} else {
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do_IRQ(__ffs(en));
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}
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}
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void __init arch_init_irq(void)
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{
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irq_init_core();
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irq_pci_init();
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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int ip;
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if (unlikely(!pending)) {
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spurious_interrupt();
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return;
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}
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ip = ffs(pending) - 1 - STATUSB_IP0;
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if (ip == 2)
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irq_pci_dispatch();
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else
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do_IRQ(MIPS_CPU_IRQ_BASE + ip);
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}
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