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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 23:58:51 +01:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
243
arch/mips/pnx833x/common/platform.c
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243
arch/mips/pnx833x/common/platform.c
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/*
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* platform.c: platform support for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* Based on software written by:
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* Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/resource.h>
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#include <linux/serial.h>
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#include <linux/serial_pnx8xxx.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <irq.h>
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#include <irq-mapping.h>
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#include <pnx833x.h>
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static u64 uart_dmamask = DMA_BIT_MASK(32);
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static struct resource pnx833x_uart_resources[] = {
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[0] = {
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.start = PNX833X_UART0_PORTS_START,
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.end = PNX833X_UART0_PORTS_END,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PNX833X_PIC_UART0_INT,
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.end = PNX833X_PIC_UART0_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = PNX833X_UART1_PORTS_START,
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.end = PNX833X_UART1_PORTS_END,
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.flags = IORESOURCE_MEM,
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},
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[3] = {
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.start = PNX833X_PIC_UART1_INT,
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.end = PNX833X_PIC_UART1_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct pnx8xxx_port pnx8xxx_ports[] = {
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[0] = {
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.port = {
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.type = PORT_PNX8XXX,
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.iotype = UPIO_MEM,
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.membase = (void __iomem *)PNX833X_UART0_PORTS_START,
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.mapbase = PNX833X_UART0_PORTS_START,
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.irq = PNX833X_PIC_UART0_INT,
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.uartclk = 3692300,
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.fifosize = 16,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 0,
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},
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},
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[1] = {
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.port = {
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.type = PORT_PNX8XXX,
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.iotype = UPIO_MEM,
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.membase = (void __iomem *)PNX833X_UART1_PORTS_START,
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.mapbase = PNX833X_UART1_PORTS_START,
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.irq = PNX833X_PIC_UART1_INT,
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.uartclk = 3692300,
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.fifosize = 16,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 1,
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},
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},
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};
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static struct platform_device pnx833x_uart_device = {
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.name = "pnx8xxx-uart",
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.id = -1,
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.dev = {
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.dma_mask = &uart_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = pnx8xxx_ports,
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},
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.num_resources = ARRAY_SIZE(pnx833x_uart_resources),
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.resource = pnx833x_uart_resources,
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};
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static u64 ehci_dmamask = DMA_BIT_MASK(32);
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static struct resource pnx833x_usb_ehci_resources[] = {
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[0] = {
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.start = PNX833X_USB_PORTS_START,
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.end = PNX833X_USB_PORTS_END,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PNX833X_PIC_USB_INT,
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.end = PNX833X_PIC_USB_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device pnx833x_usb_ehci_device = {
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.name = "pnx833x-ehci",
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.id = -1,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources),
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.resource = pnx833x_usb_ehci_resources,
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};
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static u64 ethernet_dmamask = DMA_BIT_MASK(32);
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static struct resource pnx833x_ethernet_resources[] = {
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[0] = {
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.start = PNX8335_IP3902_PORTS_START,
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.end = PNX8335_IP3902_PORTS_END,
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.flags = IORESOURCE_MEM,
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},
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#ifdef CONFIG_SOC_PNX8335
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[1] = {
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.start = PNX8335_PIC_ETHERNET_INT,
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.end = PNX8335_PIC_ETHERNET_INT,
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.flags = IORESOURCE_IRQ,
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},
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#endif
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};
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static struct platform_device pnx833x_ethernet_device = {
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.name = "ip3902-eth",
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.id = -1,
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.dev = {
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.dma_mask = ðernet_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
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.resource = pnx833x_ethernet_resources,
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};
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static struct resource pnx833x_sata_resources[] = {
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[0] = {
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.start = PNX8335_SATA_PORTS_START,
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.end = PNX8335_SATA_PORTS_END,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PNX8335_PIC_SATA_INT,
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.end = PNX8335_PIC_SATA_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device pnx833x_sata_device = {
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.name = "pnx833x-sata",
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.id = -1,
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.num_resources = ARRAY_SIZE(pnx833x_sata_resources),
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.resource = pnx833x_sata_resources,
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};
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static void
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pnx833x_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_CLE_MASK));
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else
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writeb(cmd, (void __iomem *)(nandaddr + PNX8335_NAND_ALE_MASK));
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}
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static struct platform_nand_data pnx833x_flash_nand_data = {
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.chip = {
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.nr_chips = 1,
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.chip_delay = 25,
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},
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.ctrl = {
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.cmd_ctrl = pnx833x_flash_nand_cmd_ctrl
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}
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};
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/*
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* Set start to be the correct address (PNX8335_NAND_BASE with no 0xb!!),
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* 12 bytes more seems to be the standard that allows for NAND access.
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*/
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static struct resource pnx833x_flash_nand_resource = {
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.start = PNX8335_NAND_BASE,
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.end = PNX8335_NAND_BASE + 12,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device pnx833x_flash_nand = {
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.name = "gen_nand",
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.id = -1,
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.num_resources = 1,
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.resource = &pnx833x_flash_nand_resource,
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.dev = {
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.platform_data = &pnx833x_flash_nand_data,
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},
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};
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static struct platform_device *pnx833x_platform_devices[] __initdata = {
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&pnx833x_uart_device,
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&pnx833x_usb_ehci_device,
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&pnx833x_ethernet_device,
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&pnx833x_sata_device,
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&pnx833x_flash_nand,
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};
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static int __init pnx833x_platform_init(void)
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{
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int res;
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res = platform_add_devices(pnx833x_platform_devices,
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ARRAY_SIZE(pnx833x_platform_devices));
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return res;
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}
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arch_initcall(pnx833x_platform_init);
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