mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
235
arch/mips/rb532/irq.c
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235
arch/mips/rb532/irq.c
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Copyright 2002 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* stevel@mvista.com or source@mvista.com
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/random.h>
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#include <linux/delay.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-rc32434/irq.h>
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#include <asm/mach-rc32434/gpio.h>
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struct intr_group {
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u32 mask; /* mask of valid bits in pending/mask registers */
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volatile u32 *base_addr;
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};
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#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
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#if (NR_IRQS < RC32434_NR_IRQS)
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#error Too little irqs defined. Did you override <asm/irq.h> ?
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#endif
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static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
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{
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.mask = 0x0000efff,
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.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
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{
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.mask = 0x00001fff,
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.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
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{
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.mask = 0x00000007,
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.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
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{
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.mask = 0x0003ffff,
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.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
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{
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.mask = 0xffffffff,
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.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
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};
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#define READ_PEND(base) (*(base))
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#define READ_MASK(base) (*(base + 2))
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#define WRITE_MASK(base, val) (*(base + 2) = (val))
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static inline int irq_to_group(unsigned int irq_nr)
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{
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return (irq_nr - GROUP0_IRQ_BASE) >> 5;
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}
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static inline int group_to_ip(unsigned int group)
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{
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return group + 2;
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}
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static inline void enable_local_irq(unsigned int ip)
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{
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int ipnum = 0x100 << ip;
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set_c0_status(ipnum);
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}
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static inline void disable_local_irq(unsigned int ip)
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{
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int ipnum = 0x100 << ip;
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clear_c0_status(ipnum);
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}
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static inline void ack_local_irq(unsigned int ip)
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{
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int ipnum = 0x100 << ip;
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clear_c0_cause(ipnum);
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}
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static void rb532_enable_irq(struct irq_data *d)
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{
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unsigned int group, intr_bit, irq_nr = d->irq;
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int ip = irq_nr - GROUP0_IRQ_BASE;
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volatile unsigned int *addr;
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if (ip < 0)
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enable_local_irq(irq_nr);
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else {
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group = ip >> 5;
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ip &= (1 << 5) - 1;
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intr_bit = 1 << ip;
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enable_local_irq(group_to_ip(group));
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addr = intr_group[group].base_addr;
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WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
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}
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}
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static void rb532_disable_irq(struct irq_data *d)
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{
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unsigned int group, intr_bit, mask, irq_nr = d->irq;
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int ip = irq_nr - GROUP0_IRQ_BASE;
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volatile unsigned int *addr;
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if (ip < 0) {
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disable_local_irq(irq_nr);
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} else {
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group = ip >> 5;
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ip &= (1 << 5) - 1;
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intr_bit = 1 << ip;
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addr = intr_group[group].base_addr;
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mask = READ_MASK(addr);
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mask |= intr_bit;
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WRITE_MASK(addr, mask);
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/* There is a maximum of 14 GPIO interrupts */
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if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
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rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
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/*
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* if there are no more interrupts enabled in this
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* group, disable corresponding IP
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*/
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if (mask == intr_group[group].mask)
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disable_local_irq(group_to_ip(group));
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}
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}
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static void rb532_mask_and_ack_irq(struct irq_data *d)
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{
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rb532_disable_irq(d);
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ack_local_irq(group_to_ip(irq_to_group(d->irq)));
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}
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static int rb532_set_type(struct irq_data *d, unsigned type)
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{
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int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
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int group = irq_to_group(d->irq);
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if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
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return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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rb532_gpio_set_ilevel(1, gpio);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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rb532_gpio_set_ilevel(0, gpio);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_chip rc32434_irq_type = {
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.name = "RB532",
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.irq_ack = rb532_disable_irq,
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.irq_mask = rb532_disable_irq,
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.irq_mask_ack = rb532_mask_and_ack_irq,
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.irq_unmask = rb532_enable_irq,
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.irq_set_type = rb532_set_type,
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};
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void __init arch_init_irq(void)
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{
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int i;
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pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
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for (i = 0; i < RC32434_NR_IRQS; i++)
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irq_set_chip_and_handler(i, &rc32434_irq_type,
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handle_level_irq);
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}
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/* Main Interrupt dispatcher */
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int ip, pend, group;
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volatile unsigned int *addr;
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unsigned int cp0_cause = read_c0_cause() & read_c0_status();
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if (cp0_cause & CAUSEF_IP7) {
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do_IRQ(7);
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} else {
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ip = (cp0_cause & 0x7c00);
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if (ip) {
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group = 21 + (fls(ip) - 32);
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addr = intr_group[group].base_addr;
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pend = READ_PEND(addr);
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pend &= ~READ_MASK(addr); /* only unmasked interrupts */
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pend = 39 + (fls(pend) - 32);
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do_IRQ((group << 5) + pend);
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}
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}
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}
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