mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 09:08:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
7
arch/mips/sgi-ip32/Makefile
Normal file
7
arch/mips/sgi-ip32/Makefile
Normal file
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@ -0,0 +1,7 @@
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#
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# Makefile for the SGI specific kernel interface routines
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# under Linux.
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#
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obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \
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crime.o ip32-memory.o
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11
arch/mips/sgi-ip32/Platform
Normal file
11
arch/mips/sgi-ip32/Platform
Normal file
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@ -0,0 +1,11 @@
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#
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# SGI-IP32 (O2)
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#
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# Set the load address to >= 80069000 if you want to leave space for symmon,
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# 0xffffffff80004000 for production kernels. Note that the value must be aligned to
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# a multiple of the kernel stack size or the handling of the current variable
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# will break.
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#
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platform-$(CONFIG_SGI_IP32) += sgi-ip32/
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cflags-$(CONFIG_SGI_IP32) += -I$(srctree)/arch/mips/include/asm/mach-ip32
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load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
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103
arch/mips/sgi-ip32/crime.c
Normal file
103
arch/mips/sgi-ip32/crime.c
Normal file
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|
@ -0,0 +1,103 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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||||
* for more details.
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||||
*
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* Copyright (C) 2001, 2003 Keith M Wesolowski
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* Copyright (C) 2005 Ilya A. Volynets <ilya@total-knowledge.com>
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/page.h>
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#include <asm/ip32/crime.h>
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#include <asm/ip32/mace.h>
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struct sgi_crime __iomem *crime;
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struct sgi_mace __iomem *mace;
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EXPORT_SYMBOL_GPL(mace);
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void __init crime_init(void)
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{
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unsigned int id, rev;
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const int field = 2 * sizeof(unsigned long);
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set_io_port_base((unsigned long) ioremap(MACEPCI_LOW_IO, 0x2000000));
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crime = ioremap(CRIME_BASE, sizeof(struct sgi_crime));
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mace = ioremap(MACE_BASE, sizeof(struct sgi_mace));
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id = crime->id;
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rev = id & CRIME_ID_REV;
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id = (id & CRIME_ID_IDBITS) >> 4;
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printk(KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n",
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id, rev, field, (unsigned long) CRIME_BASE);
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}
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irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
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{
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unsigned long stat, addr;
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int fatal = 0;
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stat = crime->mem_error_stat & CRIME_MEM_ERROR_STAT_MASK;
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addr = crime->mem_error_addr & CRIME_MEM_ERROR_ADDR_MASK;
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printk("CRIME memory error at 0x%08lx ST 0x%08lx<", addr, stat);
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if (stat & CRIME_MEM_ERROR_INV)
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printk("INV,");
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if (stat & CRIME_MEM_ERROR_ECC) {
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unsigned long ecc_syn =
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crime->mem_ecc_syn & CRIME_MEM_ERROR_ECC_SYN_MASK;
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unsigned long ecc_gen =
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crime->mem_ecc_chk & CRIME_MEM_ERROR_ECC_CHK_MASK;
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printk("ECC,SYN=0x%08lx,GEN=0x%08lx,", ecc_syn, ecc_gen);
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}
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if (stat & CRIME_MEM_ERROR_MULTIPLE) {
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fatal = 1;
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printk("MULTIPLE,");
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}
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if (stat & CRIME_MEM_ERROR_HARD_ERR) {
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fatal = 1;
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printk("HARD,");
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}
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if (stat & CRIME_MEM_ERROR_SOFT_ERR)
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printk("SOFT,");
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if (stat & CRIME_MEM_ERROR_CPU_ACCESS)
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printk("CPU,");
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if (stat & CRIME_MEM_ERROR_VICE_ACCESS)
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printk("VICE,");
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if (stat & CRIME_MEM_ERROR_GBE_ACCESS)
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printk("GBE,");
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if (stat & CRIME_MEM_ERROR_RE_ACCESS)
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printk("RE,REID=0x%02lx,", (stat & CRIME_MEM_ERROR_RE_ID)>>8);
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if (stat & CRIME_MEM_ERROR_MACE_ACCESS)
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printk("MACE,MACEID=0x%02lx,", stat & CRIME_MEM_ERROR_MACE_ID);
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crime->mem_error_stat = 0;
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if (fatal) {
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printk("FATAL>\n");
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panic("Fatal memory error.");
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} else
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printk("NONFATAL>\n");
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return IRQ_HANDLED;
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}
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irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
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{
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unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
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unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
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addr <<= 2;
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printk("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat);
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crime->cpu_error_stat = 0;
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return IRQ_HANDLED;
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}
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36
arch/mips/sgi-ip32/ip32-berr.c
Normal file
36
arch/mips/sgi-ip32/ip32-berr.c
Normal file
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@ -0,0 +1,36 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 by Silicon Graphics
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* Copyright (C) 2002 Maciej W. Rozycki
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <asm/traps.h>
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#include <asm/uaccess.h>
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#include <asm/addrspace.h>
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#include <asm/ptrace.h>
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#include <asm/tlbdebug.h>
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static int ip32_be_handler(struct pt_regs *regs, int is_fixup)
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{
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int data = regs->cp0_cause & 4;
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if (is_fixup)
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return MIPS_BE_FIXUP;
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printk("Got %cbe at 0x%lx\n", data ? 'd' : 'i', regs->cp0_epc);
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show_regs(regs);
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dump_tlb_all();
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while(1);
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force_sig(SIGBUS, current);
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}
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void __init ip32_be_init(void)
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{
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board_be_handler = ip32_be_handler;
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}
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504
arch/mips/sgi-ip32/ip32-irq.c
Normal file
504
arch/mips/sgi-ip32/ip32-irq.c
Normal file
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@ -0,0 +1,504 @@
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/*
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* Code to handle IP32 IRQs
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Harald Koerfgen
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* Copyright (C) 2001 Keith M Wesolowski
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*/
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/random.h>
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#include <linux/sched.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/signal.h>
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#include <asm/time.h>
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#include <asm/ip32/crime.h>
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#include <asm/ip32/mace.h>
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#include <asm/ip32/ip32_ints.h>
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/* issue a PIO read to make sure no PIO writes are pending */
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static void inline flush_crime_bus(void)
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{
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crime->control;
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}
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static void inline flush_mace_bus(void)
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{
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mace->perif.ctrl.misc;
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}
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/*
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* O2 irq map
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*
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* IP0 -> software (ignored)
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* IP1 -> software (ignored)
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* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
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* IP3 -> (irq1) X unknown
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* IP4 -> (irq2) X unknown
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* IP5 -> (irq3) X unknown
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* IP6 -> (irq4) X unknown
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* IP7 -> (irq5) 7 CPU count/compare timer (system timer)
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*
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* crime: (C)
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*
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* CRIME_INT_STAT 31:0:
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*
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* 0 -> 8 Video in 1
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* 1 -> 9 Video in 2
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* 2 -> 10 Video out
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* 3 -> 11 Mace ethernet
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* 4 -> S SuperIO sub-interrupt
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* 5 -> M Miscellaneous sub-interrupt
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* 6 -> A Audio sub-interrupt
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* 7 -> 15 PCI bridge errors
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* 8 -> 16 PCI SCSI aic7xxx 0
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* 9 -> 17 PCI SCSI aic7xxx 1
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* 10 -> 18 PCI slot 0
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* 11 -> 19 unused (PCI slot 1)
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* 12 -> 20 unused (PCI slot 2)
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* 13 -> 21 unused (PCI shared 0)
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* 14 -> 22 unused (PCI shared 1)
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* 15 -> 23 unused (PCI shared 2)
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* 16 -> 24 GBE0 (E)
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* 17 -> 25 GBE1 (E)
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* 18 -> 26 GBE2 (E)
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* 19 -> 27 GBE3 (E)
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* 20 -> 28 CPU errors
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* 21 -> 29 Memory errors
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* 22 -> 30 RE empty edge (E)
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* 23 -> 31 RE full edge (E)
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* 24 -> 32 RE idle edge (E)
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* 25 -> 33 RE empty level
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* 26 -> 34 RE full level
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* 27 -> 35 RE idle level
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* 28 -> 36 unused (software 0) (E)
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* 29 -> 37 unused (software 1) (E)
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* 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
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* 31 -> 39 VICE
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*
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* S, M, A: Use the MACE ISA interrupt register
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* MACE_ISA_INT_STAT 31:0
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*
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* 0-7 -> 40-47 Audio
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* 8 -> 48 RTC
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* 9 -> 49 Keyboard
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* 10 -> X Keyboard polled
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* 11 -> 51 Mouse
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* 12 -> X Mouse polled
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* 13-15 -> 53-55 Count/compare timers
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* 16-19 -> 56-59 Parallel (16 E)
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* 20-25 -> 60-62 Serial 1 (22 E)
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* 26-31 -> 66-71 Serial 2 (28 E)
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*
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* Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
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* different IRQ map than IRIX uses, but that's OK as Linux irq handling
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* is quite different anyway.
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*/
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|
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/* Some initial interrupts to set up */
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extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
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extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
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static struct irqaction memerr_irq = {
|
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.handler = crime_memerr_intr,
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.name = "CRIME memory error",
|
||||
};
|
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|
||||
static struct irqaction cpuerr_irq = {
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||||
.handler = crime_cpuerr_intr,
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.name = "CRIME CPU error",
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};
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|
||||
/*
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* This is for pure CRIME interrupts - ie not MACE. The advantage?
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* We get to split the register in half and do faster lookups.
|
||||
*/
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||||
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static uint64_t crime_mask;
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||||
|
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static inline void crime_enable_irq(struct irq_data *d)
|
||||
{
|
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unsigned int bit = d->irq - CRIME_IRQ_BASE;
|
||||
|
||||
crime_mask |= 1 << bit;
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crime->imask = crime_mask;
|
||||
}
|
||||
|
||||
static inline void crime_disable_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = d->irq - CRIME_IRQ_BASE;
|
||||
|
||||
crime_mask &= ~(1 << bit);
|
||||
crime->imask = crime_mask;
|
||||
flush_crime_bus();
|
||||
}
|
||||
|
||||
static struct irq_chip crime_level_interrupt = {
|
||||
.name = "IP32 CRIME",
|
||||
.irq_mask = crime_disable_irq,
|
||||
.irq_unmask = crime_enable_irq,
|
||||
};
|
||||
|
||||
static void crime_edge_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = d->irq - CRIME_IRQ_BASE;
|
||||
uint64_t crime_int;
|
||||
|
||||
/* Edge triggered interrupts must be cleared. */
|
||||
crime_int = crime->hard_int;
|
||||
crime_int &= ~(1 << bit);
|
||||
crime->hard_int = crime_int;
|
||||
|
||||
crime_disable_irq(d);
|
||||
}
|
||||
|
||||
static struct irq_chip crime_edge_interrupt = {
|
||||
.name = "IP32 CRIME",
|
||||
.irq_ack = crime_edge_mask_and_ack_irq,
|
||||
.irq_mask = crime_disable_irq,
|
||||
.irq_mask_ack = crime_edge_mask_and_ack_irq,
|
||||
.irq_unmask = crime_enable_irq,
|
||||
};
|
||||
|
||||
/*
|
||||
* This is for MACE PCI interrupts. We can decrease bus traffic by masking
|
||||
* as close to the source as possible. This also means we can take the
|
||||
* next chunk of the CRIME register in one piece.
|
||||
*/
|
||||
|
||||
static unsigned long macepci_mask;
|
||||
|
||||
static void enable_macepci_irq(struct irq_data *d)
|
||||
{
|
||||
macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
|
||||
mace->pci.control = macepci_mask;
|
||||
crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
|
||||
crime->imask = crime_mask;
|
||||
}
|
||||
|
||||
static void disable_macepci_irq(struct irq_data *d)
|
||||
{
|
||||
crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
|
||||
crime->imask = crime_mask;
|
||||
flush_crime_bus();
|
||||
macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
|
||||
mace->pci.control = macepci_mask;
|
||||
flush_mace_bus();
|
||||
}
|
||||
|
||||
static struct irq_chip ip32_macepci_interrupt = {
|
||||
.name = "IP32 MACE PCI",
|
||||
.irq_mask = disable_macepci_irq,
|
||||
.irq_unmask = enable_macepci_irq,
|
||||
};
|
||||
|
||||
/* This is used for MACE ISA interrupts. That means bits 4-6 in the
|
||||
* CRIME register.
|
||||
*/
|
||||
|
||||
#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \
|
||||
MACEISA_AUDIO_SC_INT | \
|
||||
MACEISA_AUDIO1_DMAT_INT | \
|
||||
MACEISA_AUDIO1_OF_INT | \
|
||||
MACEISA_AUDIO2_DMAT_INT | \
|
||||
MACEISA_AUDIO2_MERR_INT | \
|
||||
MACEISA_AUDIO3_DMAT_INT | \
|
||||
MACEISA_AUDIO3_MERR_INT)
|
||||
#define MACEISA_MISC_INT (MACEISA_RTC_INT | \
|
||||
MACEISA_KEYB_INT | \
|
||||
MACEISA_KEYB_POLL_INT | \
|
||||
MACEISA_MOUSE_INT | \
|
||||
MACEISA_MOUSE_POLL_INT | \
|
||||
MACEISA_TIMER0_INT | \
|
||||
MACEISA_TIMER1_INT | \
|
||||
MACEISA_TIMER2_INT)
|
||||
#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \
|
||||
MACEISA_PAR_CTXA_INT | \
|
||||
MACEISA_PAR_CTXB_INT | \
|
||||
MACEISA_PAR_MERR_INT | \
|
||||
MACEISA_SERIAL1_INT | \
|
||||
MACEISA_SERIAL1_TDMAT_INT | \
|
||||
MACEISA_SERIAL1_TDMAPR_INT | \
|
||||
MACEISA_SERIAL1_TDMAME_INT | \
|
||||
MACEISA_SERIAL1_RDMAT_INT | \
|
||||
MACEISA_SERIAL1_RDMAOR_INT | \
|
||||
MACEISA_SERIAL2_INT | \
|
||||
MACEISA_SERIAL2_TDMAT_INT | \
|
||||
MACEISA_SERIAL2_TDMAPR_INT | \
|
||||
MACEISA_SERIAL2_TDMAME_INT | \
|
||||
MACEISA_SERIAL2_RDMAT_INT | \
|
||||
MACEISA_SERIAL2_RDMAOR_INT)
|
||||
|
||||
static unsigned long maceisa_mask;
|
||||
|
||||
static void enable_maceisa_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int crime_int = 0;
|
||||
|
||||
pr_debug("maceisa enable: %u\n", d->irq);
|
||||
|
||||
switch (d->irq) {
|
||||
case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
|
||||
crime_int = MACE_AUDIO_INT;
|
||||
break;
|
||||
case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
|
||||
crime_int = MACE_MISC_INT;
|
||||
break;
|
||||
case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
|
||||
crime_int = MACE_SUPERIO_INT;
|
||||
break;
|
||||
}
|
||||
pr_debug("crime_int %08x enabled\n", crime_int);
|
||||
crime_mask |= crime_int;
|
||||
crime->imask = crime_mask;
|
||||
maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
|
||||
mace->perif.ctrl.imask = maceisa_mask;
|
||||
}
|
||||
|
||||
static void disable_maceisa_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int crime_int = 0;
|
||||
|
||||
maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
|
||||
if (!(maceisa_mask & MACEISA_AUDIO_INT))
|
||||
crime_int |= MACE_AUDIO_INT;
|
||||
if (!(maceisa_mask & MACEISA_MISC_INT))
|
||||
crime_int |= MACE_MISC_INT;
|
||||
if (!(maceisa_mask & MACEISA_SUPERIO_INT))
|
||||
crime_int |= MACE_SUPERIO_INT;
|
||||
crime_mask &= ~crime_int;
|
||||
crime->imask = crime_mask;
|
||||
flush_crime_bus();
|
||||
mace->perif.ctrl.imask = maceisa_mask;
|
||||
flush_mace_bus();
|
||||
}
|
||||
|
||||
static void mask_and_ack_maceisa_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned long mace_int;
|
||||
|
||||
/* edge triggered */
|
||||
mace_int = mace->perif.ctrl.istat;
|
||||
mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
|
||||
mace->perif.ctrl.istat = mace_int;
|
||||
|
||||
disable_maceisa_irq(d);
|
||||
}
|
||||
|
||||
static struct irq_chip ip32_maceisa_level_interrupt = {
|
||||
.name = "IP32 MACE ISA",
|
||||
.irq_mask = disable_maceisa_irq,
|
||||
.irq_unmask = enable_maceisa_irq,
|
||||
};
|
||||
|
||||
static struct irq_chip ip32_maceisa_edge_interrupt = {
|
||||
.name = "IP32 MACE ISA",
|
||||
.irq_ack = mask_and_ack_maceisa_irq,
|
||||
.irq_mask = disable_maceisa_irq,
|
||||
.irq_mask_ack = mask_and_ack_maceisa_irq,
|
||||
.irq_unmask = enable_maceisa_irq,
|
||||
};
|
||||
|
||||
/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
|
||||
* bits 0-3 and 7 in the CRIME register.
|
||||
*/
|
||||
|
||||
static void enable_mace_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = d->irq - CRIME_IRQ_BASE;
|
||||
|
||||
crime_mask |= (1 << bit);
|
||||
crime->imask = crime_mask;
|
||||
}
|
||||
|
||||
static void disable_mace_irq(struct irq_data *d)
|
||||
{
|
||||
unsigned int bit = d->irq - CRIME_IRQ_BASE;
|
||||
|
||||
crime_mask &= ~(1 << bit);
|
||||
crime->imask = crime_mask;
|
||||
flush_crime_bus();
|
||||
}
|
||||
|
||||
static struct irq_chip ip32_mace_interrupt = {
|
||||
.name = "IP32 MACE",
|
||||
.irq_mask = disable_mace_irq,
|
||||
.irq_unmask = enable_mace_irq,
|
||||
};
|
||||
|
||||
static void ip32_unknown_interrupt(void)
|
||||
{
|
||||
printk("Unknown interrupt occurred!\n");
|
||||
printk("cp0_status: %08x\n", read_c0_status());
|
||||
printk("cp0_cause: %08x\n", read_c0_cause());
|
||||
printk("CRIME intr mask: %016lx\n", crime->imask);
|
||||
printk("CRIME intr status: %016lx\n", crime->istat);
|
||||
printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
|
||||
printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
|
||||
printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
|
||||
printk("MACE PCI control register: %08x\n", mace->pci.control);
|
||||
|
||||
printk("Register dump:\n");
|
||||
show_regs(get_irq_regs());
|
||||
|
||||
printk("Please mail this report to linux-mips@linux-mips.org\n");
|
||||
printk("Spinning...");
|
||||
while(1) ;
|
||||
}
|
||||
|
||||
/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
|
||||
/* change this to loop over all edge-triggered irqs, exception masked out ones */
|
||||
static void ip32_irq0(void)
|
||||
{
|
||||
uint64_t crime_int;
|
||||
int irq = 0;
|
||||
|
||||
/*
|
||||
* Sanity check interrupt numbering enum.
|
||||
* MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
|
||||
* chained.
|
||||
*/
|
||||
BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
|
||||
BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
|
||||
|
||||
crime_int = crime->istat & crime_mask;
|
||||
|
||||
/* crime sometime delivers spurious interrupts, ignore them */
|
||||
if (unlikely(crime_int == 0))
|
||||
return;
|
||||
|
||||
irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
|
||||
|
||||
if (crime_int & CRIME_MACEISA_INT_MASK) {
|
||||
unsigned long mace_int = mace->perif.ctrl.istat;
|
||||
irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
|
||||
}
|
||||
|
||||
pr_debug("*irq %u*\n", irq);
|
||||
do_IRQ(irq);
|
||||
}
|
||||
|
||||
static void ip32_irq1(void)
|
||||
{
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq2(void)
|
||||
{
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq3(void)
|
||||
{
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq4(void)
|
||||
{
|
||||
ip32_unknown_interrupt();
|
||||
}
|
||||
|
||||
static void ip32_irq5(void)
|
||||
{
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (likely(pending & IE_IRQ0))
|
||||
ip32_irq0();
|
||||
else if (unlikely(pending & IE_IRQ1))
|
||||
ip32_irq1();
|
||||
else if (unlikely(pending & IE_IRQ2))
|
||||
ip32_irq2();
|
||||
else if (unlikely(pending & IE_IRQ3))
|
||||
ip32_irq3();
|
||||
else if (unlikely(pending & IE_IRQ4))
|
||||
ip32_irq4();
|
||||
else if (likely(pending & IE_IRQ5))
|
||||
ip32_irq5();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
unsigned int irq;
|
||||
|
||||
/* Install our interrupt handler, then clear and disable all
|
||||
* CRIME and MACE interrupts. */
|
||||
crime->imask = 0;
|
||||
crime->hard_int = 0;
|
||||
crime->soft_int = 0;
|
||||
mace->perif.ctrl.istat = 0;
|
||||
mace->perif.ctrl.imask = 0;
|
||||
|
||||
mips_cpu_irq_init();
|
||||
for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
|
||||
switch (irq) {
|
||||
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
|
||||
irq_set_chip_and_handler_name(irq,
|
||||
&ip32_mace_interrupt,
|
||||
handle_level_irq,
|
||||
"level");
|
||||
break;
|
||||
|
||||
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
|
||||
irq_set_chip_and_handler_name(irq,
|
||||
&ip32_macepci_interrupt,
|
||||
handle_level_irq,
|
||||
"level");
|
||||
break;
|
||||
|
||||
case CRIME_CPUERR_IRQ:
|
||||
case CRIME_MEMERR_IRQ:
|
||||
irq_set_chip_and_handler_name(irq,
|
||||
&crime_level_interrupt,
|
||||
handle_level_irq,
|
||||
"level");
|
||||
break;
|
||||
|
||||
case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
|
||||
case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
|
||||
case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
|
||||
case CRIME_VICE_IRQ:
|
||||
irq_set_chip_and_handler_name(irq,
|
||||
&crime_edge_interrupt,
|
||||
handle_edge_irq,
|
||||
"edge");
|
||||
break;
|
||||
|
||||
case MACEISA_PARALLEL_IRQ:
|
||||
case MACEISA_SERIAL1_TDMAPR_IRQ:
|
||||
case MACEISA_SERIAL2_TDMAPR_IRQ:
|
||||
irq_set_chip_and_handler_name(irq,
|
||||
&ip32_maceisa_edge_interrupt,
|
||||
handle_edge_irq,
|
||||
"edge");
|
||||
break;
|
||||
|
||||
default:
|
||||
irq_set_chip_and_handler_name(irq,
|
||||
&ip32_maceisa_level_interrupt,
|
||||
handle_level_irq,
|
||||
"level");
|
||||
break;
|
||||
}
|
||||
}
|
||||
setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
|
||||
setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
|
||||
|
||||
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
|
||||
change_c0_status(ST0_IM, ALLINTS);
|
||||
}
|
||||
48
arch/mips/sgi-ip32/ip32-memory.c
Normal file
48
arch/mips/sgi-ip32/ip32-memory.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2003 Keith M Wesolowski
|
||||
* Copyright (C) 2005 Ilya A. Volynets (Total Knowledge)
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <asm/ip32/crime.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/pgalloc.h>
|
||||
|
||||
extern void crime_init(void);
|
||||
|
||||
void __init prom_meminit(void)
|
||||
{
|
||||
u64 base, size;
|
||||
int bank;
|
||||
|
||||
crime_init();
|
||||
|
||||
for (bank=0; bank < CRIME_MAXBANKS; bank++) {
|
||||
u64 bankctl = crime->bank_ctrl[bank];
|
||||
base = (bankctl & CRIME_MEM_BANK_CONTROL_ADDR) << 25;
|
||||
if (bank != 0 && base == 0)
|
||||
continue;
|
||||
size = (bankctl & CRIME_MEM_BANK_CONTROL_SDRAM_SIZE) ? 128 : 32;
|
||||
size <<= 20;
|
||||
if (base + size > (256 << 20))
|
||||
base += CRIME_HI_MEM_BASE;
|
||||
|
||||
printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n",
|
||||
bank, base, size >> 20);
|
||||
add_memory_region(base, size, BOOT_MEM_RAM);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
111
arch/mips/sgi-ip32/ip32-platform.c
Normal file
111
arch/mips/sgi-ip32/ip32-platform.c
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_8250.h>
|
||||
|
||||
#include <asm/ip32/mace.h>
|
||||
#include <asm/ip32/ip32_ints.h>
|
||||
|
||||
#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1)
|
||||
#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2)
|
||||
|
||||
#define MACE_PORT(offset,_irq) \
|
||||
{ \
|
||||
.mapbase = MACE_BASE + offset, \
|
||||
.irq = _irq, \
|
||||
.uartclk = 1843200, \
|
||||
.iotype = UPIO_MEM, \
|
||||
.flags = UPF_SKIP_TEST|UPF_IOREMAP, \
|
||||
.regshift = 8, \
|
||||
}
|
||||
|
||||
static struct plat_serial8250_port uart8250_data[] = {
|
||||
MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ),
|
||||
MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ),
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_device uart8250_device = {
|
||||
.name = "serial8250",
|
||||
.id = PLAT8250_DEV_PLATFORM,
|
||||
.dev = {
|
||||
.platform_data = uart8250_data,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init uart8250_init(void)
|
||||
{
|
||||
return platform_device_register(&uart8250_device);
|
||||
}
|
||||
|
||||
device_initcall(uart8250_init);
|
||||
|
||||
static __init int meth_devinit(void)
|
||||
{
|
||||
struct platform_device *pd;
|
||||
int ret;
|
||||
|
||||
pd = platform_device_alloc("meth", -1);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = platform_device_add(pd);
|
||||
if (ret)
|
||||
platform_device_put(pd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
device_initcall(meth_devinit);
|
||||
|
||||
static __init int sgio2audio_devinit(void)
|
||||
{
|
||||
struct platform_device *pd;
|
||||
int ret;
|
||||
|
||||
pd = platform_device_alloc("sgio2audio", -1);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = platform_device_add(pd);
|
||||
if (ret)
|
||||
platform_device_put(pd);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
device_initcall(sgio2audio_devinit);
|
||||
|
||||
static __init int sgio2btns_devinit(void)
|
||||
{
|
||||
return IS_ERR(platform_device_register_simple("sgibtns", -1, NULL, 0));
|
||||
}
|
||||
|
||||
device_initcall(sgio2btns_devinit);
|
||||
|
||||
static struct resource sgio2_cmos_rsrc[] = {
|
||||
{
|
||||
.start = 0x70,
|
||||
.end = 0x71,
|
||||
.flags = IORESOURCE_IO
|
||||
}
|
||||
};
|
||||
|
||||
static __init int sgio2_cmos_devinit(void)
|
||||
{
|
||||
return IS_ERR(platform_device_register_simple("rtc_cmos", -1,
|
||||
sgio2_cmos_rsrc, 1));
|
||||
}
|
||||
|
||||
device_initcall(sgio2_cmos_devinit);
|
||||
|
||||
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2");
|
||||
204
arch/mips/sgi-ip32/ip32-reset.c
Normal file
204
arch/mips/sgi-ip32/ip32-reset.c
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2001 Keith M Wesolowski
|
||||
* Copyright (C) 2001 Paul Mundt
|
||||
* Copyright (C) 2003 Guido Guenther <agx@sigxcpu.org>
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/ds17287rtc.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/wbflush.h>
|
||||
#include <asm/ip32/mace.h>
|
||||
#include <asm/ip32/crime.h>
|
||||
#include <asm/ip32/ip32_ints.h>
|
||||
|
||||
#define POWERDOWN_TIMEOUT 120
|
||||
/*
|
||||
* Blink frequency during reboot grace period and when panicked.
|
||||
*/
|
||||
#define POWERDOWN_FREQ (HZ / 4)
|
||||
#define PANIC_FREQ (HZ / 8)
|
||||
|
||||
static struct timer_list power_timer, blink_timer, debounce_timer;
|
||||
static int has_panicked, shuting_down;
|
||||
|
||||
static void ip32_machine_restart(char *command) __attribute__((noreturn));
|
||||
static void ip32_machine_halt(void) __attribute__((noreturn));
|
||||
static void ip32_machine_power_off(void) __attribute__((noreturn));
|
||||
|
||||
static void ip32_machine_restart(char *cmd)
|
||||
{
|
||||
crime->control = CRIME_CONTROL_HARD_RESET;
|
||||
while (1);
|
||||
}
|
||||
|
||||
static inline void ip32_machine_halt(void)
|
||||
{
|
||||
ip32_machine_power_off();
|
||||
}
|
||||
|
||||
static void ip32_machine_power_off(void)
|
||||
{
|
||||
unsigned char reg_a, xctrl_a, xctrl_b;
|
||||
|
||||
disable_irq(MACEISA_RTC_IRQ);
|
||||
reg_a = CMOS_READ(RTC_REG_A);
|
||||
|
||||
/* setup for kickstart & wake-up (DS12287 Ref. Man. p. 19) */
|
||||
reg_a &= ~DS_REGA_DV2;
|
||||
reg_a |= DS_REGA_DV1;
|
||||
|
||||
CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A);
|
||||
wbflush();
|
||||
xctrl_b = CMOS_READ(DS_B1_XCTRL4B)
|
||||
| DS_XCTRL4B_ABE | DS_XCTRL4B_KFE;
|
||||
CMOS_WRITE(xctrl_b, DS_B1_XCTRL4B);
|
||||
xctrl_a = CMOS_READ(DS_B1_XCTRL4A) & ~DS_XCTRL4A_IFS;
|
||||
CMOS_WRITE(xctrl_a, DS_B1_XCTRL4A);
|
||||
wbflush();
|
||||
/* adios amigos... */
|
||||
CMOS_WRITE(xctrl_a | DS_XCTRL4A_PAB, DS_B1_XCTRL4A);
|
||||
CMOS_WRITE(reg_a, RTC_REG_A);
|
||||
wbflush();
|
||||
while (1);
|
||||
}
|
||||
|
||||
static void power_timeout(unsigned long data)
|
||||
{
|
||||
ip32_machine_power_off();
|
||||
}
|
||||
|
||||
static void blink_timeout(unsigned long data)
|
||||
{
|
||||
unsigned long led = mace->perif.ctrl.misc ^ MACEISA_LED_RED;
|
||||
mace->perif.ctrl.misc = led;
|
||||
mod_timer(&blink_timer, jiffies + data);
|
||||
}
|
||||
|
||||
static void debounce(unsigned long data)
|
||||
{
|
||||
unsigned char reg_a, reg_c, xctrl_a;
|
||||
|
||||
reg_c = CMOS_READ(RTC_INTR_FLAGS);
|
||||
reg_a = CMOS_READ(RTC_REG_A);
|
||||
CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A);
|
||||
wbflush();
|
||||
xctrl_a = CMOS_READ(DS_B1_XCTRL4A);
|
||||
if ((xctrl_a & DS_XCTRL4A_IFS) || (reg_c & RTC_IRQF )) {
|
||||
/* Interrupt still being sent. */
|
||||
debounce_timer.expires = jiffies + 50;
|
||||
add_timer(&debounce_timer);
|
||||
|
||||
/* clear interrupt source */
|
||||
CMOS_WRITE(xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A);
|
||||
CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A);
|
||||
return;
|
||||
}
|
||||
CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A);
|
||||
|
||||
if (has_panicked)
|
||||
ip32_machine_restart(NULL);
|
||||
|
||||
enable_irq(MACEISA_RTC_IRQ);
|
||||
}
|
||||
|
||||
static inline void ip32_power_button(void)
|
||||
{
|
||||
if (has_panicked)
|
||||
return;
|
||||
|
||||
if (shuting_down || kill_cad_pid(SIGINT, 1)) {
|
||||
/* No init process or button pressed twice. */
|
||||
ip32_machine_power_off();
|
||||
}
|
||||
|
||||
shuting_down = 1;
|
||||
blink_timer.data = POWERDOWN_FREQ;
|
||||
blink_timeout(POWERDOWN_FREQ);
|
||||
|
||||
init_timer(&power_timer);
|
||||
power_timer.function = power_timeout;
|
||||
power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ;
|
||||
add_timer(&power_timer);
|
||||
}
|
||||
|
||||
static irqreturn_t ip32_rtc_int(int irq, void *dev_id)
|
||||
{
|
||||
unsigned char reg_c;
|
||||
|
||||
reg_c = CMOS_READ(RTC_INTR_FLAGS);
|
||||
if (!(reg_c & RTC_IRQF)) {
|
||||
printk(KERN_WARNING
|
||||
"%s: RTC IRQ without RTC_IRQF\n", __func__);
|
||||
}
|
||||
/* Wait until interrupt goes away */
|
||||
disable_irq_nosync(MACEISA_RTC_IRQ);
|
||||
init_timer(&debounce_timer);
|
||||
debounce_timer.function = debounce;
|
||||
debounce_timer.expires = jiffies + 50;
|
||||
add_timer(&debounce_timer);
|
||||
|
||||
printk(KERN_DEBUG "Power button pressed\n");
|
||||
ip32_power_button();
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int panic_event(struct notifier_block *this, unsigned long event,
|
||||
void *ptr)
|
||||
{
|
||||
unsigned long led;
|
||||
|
||||
if (has_panicked)
|
||||
return NOTIFY_DONE;
|
||||
has_panicked = 1;
|
||||
|
||||
/* turn off the green LED */
|
||||
led = mace->perif.ctrl.misc | MACEISA_LED_GREEN;
|
||||
mace->perif.ctrl.misc = led;
|
||||
|
||||
blink_timer.data = PANIC_FREQ;
|
||||
blink_timeout(PANIC_FREQ);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block panic_block = {
|
||||
.notifier_call = panic_event,
|
||||
};
|
||||
|
||||
static __init int ip32_reboot_setup(void)
|
||||
{
|
||||
/* turn on the green led only */
|
||||
unsigned long led = mace->perif.ctrl.misc;
|
||||
led |= MACEISA_LED_RED;
|
||||
led &= ~MACEISA_LED_GREEN;
|
||||
mace->perif.ctrl.misc = led;
|
||||
|
||||
_machine_restart = ip32_machine_restart;
|
||||
_machine_halt = ip32_machine_halt;
|
||||
pm_power_off = ip32_machine_power_off;
|
||||
|
||||
init_timer(&blink_timer);
|
||||
blink_timer.function = blink_timeout;
|
||||
atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
|
||||
|
||||
if (request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL))
|
||||
panic("Can't allocate MACEISA RTC IRQ");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(ip32_reboot_setup);
|
||||
102
arch/mips/sgi-ip32/ip32-setup.c
Normal file
102
arch/mips/sgi-ip32/ip32-setup.c
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* IP32 basic setup
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2000 Harald Koerfgen
|
||||
* Copyright (C) 2002, 2003, 2005 Ilya A. Volynets
|
||||
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#include <linux/console.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mc146818rtc.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/mc146818-time.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/sgialib.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/ip32/crime.h>
|
||||
#include <asm/ip32/mace.h>
|
||||
#include <asm/ip32/ip32_ints.h>
|
||||
|
||||
extern void ip32_be_init(void);
|
||||
extern void crime_init(void);
|
||||
|
||||
#ifdef CONFIG_SGI_O2MACE_ETH
|
||||
/*
|
||||
* This is taken care of in here 'cause they say using Arc later on is
|
||||
* problematic
|
||||
*/
|
||||
extern char o2meth_eaddr[8];
|
||||
static inline unsigned char str2hexnum(unsigned char c)
|
||||
{
|
||||
if (c >= '0' && c <= '9')
|
||||
return c - '0';
|
||||
if (c >= 'a' && c <= 'f')
|
||||
return c - 'a' + 10;
|
||||
return 0; /* foo */
|
||||
}
|
||||
|
||||
static inline void str2eaddr(unsigned char *ea, unsigned char *str)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
unsigned char num;
|
||||
|
||||
if(*str == ':')
|
||||
str++;
|
||||
num = str2hexnum(*str++) << 4;
|
||||
num |= (str2hexnum(*str++));
|
||||
ea[i] = num;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* An arbitrary time; this can be decreased if reliability looks good */
|
||||
#define WAIT_MS 10
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
printk(KERN_INFO "Calibrating system timer... ");
|
||||
write_c0_count(0);
|
||||
crime->timer = 0;
|
||||
while (crime->timer < CRIME_MASTER_FREQ * WAIT_MS / 1000) ;
|
||||
mips_hpt_frequency = read_c0_count() * 1000 / WAIT_MS;
|
||||
printk("%d MHz CPU detected\n", mips_hpt_frequency * 2 / 1000000);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
board_be_init = ip32_be_init;
|
||||
|
||||
#ifdef CONFIG_SGI_O2MACE_ETH
|
||||
{
|
||||
char *mac = ArcGetEnvironmentVariable("eaddr");
|
||||
str2eaddr(o2meth_eaddr, mac);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_CORE_CONSOLE)
|
||||
{
|
||||
char* con = ArcGetEnvironmentVariable("console");
|
||||
if (con && *con == 'd') {
|
||||
static char options[8] __initdata;
|
||||
char *baud = ArcGetEnvironmentVariable("dbaud");
|
||||
if (baud)
|
||||
strcpy(options, baud);
|
||||
add_preferred_console("ttyS", *(con + 1) == '2' ? 1 : 0,
|
||||
baud ? options : NULL);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue