mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-29 07:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
123
arch/mips/txx9/generic/7segled.c
Normal file
123
arch/mips/txx9/generic/7segled.c
Normal file
|
|
@ -0,0 +1,123 @@
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|||
/*
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* 7 Segment LED routines
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* Based on RBTX49xx patch from CELF patch archive.
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*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
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*
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* (C) Copyright TOSHIBA CORPORATION 2005-2007
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* All Rights Reserved.
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*/
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/map_to_7segment.h>
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#include <asm/txx9/generic.h>
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static unsigned int tx_7segled_num;
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static void (*tx_7segled_putc)(unsigned int pos, unsigned char val);
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void __init txx9_7segled_init(unsigned int num,
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void (*putc)(unsigned int pos, unsigned char val))
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{
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tx_7segled_num = num;
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tx_7segled_putc = putc;
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}
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static SEG7_CONVERSION_MAP(txx9_seg7map, MAP_ASCII7SEG_ALPHANUM_LC);
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int txx9_7segled_putc(unsigned int pos, char c)
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{
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if (pos >= tx_7segled_num)
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return -EINVAL;
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c = map_to_seg7(&txx9_seg7map, c);
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if (c < 0)
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return c;
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tx_7segled_putc(pos, c);
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return 0;
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}
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static ssize_t ascii_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned int ch = dev->id;
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txx9_7segled_putc(ch, buf[0]);
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return size;
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}
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static ssize_t raw_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned int ch = dev->id;
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tx_7segled_putc(ch, buf[0]);
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return size;
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}
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static DEVICE_ATTR(ascii, 0200, NULL, ascii_store);
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static DEVICE_ATTR(raw, 0200, NULL, raw_store);
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static ssize_t map_seg7_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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memcpy(buf, &txx9_seg7map, sizeof(txx9_seg7map));
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return sizeof(txx9_seg7map);
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}
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static ssize_t map_seg7_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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if (size != sizeof(txx9_seg7map))
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return -EINVAL;
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memcpy(&txx9_seg7map, buf, size);
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return size;
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}
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static DEVICE_ATTR(map_seg7, 0600, map_seg7_show, map_seg7_store);
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static struct bus_type tx_7segled_subsys = {
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.name = "7segled",
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.dev_name = "7segled",
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};
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static void tx_7segled_release(struct device *dev)
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{
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kfree(dev);
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}
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static int __init tx_7segled_init_sysfs(void)
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{
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int error, i;
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if (!tx_7segled_num)
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return -ENODEV;
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error = subsys_system_register(&tx_7segled_subsys, NULL);
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if (error)
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return error;
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error = device_create_file(tx_7segled_subsys.dev_root, &dev_attr_map_seg7);
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if (error)
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return error;
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for (i = 0; i < tx_7segled_num; i++) {
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struct device *dev;
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dev = kzalloc(sizeof(*dev), GFP_KERNEL);
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if (!dev) {
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error = -ENODEV;
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break;
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}
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dev->id = i;
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dev->bus = &tx_7segled_subsys;
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dev->release = &tx_7segled_release;
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error = device_register(dev);
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if (error) {
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put_device(dev);
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return error;
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}
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device_create_file(dev, &dev_attr_ascii);
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device_create_file(dev, &dev_attr_raw);
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}
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return error;
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}
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device_initcall(tx_7segled_init_sysfs);
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13
arch/mips/txx9/generic/Makefile
Normal file
13
arch/mips/txx9/generic/Makefile
Normal file
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@ -0,0 +1,13 @@
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#
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# Makefile for common code for TXx9 based systems
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#
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obj-y += setup.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
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obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
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obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
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obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
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obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
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obj-$(CONFIG_SPI) += spi_eeprom.o
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obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o
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25
arch/mips/txx9/generic/irq_tx3927.c
Normal file
25
arch/mips/txx9/generic/irq_tx3927.c
Normal file
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@ -0,0 +1,25 @@
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/*
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* Common tx3927 irq handler
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright 2001 MontaVista Software Inc.
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* Copyright (C) 2000-2001 Toshiba Corporation
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*/
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#include <linux/init.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9/tx3927.h>
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void __init tx3927_irq_init(void)
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{
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int i;
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txx9_irq_init(TX3927_IRC_REG);
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/* raise priority for timers, sio */
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for (i = 0; i < TX3927_NR_TMR; i++)
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txx9_irq_set_pri(TX3927_IR_TMR(i), 6);
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for (i = 0; i < TX3927_NR_SIO; i++)
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txx9_irq_set_pri(TX3927_IR_SIO(i), 7);
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}
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49
arch/mips/txx9/generic/irq_tx4927.c
Normal file
49
arch/mips/txx9/generic/irq_tx4927.c
Normal file
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@ -0,0 +1,49 @@
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/*
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* Common tx4927 irq handler
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
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||||
*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
|
||||
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/txx9/tx4927.h>
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void __init tx4927_irq_init(void)
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{
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int i;
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mips_cpu_irq_init();
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txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
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irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
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handle_simple_irq);
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/* raise priority for errors, timers, SIO */
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txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
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txx9_irq_set_pri(TX4927_IR_WTOERR, 7);
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txx9_irq_set_pri(TX4927_IR_PCIERR, 7);
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txx9_irq_set_pri(TX4927_IR_PCIPME, 7);
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for (i = 0; i < TX4927_NUM_IR_TMR; i++)
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txx9_irq_set_pri(TX4927_IR_TMR(i), 6);
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for (i = 0; i < TX4927_NUM_IR_SIO; i++)
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txx9_irq_set_pri(TX4927_IR_SIO(i), 5);
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}
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37
arch/mips/txx9/generic/irq_tx4938.c
Normal file
37
arch/mips/txx9/generic/irq_tx4938.c
Normal file
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@ -0,0 +1,37 @@
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/*
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* linux/arch/mips/tx4938/common/irq.c
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*
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* Common tx4938 irq handler
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/txx9/tx4938.h>
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void __init tx4938_irq_init(void)
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{
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int i;
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mips_cpu_irq_init();
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txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
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irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
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handle_simple_irq);
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/* raise priority for errors, timers, SIO */
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txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
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txx9_irq_set_pri(TX4938_IR_WTOERR, 7);
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txx9_irq_set_pri(TX4938_IR_PCIERR, 7);
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txx9_irq_set_pri(TX4938_IR_PCIPME, 7);
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for (i = 0; i < TX4938_NUM_IR_TMR; i++)
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txx9_irq_set_pri(TX4938_IR_TMR(i), 6);
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for (i = 0; i < TX4938_NUM_IR_SIO; i++)
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txx9_irq_set_pri(TX4938_IR_SIO(i), 5);
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}
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216
arch/mips/txx9/generic/irq_tx4939.c
Normal file
216
arch/mips/txx9/generic/irq_tx4939.c
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* TX4939 irq routines
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||||
* Based on linux/arch/mips/kernel/irq_txx9.c,
|
||||
* and RBTX49xx patch from CELF patch archive.
|
||||
*
|
||||
* Copyright 2001, 2003-2005 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ahennessy@mvista.com
|
||||
* source@mvista.com
|
||||
* Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
/*
|
||||
* TX4939 defines 64 IRQs.
|
||||
* Similer to irq_txx9.c but different register layouts.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9/tx4939.h>
|
||||
|
||||
/* IRCER : Int. Control Enable */
|
||||
#define TXx9_IRCER_ICE 0x00000001
|
||||
|
||||
/* IRCR : Int. Control */
|
||||
#define TXx9_IRCR_LOW 0x00000000
|
||||
#define TXx9_IRCR_HIGH 0x00000001
|
||||
#define TXx9_IRCR_DOWN 0x00000002
|
||||
#define TXx9_IRCR_UP 0x00000003
|
||||
#define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
|
||||
|
||||
/* IRSCR : Int. Status Control */
|
||||
#define TXx9_IRSCR_EIClrE 0x00000100
|
||||
#define TXx9_IRSCR_EIClr_MASK 0x0000000f
|
||||
|
||||
/* IRCSR : Int. Current Status */
|
||||
#define TXx9_IRCSR_IF 0x00010000
|
||||
|
||||
#define irc_dlevel 0
|
||||
#define irc_elevel 1
|
||||
|
||||
static struct {
|
||||
unsigned char level;
|
||||
unsigned char mode;
|
||||
} tx4939irq[TX4939_NUM_IR] __read_mostly;
|
||||
|
||||
static void tx4939_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
|
||||
u32 __iomem *lvlp;
|
||||
int ofs;
|
||||
if (irq_nr < 32) {
|
||||
irq_nr--;
|
||||
lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
|
||||
} else {
|
||||
irq_nr -= 32;
|
||||
lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
|
||||
}
|
||||
ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
|
||||
__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
|
||||
| (tx4939irq[irq_nr].level << ofs),
|
||||
lvlp);
|
||||
}
|
||||
|
||||
static inline void tx4939_irq_mask(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
|
||||
u32 __iomem *lvlp;
|
||||
int ofs;
|
||||
if (irq_nr < 32) {
|
||||
irq_nr--;
|
||||
lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
|
||||
} else {
|
||||
irq_nr -= 32;
|
||||
lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
|
||||
}
|
||||
ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
|
||||
__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
|
||||
| (irc_dlevel << ofs),
|
||||
lvlp);
|
||||
mmiowb();
|
||||
}
|
||||
|
||||
static void tx4939_irq_mask_ack(struct irq_data *d)
|
||||
{
|
||||
unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
|
||||
|
||||
tx4939_irq_mask(d);
|
||||
if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
|
||||
irq_nr--;
|
||||
/* clear edge detection */
|
||||
__raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
|
||||
<< (irq_nr & 0x10),
|
||||
&tx4939_ircptr->edc.r);
|
||||
}
|
||||
}
|
||||
|
||||
static int tx4939_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
||||
{
|
||||
unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
|
||||
u32 cr;
|
||||
u32 __iomem *crp;
|
||||
int ofs;
|
||||
int mode;
|
||||
|
||||
if (flow_type & IRQF_TRIGGER_PROBE)
|
||||
return 0;
|
||||
switch (flow_type & IRQF_TRIGGER_MASK) {
|
||||
case IRQF_TRIGGER_RISING:
|
||||
mode = TXx9_IRCR_UP;
|
||||
break;
|
||||
case IRQF_TRIGGER_FALLING:
|
||||
mode = TXx9_IRCR_DOWN;
|
||||
break;
|
||||
case IRQF_TRIGGER_HIGH:
|
||||
mode = TXx9_IRCR_HIGH;
|
||||
break;
|
||||
case IRQF_TRIGGER_LOW:
|
||||
mode = TXx9_IRCR_LOW;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
if (irq_nr < 32) {
|
||||
irq_nr--;
|
||||
crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
|
||||
} else {
|
||||
irq_nr -= 32;
|
||||
crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
|
||||
}
|
||||
ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
|
||||
cr = __raw_readl(crp);
|
||||
cr &= ~(0x3 << ofs);
|
||||
cr |= (mode & 0x3) << ofs;
|
||||
__raw_writel(cr, crp);
|
||||
tx4939irq[irq_nr].mode = mode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip tx4939_irq_chip = {
|
||||
.name = "TX4939",
|
||||
.irq_ack = tx4939_irq_mask_ack,
|
||||
.irq_mask = tx4939_irq_mask,
|
||||
.irq_mask_ack = tx4939_irq_mask_ack,
|
||||
.irq_unmask = tx4939_irq_unmask,
|
||||
.irq_set_type = tx4939_irq_set_type,
|
||||
};
|
||||
|
||||
static int tx4939_irq_set_pri(int irc_irq, int new_pri)
|
||||
{
|
||||
int old_pri;
|
||||
|
||||
if ((unsigned int)irc_irq >= TX4939_NUM_IR)
|
||||
return 0;
|
||||
old_pri = tx4939irq[irc_irq].level;
|
||||
tx4939irq[irc_irq].level = new_pri;
|
||||
return old_pri;
|
||||
}
|
||||
|
||||
void __init tx4939_irq_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
mips_cpu_irq_init();
|
||||
/* disable interrupt control */
|
||||
__raw_writel(0, &tx4939_ircptr->den.r);
|
||||
__raw_writel(0, &tx4939_ircptr->maskint.r);
|
||||
__raw_writel(0, &tx4939_ircptr->maskext.r);
|
||||
/* irq_base + 0 is not used */
|
||||
for (i = 1; i < TX4939_NUM_IR; i++) {
|
||||
tx4939irq[i].level = 4; /* middle level */
|
||||
tx4939irq[i].mode = TXx9_IRCR_LOW;
|
||||
irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
/* mask all IRC interrupts */
|
||||
__raw_writel(0, &tx4939_ircptr->msk.r);
|
||||
for (i = 0; i < 16; i++)
|
||||
__raw_writel(0, &tx4939_ircptr->lvl[i].r);
|
||||
/* setup IRC interrupt mode (Low Active) */
|
||||
for (i = 0; i < 2; i++)
|
||||
__raw_writel(0, &tx4939_ircptr->dm[i].r);
|
||||
for (i = 0; i < 2; i++)
|
||||
__raw_writel(0, &tx4939_ircptr->dm2[i].r);
|
||||
/* enable interrupt control */
|
||||
__raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
|
||||
__raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
|
||||
|
||||
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
|
||||
handle_simple_irq);
|
||||
|
||||
/* raise priority for errors, timers, sio */
|
||||
tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
|
||||
tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
|
||||
tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
|
||||
for (i = 0; i < TX4939_NUM_IR_TMR; i++)
|
||||
tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
|
||||
for (i = 0; i < TX4939_NUM_IR_SIO; i++)
|
||||
tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
|
||||
}
|
||||
|
||||
int tx4939_irq(void)
|
||||
{
|
||||
u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
|
||||
|
||||
if (likely(!(csr & TXx9_IRCSR_IF)))
|
||||
return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
|
||||
return -1;
|
||||
}
|
||||
75
arch/mips/txx9/generic/mem_tx4927.c
Normal file
75
arch/mips/txx9/generic/mem_tx4927.c
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* common tx4927 memory interface
|
||||
*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
*
|
||||
* Copyright 2001-2002 MontaVista Software Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
|
||||
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/txx9/tx4927.h>
|
||||
|
||||
static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
|
||||
{
|
||||
u64 val;
|
||||
unsigned int sdccr_ce;
|
||||
unsigned int sdccr_bs;
|
||||
unsigned int sdccr_rs;
|
||||
unsigned int sdccr_cs;
|
||||
unsigned int sdccr_mw;
|
||||
unsigned int bs = 0;
|
||||
unsigned int rs = 0;
|
||||
unsigned int cs = 0;
|
||||
unsigned int mw = 0;
|
||||
|
||||
val = __raw_readq(addr);
|
||||
|
||||
/* MVMCP -- need #defs for these bits masks */
|
||||
sdccr_ce = ((val & (1 << 10)) >> 10);
|
||||
sdccr_bs = ((val & (1 << 8)) >> 8);
|
||||
sdccr_rs = ((val & (3 << 5)) >> 5);
|
||||
sdccr_cs = ((val & (7 << 2)) >> 2);
|
||||
sdccr_mw = ((val & (1 << 0)) >> 0);
|
||||
|
||||
if (sdccr_ce) {
|
||||
bs = 2 << sdccr_bs;
|
||||
rs = 2048 << sdccr_rs;
|
||||
cs = 256 << sdccr_cs;
|
||||
mw = 8 >> sdccr_mw;
|
||||
}
|
||||
|
||||
return rs * cs * mw * bs;
|
||||
}
|
||||
|
||||
unsigned int __init tx4927_get_mem_size(void)
|
||||
{
|
||||
unsigned int total = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
|
||||
total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
|
||||
return total;
|
||||
}
|
||||
434
arch/mips/txx9/generic/pci.c
Normal file
434
arch/mips/txx9/generic/pci.c
Normal file
|
|
@ -0,0 +1,434 @@
|
|||
/*
|
||||
* linux/arch/mips/txx9/pci.c
|
||||
*
|
||||
* Based on linux/arch/mips/txx9/rbtx4927/setup.c,
|
||||
* linux/arch/mips/txx9/rbtx4938/setup.c,
|
||||
* and RBTX49xx patch from CELF patch archive.
|
||||
*
|
||||
* Copyright 2001-2005 MontaVista Software Inc.
|
||||
* Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
|
||||
* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/delay.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/pci.h>
|
||||
#ifdef CONFIG_TOSHIBA_FPCIB0
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/i8259.h>
|
||||
#include <asm/txx9/smsc_fdc37m81x.h>
|
||||
#endif
|
||||
|
||||
static int __init
|
||||
early_read_config_word(struct pci_controller *hose,
|
||||
int top_bus, int bus, int devfn, int offset, u16 *value)
|
||||
{
|
||||
struct pci_dev fake_dev;
|
||||
struct pci_bus fake_bus;
|
||||
|
||||
fake_dev.bus = &fake_bus;
|
||||
fake_dev.sysdata = hose;
|
||||
fake_dev.devfn = devfn;
|
||||
fake_bus.number = bus;
|
||||
fake_bus.sysdata = hose;
|
||||
fake_bus.ops = hose->pci_ops;
|
||||
|
||||
if (bus != top_bus)
|
||||
/* Fake a parent bus structure. */
|
||||
fake_bus.parent = &fake_bus;
|
||||
else
|
||||
fake_bus.parent = NULL;
|
||||
|
||||
return pci_read_config_word(&fake_dev, offset, value);
|
||||
}
|
||||
|
||||
int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
|
||||
int current_bus)
|
||||
{
|
||||
u32 pci_devfn;
|
||||
unsigned short vid;
|
||||
int cap66 = -1;
|
||||
u16 stat;
|
||||
|
||||
/* It seems SLC90E66 needs some time after PCI reset... */
|
||||
mdelay(80);
|
||||
|
||||
printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
|
||||
|
||||
for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
|
||||
if (PCI_FUNC(pci_devfn))
|
||||
continue;
|
||||
if (early_read_config_word(hose, top_bus, current_bus,
|
||||
pci_devfn, PCI_VENDOR_ID, &vid) !=
|
||||
PCIBIOS_SUCCESSFUL)
|
||||
continue;
|
||||
if (vid == 0xffff)
|
||||
continue;
|
||||
|
||||
/* check 66MHz capability */
|
||||
if (cap66 < 0)
|
||||
cap66 = 1;
|
||||
if (cap66) {
|
||||
early_read_config_word(hose, top_bus, current_bus,
|
||||
pci_devfn, PCI_STATUS, &stat);
|
||||
if (!(stat & PCI_STATUS_66MHZ)) {
|
||||
printk(KERN_DEBUG
|
||||
"PCI: %02x:%02x not 66MHz capable.\n",
|
||||
current_bus, pci_devfn);
|
||||
cap66 = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return cap66 > 0;
|
||||
}
|
||||
|
||||
static struct resource primary_pci_mem_res[2] = {
|
||||
{ .name = "PCI MEM" },
|
||||
{ .name = "PCI MMIO" },
|
||||
};
|
||||
static struct resource primary_pci_io_res = { .name = "PCI IO" };
|
||||
struct pci_controller txx9_primary_pcic = {
|
||||
.mem_resource = &primary_pci_mem_res[0],
|
||||
.io_resource = &primary_pci_io_res,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
int txx9_pci_mem_high __initdata = 1;
|
||||
#else
|
||||
int txx9_pci_mem_high __initdata;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* allocate pci_controller and resources.
|
||||
* mem_base, io_base: physical address. 0 for auto assignment.
|
||||
* mem_size and io_size means max size on auto assignment.
|
||||
* pcic must be &txx9_primary_pcic or NULL.
|
||||
*/
|
||||
struct pci_controller *__init
|
||||
txx9_alloc_pci_controller(struct pci_controller *pcic,
|
||||
unsigned long mem_base, unsigned long mem_size,
|
||||
unsigned long io_base, unsigned long io_size)
|
||||
{
|
||||
struct pcic {
|
||||
struct pci_controller c;
|
||||
struct resource r_mem[2];
|
||||
struct resource r_io;
|
||||
} *new = NULL;
|
||||
int min_size = 0x10000;
|
||||
|
||||
if (!pcic) {
|
||||
new = kzalloc(sizeof(*new), GFP_KERNEL);
|
||||
if (!new)
|
||||
return NULL;
|
||||
new->r_mem[0].name = "PCI mem";
|
||||
new->r_mem[1].name = "PCI mmio";
|
||||
new->r_io.name = "PCI io";
|
||||
new->c.mem_resource = new->r_mem;
|
||||
new->c.io_resource = &new->r_io;
|
||||
pcic = &new->c;
|
||||
} else
|
||||
BUG_ON(pcic != &txx9_primary_pcic);
|
||||
pcic->io_resource->flags = IORESOURCE_IO;
|
||||
|
||||
/*
|
||||
* for auto assignment, first search a (big) region for PCI
|
||||
* MEM, then search a region for PCI IO.
|
||||
*/
|
||||
if (mem_base) {
|
||||
pcic->mem_resource[0].start = mem_base;
|
||||
pcic->mem_resource[0].end = mem_base + mem_size - 1;
|
||||
if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
|
||||
goto free_and_exit;
|
||||
} else {
|
||||
unsigned long min = 0, max = 0x20000000; /* low 512MB */
|
||||
if (!mem_size) {
|
||||
/* default size for auto assignment */
|
||||
if (txx9_pci_mem_high)
|
||||
mem_size = 0x20000000; /* mem:512M(max) */
|
||||
else
|
||||
mem_size = 0x08000000; /* mem:128M(max) */
|
||||
}
|
||||
if (txx9_pci_mem_high) {
|
||||
min = 0x20000000;
|
||||
max = 0xe0000000;
|
||||
}
|
||||
/* search free region for PCI MEM */
|
||||
for (; mem_size >= min_size; mem_size /= 2) {
|
||||
if (allocate_resource(&iomem_resource,
|
||||
&pcic->mem_resource[0],
|
||||
mem_size, min, max,
|
||||
mem_size, NULL, NULL) == 0)
|
||||
break;
|
||||
}
|
||||
if (mem_size < min_size)
|
||||
goto free_and_exit;
|
||||
}
|
||||
|
||||
pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
||||
if (io_base) {
|
||||
pcic->mem_resource[1].start = io_base;
|
||||
pcic->mem_resource[1].end = io_base + io_size - 1;
|
||||
if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
|
||||
goto release_and_exit;
|
||||
} else {
|
||||
if (!io_size)
|
||||
/* default size for auto assignment */
|
||||
io_size = 0x01000000; /* io:16M(max) */
|
||||
/* search free region for PCI IO in low 512MB */
|
||||
for (; io_size >= min_size; io_size /= 2) {
|
||||
if (allocate_resource(&iomem_resource,
|
||||
&pcic->mem_resource[1],
|
||||
io_size, 0, 0x20000000,
|
||||
io_size, NULL, NULL) == 0)
|
||||
break;
|
||||
}
|
||||
if (io_size < min_size)
|
||||
goto release_and_exit;
|
||||
io_base = pcic->mem_resource[1].start;
|
||||
}
|
||||
|
||||
pcic->mem_resource[0].flags = IORESOURCE_MEM;
|
||||
if (pcic == &txx9_primary_pcic &&
|
||||
mips_io_port_base == (unsigned long)-1) {
|
||||
/* map ioport 0 to PCI I/O space address 0 */
|
||||
set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
|
||||
pcic->io_resource->start = 0;
|
||||
pcic->io_offset = 0; /* busaddr == ioaddr */
|
||||
pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
|
||||
} else {
|
||||
/* physaddr to ioaddr */
|
||||
pcic->io_resource->start =
|
||||
io_base - (mips_io_port_base - IO_BASE);
|
||||
pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
|
||||
pcic->io_map_base = mips_io_port_base;
|
||||
}
|
||||
pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
|
||||
|
||||
pcic->mem_offset = 0; /* busaddr == physaddr */
|
||||
|
||||
printk(KERN_INFO "PCI: IO %pR MEM %pR\n",
|
||||
&pcic->mem_resource[1], &pcic->mem_resource[0]);
|
||||
|
||||
/* register_pci_controller() will request MEM resource */
|
||||
release_resource(&pcic->mem_resource[0]);
|
||||
return pcic;
|
||||
release_and_exit:
|
||||
release_resource(&pcic->mem_resource[0]);
|
||||
free_and_exit:
|
||||
kfree(new);
|
||||
printk(KERN_ERR "PCI: Failed to allocate resources.\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int __init
|
||||
txx9_arch_pci_init(void)
|
||||
{
|
||||
PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(txx9_arch_pci_init);
|
||||
|
||||
/* IRQ/IDSEL mapping */
|
||||
int txx9_pci_option =
|
||||
#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
|
||||
TXX9_PCI_OPT_PICMG |
|
||||
#endif
|
||||
TXX9_PCI_OPT_CLK_AUTO;
|
||||
|
||||
enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
|
||||
|
||||
#ifdef CONFIG_TOSHIBA_FPCIB0
|
||||
static irqreturn_t i8259_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
int isairq;
|
||||
|
||||
isairq = i8259_irq();
|
||||
if (unlikely(isairq <= I8259A_IRQ_BASE))
|
||||
return IRQ_NONE;
|
||||
generic_handle_irq(isairq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int txx9_i8259_irq_setup(int irq)
|
||||
{
|
||||
int err;
|
||||
|
||||
init_i8259_irqs();
|
||||
err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
|
||||
"cascade(i8259)", (void *)(long)irq);
|
||||
if (!err)
|
||||
printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void __init_refok quirk_slc90e66_bridge(struct pci_dev *dev)
|
||||
{
|
||||
int irq; /* PCI/ISA Bridge interrupt */
|
||||
u8 reg_64;
|
||||
u32 reg_b0;
|
||||
u8 reg_e1;
|
||||
irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
|
||||
if (!irq)
|
||||
return;
|
||||
txx9_i8259_irq_setup(irq);
|
||||
pci_read_config_byte(dev, 0x64, ®_64);
|
||||
pci_read_config_dword(dev, 0xb0, ®_b0);
|
||||
pci_read_config_byte(dev, 0xe1, ®_e1);
|
||||
/* serial irq control */
|
||||
reg_64 = 0xd0;
|
||||
/* serial irq pin */
|
||||
reg_b0 |= 0x00010000;
|
||||
/* ide irq on isa14 */
|
||||
reg_e1 &= 0xf0;
|
||||
reg_e1 |= 0x0d;
|
||||
pci_write_config_byte(dev, 0x64, reg_64);
|
||||
pci_write_config_dword(dev, 0xb0, reg_b0);
|
||||
pci_write_config_byte(dev, 0xe1, reg_e1);
|
||||
|
||||
smsc_fdc37m81x_init(0x3f0);
|
||||
smsc_fdc37m81x_config_beg();
|
||||
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
|
||||
SMSC_FDC37M81X_KBD);
|
||||
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
|
||||
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
|
||||
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
|
||||
1);
|
||||
smsc_fdc37m81x_config_end();
|
||||
}
|
||||
|
||||
static void quirk_slc90e66_ide(struct pci_dev *dev)
|
||||
{
|
||||
unsigned char dat;
|
||||
int regs[2] = {0x41, 0x43};
|
||||
int i;
|
||||
|
||||
/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
|
||||
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
|
||||
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
|
||||
printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
|
||||
/* enable SMSC SLC90E66 IDE */
|
||||
for (i = 0; i < ARRAY_SIZE(regs); i++) {
|
||||
pci_read_config_byte(dev, regs[i], &dat);
|
||||
pci_write_config_byte(dev, regs[i], dat | 0x80);
|
||||
pci_read_config_byte(dev, regs[i], &dat);
|
||||
printk(KERN_CONT " IDETIM%d %02x", i, dat);
|
||||
}
|
||||
pci_read_config_byte(dev, 0x5c, &dat);
|
||||
/*
|
||||
* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
|
||||
*
|
||||
* This line of code is intended to provide the user with a work
|
||||
* around solution to the anomalies cited in SMSC's anomaly sheet
|
||||
* entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
|
||||
*
|
||||
* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
|
||||
*/
|
||||
dat |= 0x01;
|
||||
pci_write_config_byte(dev, 0x5c, dat);
|
||||
pci_read_config_byte(dev, 0x5c, &dat);
|
||||
printk(KERN_CONT " REG5C %02x", dat);
|
||||
printk(KERN_CONT "\n");
|
||||
}
|
||||
#endif /* CONFIG_TOSHIBA_FPCIB0 */
|
||||
|
||||
static void tc35815_fixup(struct pci_dev *dev)
|
||||
{
|
||||
/* This device may have PM registers but not they are not supported. */
|
||||
if (dev->pm_cap) {
|
||||
dev_info(&dev->dev, "PM disabled\n");
|
||||
dev->pm_cap = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void final_fixup(struct pci_dev *dev)
|
||||
{
|
||||
unsigned char bist;
|
||||
|
||||
/* Do build-in self test */
|
||||
if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
|
||||
(bist & PCI_BIST_CAPABLE)) {
|
||||
unsigned long timeout;
|
||||
pci_set_power_state(dev, PCI_D0);
|
||||
printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
|
||||
pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
|
||||
timeout = jiffies + HZ * 2; /* timeout after 2 sec */
|
||||
do {
|
||||
pci_read_config_byte(dev, PCI_BIST, &bist);
|
||||
if (time_after(jiffies, timeout))
|
||||
break;
|
||||
} while (bist & PCI_BIST_START);
|
||||
if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
|
||||
printk(KERN_CONT "failed. (0x%x)\n", bist);
|
||||
else
|
||||
printk(KERN_CONT "OK.\n");
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TOSHIBA_FPCIB0
|
||||
#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
|
||||
quirk_slc90e66_bridge);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
|
||||
quirk_slc90e66_ide);
|
||||
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
|
||||
quirk_slc90e66_ide);
|
||||
#endif
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
|
||||
PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
|
||||
PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
|
||||
DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
|
||||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
return txx9_board_vec->pci_map_irq(dev, slot, pin);
|
||||
}
|
||||
|
||||
char * (*txx9_board_pcibios_setup)(char *str) __initdata;
|
||||
|
||||
char *__init txx9_pcibios_setup(char *str)
|
||||
{
|
||||
if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
|
||||
return NULL;
|
||||
if (!strcmp(str, "picmg")) {
|
||||
/* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
|
||||
(5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
|
||||
txx9_pci_option |= TXX9_PCI_OPT_PICMG;
|
||||
return NULL;
|
||||
} else if (!strcmp(str, "nopicmg")) {
|
||||
/* non-PICMG compliant backplane (TOSHIBA
|
||||
RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
|
||||
txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
|
||||
return NULL;
|
||||
} else if (!strncmp(str, "clk=", 4)) {
|
||||
char *val = str + 4;
|
||||
txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
|
||||
if (strcmp(val, "33") == 0)
|
||||
txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
|
||||
else if (strcmp(val, "66") == 0)
|
||||
txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
|
||||
else /* "auto" */
|
||||
txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
|
||||
return NULL;
|
||||
} else if (!strncmp(str, "err=", 4)) {
|
||||
if (!strcmp(str + 4, "panic"))
|
||||
txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
|
||||
else if (!strcmp(str + 4, "ignore"))
|
||||
txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
|
||||
return NULL;
|
||||
}
|
||||
return str;
|
||||
}
|
||||
988
arch/mips/txx9/generic/setup.c
Normal file
988
arch/mips/txx9/generic/setup.c
Normal file
|
|
@ -0,0 +1,988 @@
|
|||
/*
|
||||
* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
|
||||
* and RBTX49xx patch from CELF patch archive.
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc.
|
||||
* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/r4kcache.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/pci.h>
|
||||
#include <asm/txx9tmr.h>
|
||||
#include <asm/txx9/ndfmc.h>
|
||||
#include <asm/txx9/dmac.h>
|
||||
#ifdef CONFIG_CPU_TX49XX
|
||||
#include <asm/txx9/tx4938.h>
|
||||
#endif
|
||||
|
||||
/* EBUSC settings of TX4927, etc. */
|
||||
struct resource txx9_ce_res[8];
|
||||
static char txx9_ce_res_name[8][4]; /* "CEn" */
|
||||
|
||||
/* pcode, internal register */
|
||||
unsigned int txx9_pcode;
|
||||
char txx9_pcode_str[8];
|
||||
static struct resource txx9_reg_res = {
|
||||
.name = txx9_pcode_str,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
void __init
|
||||
txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
|
||||
sprintf(txx9_ce_res_name[i], "CE%d", i);
|
||||
txx9_ce_res[i].flags = IORESOURCE_MEM;
|
||||
txx9_ce_res[i].name = txx9_ce_res_name[i];
|
||||
}
|
||||
|
||||
txx9_pcode = pcode;
|
||||
sprintf(txx9_pcode_str, "TX%x", pcode);
|
||||
if (base) {
|
||||
txx9_reg_res.start = base & 0xfffffffffULL;
|
||||
txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
|
||||
request_resource(&iomem_resource, &txx9_reg_res);
|
||||
}
|
||||
}
|
||||
|
||||
/* clocks */
|
||||
unsigned int txx9_master_clock;
|
||||
unsigned int txx9_cpu_clock;
|
||||
unsigned int txx9_gbus_clock;
|
||||
|
||||
#ifdef CONFIG_CPU_TX39XX
|
||||
/* don't enable by default - see errata */
|
||||
int txx9_ccfg_toeon __initdata;
|
||||
#else
|
||||
int txx9_ccfg_toeon __initdata = 1;
|
||||
#endif
|
||||
|
||||
/* Minimum CLK support */
|
||||
|
||||
struct clk *clk_get(struct device *dev, const char *id)
|
||||
{
|
||||
if (!strcmp(id, "spi-baseclk"))
|
||||
return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2);
|
||||
if (!strcmp(id, "imbus_clk"))
|
||||
return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
|
||||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get);
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return (unsigned long)clk;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
void clk_put(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_put);
|
||||
|
||||
/* GPIO support */
|
||||
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
EXPORT_SYMBOL(gpio_to_irq);
|
||||
|
||||
int irq_to_gpio(unsigned irq)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
EXPORT_SYMBOL(irq_to_gpio);
|
||||
#endif
|
||||
|
||||
#define BOARD_VEC(board) extern struct txx9_board_vec board;
|
||||
#include <asm/txx9/boards.h>
|
||||
#undef BOARD_VEC
|
||||
|
||||
struct txx9_board_vec *txx9_board_vec __initdata;
|
||||
static char txx9_system_type[32];
|
||||
|
||||
static struct txx9_board_vec *board_vecs[] __initdata = {
|
||||
#define BOARD_VEC(board) &board,
|
||||
#include <asm/txx9/boards.h>
|
||||
#undef BOARD_VEC
|
||||
};
|
||||
|
||||
static struct txx9_board_vec *__init find_board_byname(const char *name)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* search board_vecs table */
|
||||
for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
|
||||
if (strstr(board_vecs[i]->system, name))
|
||||
return board_vecs[i];
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __init prom_init_cmdline(void)
|
||||
{
|
||||
int argc;
|
||||
int *argv32;
|
||||
int i; /* Always ignore the "-c" at argv[0] */
|
||||
|
||||
if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
|
||||
/*
|
||||
* argc is not a valid number, or argv32 is not a valid
|
||||
* pointer
|
||||
*/
|
||||
argc = 0;
|
||||
argv32 = NULL;
|
||||
} else {
|
||||
argc = (int)fw_arg0;
|
||||
argv32 = (int *)fw_arg1;
|
||||
}
|
||||
|
||||
arcs_cmdline[0] = '\0';
|
||||
|
||||
for (i = 1; i < argc; i++) {
|
||||
char *str = (char *)(long)argv32[i];
|
||||
if (i != 1)
|
||||
strcat(arcs_cmdline, " ");
|
||||
if (strchr(str, ' ')) {
|
||||
strcat(arcs_cmdline, "\"");
|
||||
strcat(arcs_cmdline, str);
|
||||
strcat(arcs_cmdline, "\"");
|
||||
} else
|
||||
strcat(arcs_cmdline, str);
|
||||
}
|
||||
}
|
||||
|
||||
static int txx9_ic_disable __initdata;
|
||||
static int txx9_dc_disable __initdata;
|
||||
|
||||
#if defined(CONFIG_CPU_TX49XX)
|
||||
/* flush all cache on very early stage (before 4k_cache_init) */
|
||||
static void __init early_flush_dcache(void)
|
||||
{
|
||||
unsigned int conf = read_c0_config();
|
||||
unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
|
||||
unsigned int linesz = 32;
|
||||
unsigned long addr, end;
|
||||
|
||||
end = INDEX_BASE + dc_size / 4;
|
||||
/* 4way, waybit=0 */
|
||||
for (addr = INDEX_BASE; addr < end; addr += linesz) {
|
||||
cache_op(Index_Writeback_Inv_D, addr | 0);
|
||||
cache_op(Index_Writeback_Inv_D, addr | 1);
|
||||
cache_op(Index_Writeback_Inv_D, addr | 2);
|
||||
cache_op(Index_Writeback_Inv_D, addr | 3);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init txx9_cache_fixup(void)
|
||||
{
|
||||
unsigned int conf;
|
||||
|
||||
conf = read_c0_config();
|
||||
/* flush and disable */
|
||||
if (txx9_ic_disable) {
|
||||
conf |= TX49_CONF_IC;
|
||||
write_c0_config(conf);
|
||||
}
|
||||
if (txx9_dc_disable) {
|
||||
early_flush_dcache();
|
||||
conf |= TX49_CONF_DC;
|
||||
write_c0_config(conf);
|
||||
}
|
||||
|
||||
/* enable cache */
|
||||
conf = read_c0_config();
|
||||
if (!txx9_ic_disable)
|
||||
conf &= ~TX49_CONF_IC;
|
||||
if (!txx9_dc_disable)
|
||||
conf &= ~TX49_CONF_DC;
|
||||
write_c0_config(conf);
|
||||
|
||||
if (conf & TX49_CONF_IC)
|
||||
pr_info("TX49XX I-Cache disabled.\n");
|
||||
if (conf & TX49_CONF_DC)
|
||||
pr_info("TX49XX D-Cache disabled.\n");
|
||||
}
|
||||
#elif defined(CONFIG_CPU_TX39XX)
|
||||
/* flush all cache on very early stage (before tx39_cache_init) */
|
||||
static void __init early_flush_dcache(void)
|
||||
{
|
||||
unsigned int conf = read_c0_config();
|
||||
unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
|
||||
TX39_CONF_DCS_SHIFT));
|
||||
unsigned int linesz = 16;
|
||||
unsigned long addr, end;
|
||||
|
||||
end = INDEX_BASE + dc_size / 2;
|
||||
/* 2way, waybit=0 */
|
||||
for (addr = INDEX_BASE; addr < end; addr += linesz) {
|
||||
cache_op(Index_Writeback_Inv_D, addr | 0);
|
||||
cache_op(Index_Writeback_Inv_D, addr | 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init txx9_cache_fixup(void)
|
||||
{
|
||||
unsigned int conf;
|
||||
|
||||
conf = read_c0_config();
|
||||
/* flush and disable */
|
||||
if (txx9_ic_disable) {
|
||||
conf &= ~TX39_CONF_ICE;
|
||||
write_c0_config(conf);
|
||||
}
|
||||
if (txx9_dc_disable) {
|
||||
early_flush_dcache();
|
||||
conf &= ~TX39_CONF_DCE;
|
||||
write_c0_config(conf);
|
||||
}
|
||||
|
||||
/* enable cache */
|
||||
conf = read_c0_config();
|
||||
if (!txx9_ic_disable)
|
||||
conf |= TX39_CONF_ICE;
|
||||
if (!txx9_dc_disable)
|
||||
conf |= TX39_CONF_DCE;
|
||||
write_c0_config(conf);
|
||||
|
||||
if (!(conf & TX39_CONF_ICE))
|
||||
pr_info("TX39XX I-Cache disabled.\n");
|
||||
if (!(conf & TX39_CONF_DCE))
|
||||
pr_info("TX39XX D-Cache disabled.\n");
|
||||
}
|
||||
#else
|
||||
static inline void txx9_cache_fixup(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init preprocess_cmdline(void)
|
||||
{
|
||||
static char cmdline[COMMAND_LINE_SIZE] __initdata;
|
||||
char *s;
|
||||
|
||||
strcpy(cmdline, arcs_cmdline);
|
||||
s = cmdline;
|
||||
arcs_cmdline[0] = '\0';
|
||||
while (s && *s) {
|
||||
char *str = strsep(&s, " ");
|
||||
if (strncmp(str, "board=", 6) == 0) {
|
||||
txx9_board_vec = find_board_byname(str + 6);
|
||||
continue;
|
||||
} else if (strncmp(str, "masterclk=", 10) == 0) {
|
||||
unsigned int val;
|
||||
if (kstrtouint(str + 10, 10, &val) == 0)
|
||||
txx9_master_clock = val;
|
||||
continue;
|
||||
} else if (strcmp(str, "icdisable") == 0) {
|
||||
txx9_ic_disable = 1;
|
||||
continue;
|
||||
} else if (strcmp(str, "dcdisable") == 0) {
|
||||
txx9_dc_disable = 1;
|
||||
continue;
|
||||
} else if (strcmp(str, "toeoff") == 0) {
|
||||
txx9_ccfg_toeon = 0;
|
||||
continue;
|
||||
} else if (strcmp(str, "toeon") == 0) {
|
||||
txx9_ccfg_toeon = 1;
|
||||
continue;
|
||||
}
|
||||
if (arcs_cmdline[0])
|
||||
strcat(arcs_cmdline, " ");
|
||||
strcat(arcs_cmdline, str);
|
||||
}
|
||||
|
||||
txx9_cache_fixup();
|
||||
}
|
||||
|
||||
static void __init select_board(void)
|
||||
{
|
||||
const char *envstr;
|
||||
|
||||
/* first, determine by "board=" argument in preprocess_cmdline() */
|
||||
if (txx9_board_vec)
|
||||
return;
|
||||
/* next, determine by "board" envvar */
|
||||
envstr = prom_getenv("board");
|
||||
if (envstr) {
|
||||
txx9_board_vec = find_board_byname(envstr);
|
||||
if (txx9_board_vec)
|
||||
return;
|
||||
}
|
||||
|
||||
/* select "default" board */
|
||||
#ifdef CONFIG_TOSHIBA_JMR3927
|
||||
txx9_board_vec = &jmr3927_vec;
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_TX49XX
|
||||
switch (TX4938_REV_PCODE()) {
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4927
|
||||
case 0x4927:
|
||||
txx9_board_vec = &rbtx4927_vec;
|
||||
break;
|
||||
case 0x4937:
|
||||
txx9_board_vec = &rbtx4937_vec;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4938
|
||||
case 0x4938:
|
||||
txx9_board_vec = &rbtx4938_vec;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4939
|
||||
case 0x4939:
|
||||
txx9_board_vec = &rbtx4939_vec;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
prom_init_cmdline();
|
||||
preprocess_cmdline();
|
||||
select_board();
|
||||
|
||||
strcpy(txx9_system_type, txx9_board_vec->system);
|
||||
|
||||
txx9_board_vec->prom_init();
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
unsigned long saddr = PAGE_SIZE;
|
||||
unsigned long eaddr = __pa_symbol(&_text);
|
||||
|
||||
if (saddr < eaddr)
|
||||
free_init_pages("prom memory", saddr, eaddr);
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return txx9_system_type;
|
||||
}
|
||||
|
||||
const char *__init prom_getenv(const char *name)
|
||||
{
|
||||
const s32 *str;
|
||||
|
||||
if (fw_arg2 < CKSEG0)
|
||||
return NULL;
|
||||
|
||||
str = (const s32 *)fw_arg2;
|
||||
/* YAMON style ("name", "value" pairs) */
|
||||
while (str[0] && str[1]) {
|
||||
if (!strcmp((const char *)(unsigned long)str[0], name))
|
||||
return (const char *)(unsigned long)str[1];
|
||||
str += 2;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __noreturn txx9_machine_halt(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
clear_c0_status(ST0_IM);
|
||||
while (1) {
|
||||
if (cpu_wait) {
|
||||
(*cpu_wait)();
|
||||
if (cpu_has_counter) {
|
||||
/*
|
||||
* Clear counter interrupt while it
|
||||
* breaks WAIT instruction even if
|
||||
* masked.
|
||||
*/
|
||||
write_c0_compare(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Watchdog support */
|
||||
void __init txx9_wdt_init(unsigned long base)
|
||||
{
|
||||
struct resource res = {
|
||||
.start = base,
|
||||
.end = base + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
platform_device_register_simple("txx9wdt", -1, &res, 1);
|
||||
}
|
||||
|
||||
void txx9_wdt_now(unsigned long base)
|
||||
{
|
||||
struct txx9_tmr_reg __iomem *tmrptr =
|
||||
ioremap(base, sizeof(struct txx9_tmr_reg));
|
||||
/* disable watch dog timer */
|
||||
__raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
|
||||
__raw_writel(0, &tmrptr->tcr);
|
||||
/* kick watchdog */
|
||||
__raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
|
||||
__raw_writel(1, &tmrptr->cpra); /* immediate */
|
||||
__raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
|
||||
&tmrptr->tcr);
|
||||
}
|
||||
|
||||
/* SPI support */
|
||||
void __init txx9_spi_init(int busid, unsigned long base, int irq)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = base,
|
||||
.end = base + 0x20 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
platform_device_register_simple("spi_txx9", busid,
|
||||
res, ARRAY_SIZE(res));
|
||||
}
|
||||
|
||||
void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
|
||||
{
|
||||
struct platform_device *pdev =
|
||||
platform_device_alloc("tc35815-mac", id);
|
||||
if (!pdev ||
|
||||
platform_device_add_data(pdev, ethaddr, 6) ||
|
||||
platform_device_add(pdev))
|
||||
platform_device_put(pdev);
|
||||
}
|
||||
|
||||
void __init txx9_sio_init(unsigned long baseaddr, int irq,
|
||||
unsigned int line, unsigned int sclk, int nocts)
|
||||
{
|
||||
#ifdef CONFIG_SERIAL_TXX9
|
||||
struct uart_port req;
|
||||
|
||||
memset(&req, 0, sizeof(req));
|
||||
req.line = line;
|
||||
req.iotype = UPIO_MEM;
|
||||
req.membase = ioremap(baseaddr, 0x24);
|
||||
req.mapbase = baseaddr;
|
||||
req.irq = irq;
|
||||
if (!nocts)
|
||||
req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
|
||||
if (sclk) {
|
||||
req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
|
||||
req.uartclk = sclk;
|
||||
} else
|
||||
req.uartclk = TXX9_IMCLK;
|
||||
early_serial_txx9_setup(&req);
|
||||
#endif /* CONFIG_SERIAL_TXX9 */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_EARLY_PRINTK
|
||||
static void null_prom_putchar(char c)
|
||||
{
|
||||
}
|
||||
void (*txx9_prom_putchar)(char c) = null_prom_putchar;
|
||||
|
||||
void prom_putchar(char c)
|
||||
{
|
||||
txx9_prom_putchar(c);
|
||||
}
|
||||
|
||||
static void __iomem *early_txx9_sio_port;
|
||||
|
||||
static void early_txx9_sio_putchar(char c)
|
||||
{
|
||||
#define TXX9_SICISR 0x0c
|
||||
#define TXX9_SITFIFO 0x1c
|
||||
#define TXX9_SICISR_TXALS 0x00000002
|
||||
while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
|
||||
TXX9_SICISR_TXALS))
|
||||
;
|
||||
__raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
|
||||
}
|
||||
|
||||
void __init txx9_sio_putchar_init(unsigned long baseaddr)
|
||||
{
|
||||
early_txx9_sio_port = ioremap(baseaddr, 0x24);
|
||||
txx9_prom_putchar = early_txx9_sio_putchar;
|
||||
}
|
||||
#endif /* CONFIG_EARLY_PRINTK */
|
||||
|
||||
/* wrappers */
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
ioport_resource.start = 0;
|
||||
ioport_resource.end = ~0UL; /* no limit */
|
||||
iomem_resource.start = 0;
|
||||
iomem_resource.end = ~0UL; /* no limit */
|
||||
|
||||
/* fallback restart/halt routines */
|
||||
_machine_restart = (void (*)(char *))txx9_machine_halt;
|
||||
_machine_halt = txx9_machine_halt;
|
||||
pm_power_off = txx9_machine_halt;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
pcibios_plat_setup = txx9_pcibios_setup;
|
||||
#endif
|
||||
txx9_board_vec->mem_setup();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
txx9_board_vec->irq_setup();
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CPU_TX49XX
|
||||
mips_hpt_frequency = txx9_cpu_clock / 2;
|
||||
#endif
|
||||
txx9_board_vec->time_init();
|
||||
}
|
||||
|
||||
static int __init _txx9_arch_init(void)
|
||||
{
|
||||
if (txx9_board_vec->arch_init)
|
||||
txx9_board_vec->arch_init();
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(_txx9_arch_init);
|
||||
|
||||
static int __init _txx9_device_init(void)
|
||||
{
|
||||
if (txx9_board_vec->device_init)
|
||||
txx9_board_vec->device_init();
|
||||
return 0;
|
||||
}
|
||||
device_initcall(_txx9_device_init);
|
||||
|
||||
int (*txx9_irq_dispatch)(int pending);
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
int irq = txx9_irq_dispatch(pending);
|
||||
|
||||
if (likely(irq >= 0))
|
||||
do_IRQ(irq);
|
||||
else
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
/* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
|
||||
#ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
|
||||
static unsigned long __swizzle_addr_none(unsigned long port)
|
||||
{
|
||||
return port;
|
||||
}
|
||||
unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
|
||||
EXPORT_SYMBOL(__swizzle_addr_b);
|
||||
#endif
|
||||
|
||||
#ifdef NEEDS_TXX9_IOSWABW
|
||||
static u16 ioswabw_default(volatile u16 *a, u16 x)
|
||||
{
|
||||
return le16_to_cpu(x);
|
||||
}
|
||||
static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
|
||||
{
|
||||
return x;
|
||||
}
|
||||
u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
|
||||
EXPORT_SYMBOL(ioswabw);
|
||||
u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
|
||||
EXPORT_SYMBOL(__mem_ioswabw);
|
||||
#endif
|
||||
|
||||
void __init txx9_physmap_flash_init(int no, unsigned long addr,
|
||||
unsigned long size,
|
||||
const struct physmap_flash_data *pdata)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
|
||||
struct resource res = {
|
||||
.start = addr,
|
||||
.end = addr + size - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
struct platform_device *pdev;
|
||||
static struct mtd_partition parts[2];
|
||||
struct physmap_flash_data pdata_part;
|
||||
|
||||
/* If this area contained boot area, make separate partition */
|
||||
if (pdata->nr_parts == 0 && !pdata->parts &&
|
||||
addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
|
||||
!parts[0].name) {
|
||||
parts[0].name = "boot";
|
||||
parts[0].offset = 0x1fc00000 - addr;
|
||||
parts[0].size = addr + size - 0x1fc00000;
|
||||
parts[1].name = "user";
|
||||
parts[1].offset = 0;
|
||||
parts[1].size = 0x1fc00000 - addr;
|
||||
pdata_part = *pdata;
|
||||
pdata_part.nr_parts = ARRAY_SIZE(parts);
|
||||
pdata_part.parts = parts;
|
||||
pdata = &pdata_part;
|
||||
}
|
||||
|
||||
pdev = platform_device_alloc("physmap-flash", no);
|
||||
if (!pdev ||
|
||||
platform_device_add_resources(pdev, &res, 1) ||
|
||||
platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
|
||||
platform_device_add(pdev))
|
||||
platform_device_put(pdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init txx9_ndfmc_init(unsigned long baseaddr,
|
||||
const struct txx9ndfmc_platform_data *pdata)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC)
|
||||
struct resource res = {
|
||||
.start = baseaddr,
|
||||
.end = baseaddr + 0x1000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1);
|
||||
|
||||
if (!pdev ||
|
||||
platform_device_add_resources(pdev, &res, 1) ||
|
||||
platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
|
||||
platform_device_add(pdev))
|
||||
platform_device_put(pdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_LEDS_GPIO)
|
||||
static DEFINE_SPINLOCK(txx9_iocled_lock);
|
||||
|
||||
#define TXX9_IOCLED_MAXLEDS 8
|
||||
|
||||
struct txx9_iocled_data {
|
||||
struct gpio_chip chip;
|
||||
u8 cur_val;
|
||||
void __iomem *mmioaddr;
|
||||
struct gpio_led_platform_data pdata;
|
||||
struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
|
||||
char names[TXX9_IOCLED_MAXLEDS][32];
|
||||
};
|
||||
|
||||
static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct txx9_iocled_data *data =
|
||||
container_of(chip, struct txx9_iocled_data, chip);
|
||||
return data->cur_val & (1 << offset);
|
||||
}
|
||||
|
||||
static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct txx9_iocled_data *data =
|
||||
container_of(chip, struct txx9_iocled_data, chip);
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&txx9_iocled_lock, flags);
|
||||
if (value)
|
||||
data->cur_val |= 1 << offset;
|
||||
else
|
||||
data->cur_val &= ~(1 << offset);
|
||||
writeb(data->cur_val, data->mmioaddr);
|
||||
mmiowb();
|
||||
spin_unlock_irqrestore(&txx9_iocled_lock, flags);
|
||||
}
|
||||
|
||||
static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
txx9_iocled_set(chip, offset, value);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init txx9_iocled_init(unsigned long baseaddr,
|
||||
int basenum, unsigned int num, int lowactive,
|
||||
const char *color, char **deftriggers)
|
||||
{
|
||||
struct txx9_iocled_data *iocled;
|
||||
struct platform_device *pdev;
|
||||
int i;
|
||||
static char *default_triggers[] __initdata = {
|
||||
"heartbeat",
|
||||
"ide-disk",
|
||||
"nand-disk",
|
||||
NULL,
|
||||
};
|
||||
|
||||
if (!deftriggers)
|
||||
deftriggers = default_triggers;
|
||||
iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
|
||||
if (!iocled)
|
||||
return;
|
||||
iocled->mmioaddr = ioremap(baseaddr, 1);
|
||||
if (!iocled->mmioaddr)
|
||||
goto out_free;
|
||||
iocled->chip.get = txx9_iocled_get;
|
||||
iocled->chip.set = txx9_iocled_set;
|
||||
iocled->chip.direction_input = txx9_iocled_dir_in;
|
||||
iocled->chip.direction_output = txx9_iocled_dir_out;
|
||||
iocled->chip.label = "iocled";
|
||||
iocled->chip.base = basenum;
|
||||
iocled->chip.ngpio = num;
|
||||
if (gpiochip_add(&iocled->chip))
|
||||
goto out_unmap;
|
||||
if (basenum < 0)
|
||||
basenum = iocled->chip.base;
|
||||
|
||||
pdev = platform_device_alloc("leds-gpio", basenum);
|
||||
if (!pdev)
|
||||
goto out_gpio;
|
||||
iocled->pdata.num_leds = num;
|
||||
iocled->pdata.leds = iocled->leds;
|
||||
for (i = 0; i < num; i++) {
|
||||
struct gpio_led *led = &iocled->leds[i];
|
||||
snprintf(iocled->names[i], sizeof(iocled->names[i]),
|
||||
"iocled:%s:%u", color, i);
|
||||
led->name = iocled->names[i];
|
||||
led->gpio = basenum + i;
|
||||
led->active_low = lowactive;
|
||||
if (deftriggers && *deftriggers)
|
||||
led->default_trigger = *deftriggers++;
|
||||
}
|
||||
pdev->dev.platform_data = &iocled->pdata;
|
||||
if (platform_device_add(pdev))
|
||||
goto out_pdev;
|
||||
return;
|
||||
|
||||
out_pdev:
|
||||
platform_device_put(pdev);
|
||||
out_gpio:
|
||||
gpiochip_remove(&iocled->chip);
|
||||
out_unmap:
|
||||
iounmap(iocled->mmioaddr);
|
||||
out_free:
|
||||
kfree(iocled);
|
||||
}
|
||||
#else /* CONFIG_LEDS_GPIO */
|
||||
void __init txx9_iocled_init(unsigned long baseaddr,
|
||||
int basenum, unsigned int num, int lowactive,
|
||||
const char *color, char **deftriggers)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_LEDS_GPIO */
|
||||
|
||||
void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
|
||||
const struct txx9dmac_platform_data *pdata)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_TXX9_DMAC)
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = baseaddr,
|
||||
.end = baseaddr + 0x800 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
#ifndef CONFIG_MACH_TX49XX
|
||||
}, {
|
||||
.start = irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
#endif
|
||||
}
|
||||
};
|
||||
#ifdef CONFIG_MACH_TX49XX
|
||||
struct resource chan_res[] = {
|
||||
{
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
|
||||
struct txx9dmac_chan_platform_data cpdata;
|
||||
int i;
|
||||
|
||||
if (!pdev ||
|
||||
platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
|
||||
platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
|
||||
platform_device_add(pdev)) {
|
||||
platform_device_put(pdev);
|
||||
return;
|
||||
}
|
||||
memset(&cpdata, 0, sizeof(cpdata));
|
||||
cpdata.dmac_dev = pdev;
|
||||
for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
|
||||
#ifdef CONFIG_MACH_TX49XX
|
||||
chan_res[0].start = irq + i;
|
||||
#endif
|
||||
pdev = platform_device_alloc("txx9dmac-chan",
|
||||
id * TXX9_DMA_MAX_NR_CHANNELS + i);
|
||||
if (!pdev ||
|
||||
#ifdef CONFIG_MACH_TX49XX
|
||||
platform_device_add_resources(pdev, chan_res,
|
||||
ARRAY_SIZE(chan_res)) ||
|
||||
#endif
|
||||
platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
|
||||
platform_device_add(pdev))
|
||||
platform_device_put(pdev);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init txx9_aclc_init(unsigned long baseaddr, int irq,
|
||||
unsigned int dmac_id,
|
||||
unsigned int dma_chan_out,
|
||||
unsigned int dma_chan_in)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
|
||||
unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = baseaddr,
|
||||
.end = baseaddr + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.name = "txx9dmac-chan",
|
||||
.start = dma_base + dma_chan_out,
|
||||
.flags = IORESOURCE_DMA,
|
||||
}, {
|
||||
.name = "txx9dmac-chan",
|
||||
.start = dma_base + dma_chan_in,
|
||||
.flags = IORESOURCE_DMA,
|
||||
}
|
||||
};
|
||||
struct platform_device *pdev =
|
||||
platform_device_alloc("txx9aclc-ac97", -1);
|
||||
|
||||
if (!pdev ||
|
||||
platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
|
||||
platform_device_add(pdev))
|
||||
platform_device_put(pdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct bus_type txx9_sramc_subsys = {
|
||||
.name = "txx9_sram",
|
||||
.dev_name = "txx9_sram",
|
||||
};
|
||||
|
||||
struct txx9_sramc_dev {
|
||||
struct device dev;
|
||||
struct bin_attribute bindata_attr;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
static ssize_t txx9_sram_read(struct file *filp, struct kobject *kobj,
|
||||
struct bin_attribute *bin_attr,
|
||||
char *buf, loff_t pos, size_t size)
|
||||
{
|
||||
struct txx9_sramc_dev *dev = bin_attr->private;
|
||||
size_t ramsize = bin_attr->size;
|
||||
|
||||
if (pos >= ramsize)
|
||||
return 0;
|
||||
if (pos + size > ramsize)
|
||||
size = ramsize - pos;
|
||||
memcpy_fromio(buf, dev->base + pos, size);
|
||||
return size;
|
||||
}
|
||||
|
||||
static ssize_t txx9_sram_write(struct file *filp, struct kobject *kobj,
|
||||
struct bin_attribute *bin_attr,
|
||||
char *buf, loff_t pos, size_t size)
|
||||
{
|
||||
struct txx9_sramc_dev *dev = bin_attr->private;
|
||||
size_t ramsize = bin_attr->size;
|
||||
|
||||
if (pos >= ramsize)
|
||||
return 0;
|
||||
if (pos + size > ramsize)
|
||||
size = ramsize - pos;
|
||||
memcpy_toio(dev->base + pos, buf, size);
|
||||
return size;
|
||||
}
|
||||
|
||||
static void txx9_device_release(struct device *dev)
|
||||
{
|
||||
struct txx9_sramc_dev *tdev;
|
||||
|
||||
tdev = container_of(dev, struct txx9_sramc_dev, dev);
|
||||
kfree(tdev);
|
||||
}
|
||||
|
||||
void __init txx9_sramc_init(struct resource *r)
|
||||
{
|
||||
struct txx9_sramc_dev *dev;
|
||||
size_t size;
|
||||
int err;
|
||||
|
||||
err = subsys_system_register(&txx9_sramc_subsys, NULL);
|
||||
if (err)
|
||||
return;
|
||||
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
||||
if (!dev)
|
||||
return;
|
||||
size = resource_size(r);
|
||||
dev->base = ioremap(r->start, size);
|
||||
if (!dev->base) {
|
||||
kfree(dev);
|
||||
return;
|
||||
}
|
||||
dev->dev.release = &txx9_device_release;
|
||||
dev->dev.bus = &txx9_sramc_subsys;
|
||||
sysfs_bin_attr_init(&dev->bindata_attr);
|
||||
dev->bindata_attr.attr.name = "bindata";
|
||||
dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
|
||||
dev->bindata_attr.read = txx9_sram_read;
|
||||
dev->bindata_attr.write = txx9_sram_write;
|
||||
dev->bindata_attr.size = size;
|
||||
dev->bindata_attr.private = dev;
|
||||
err = device_register(&dev->dev);
|
||||
if (err)
|
||||
goto exit_put;
|
||||
err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
|
||||
if (err) {
|
||||
device_unregister(&dev->dev);
|
||||
iounmap(dev->base);
|
||||
kfree(dev);
|
||||
}
|
||||
return;
|
||||
exit_put:
|
||||
put_device(&dev->dev);
|
||||
return;
|
||||
}
|
||||
137
arch/mips/txx9/generic/setup_tx3927.c
Normal file
137
arch/mips/txx9/generic/setup_tx3927.c
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* TX3927 setup routines
|
||||
* Based on linux/arch/mips/txx9/jmr3927/setup.c
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9tmr.h>
|
||||
#include <asm/txx9pio.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/tx3927.h>
|
||||
|
||||
void __init tx3927_wdt_init(void)
|
||||
{
|
||||
txx9_wdt_init(TX3927_TMR_REG(2));
|
||||
}
|
||||
|
||||
void __init tx3927_setup(void)
|
||||
{
|
||||
int i;
|
||||
unsigned int conf;
|
||||
|
||||
txx9_reg_res_init(TX3927_REV_PCODE(), TX3927_REG_BASE,
|
||||
TX3927_REG_SIZE);
|
||||
|
||||
/* SDRAMC,ROMC are configured by PROM */
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (!(tx3927_romcptr->cr[i] & 0x8))
|
||||
continue; /* disabled */
|
||||
txx9_ce_res[i].start = (unsigned long)TX3927_ROMC_BA(i);
|
||||
txx9_ce_res[i].end =
|
||||
txx9_ce_res[i].start + TX3927_ROMC_SIZE(i) - 1;
|
||||
request_resource(&iomem_resource, &txx9_ce_res[i]);
|
||||
}
|
||||
|
||||
/* clocks */
|
||||
txx9_gbus_clock = txx9_cpu_clock / 2;
|
||||
/* change default value to udelay/mdelay take reasonable time */
|
||||
loops_per_jiffy = txx9_cpu_clock / HZ / 2;
|
||||
|
||||
/* CCFG */
|
||||
/* enable Timeout BusError */
|
||||
if (txx9_ccfg_toeon)
|
||||
tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
|
||||
|
||||
/* clear BusErrorOnWrite flag */
|
||||
tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
|
||||
if (read_c0_conf() & TX39_CONF_WBON)
|
||||
/* Disable PCI snoop */
|
||||
tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
|
||||
else
|
||||
/* Enable PCI SNOOP - with write through only */
|
||||
tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
|
||||
/* do reset on watchdog */
|
||||
tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
|
||||
|
||||
printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
|
||||
tx3927_ccfgptr->crir,
|
||||
tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
|
||||
|
||||
/* TMR */
|
||||
for (i = 0; i < TX3927_NR_TMR; i++)
|
||||
txx9_tmr_init(TX3927_TMR_REG(i));
|
||||
|
||||
/* DMA */
|
||||
tx3927_dmaptr->mcr = 0;
|
||||
for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
|
||||
/* reset channel */
|
||||
tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
|
||||
tx3927_dmaptr->ch[i].ccr = 0;
|
||||
}
|
||||
/* enable DMA */
|
||||
#ifdef __BIG_ENDIAN
|
||||
tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
|
||||
#else
|
||||
tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
|
||||
#endif
|
||||
|
||||
/* PIO */
|
||||
__raw_writel(0, &tx3927_pioptr->maskcpu);
|
||||
__raw_writel(0, &tx3927_pioptr->maskext);
|
||||
txx9_gpio_init(TX3927_PIO_REG, 0, 16);
|
||||
|
||||
conf = read_c0_conf();
|
||||
if (conf & TX39_CONF_DCE) {
|
||||
if (!(conf & TX39_CONF_WBON))
|
||||
pr_info("TX3927 D-Cache WriteThrough.\n");
|
||||
else if (!(conf & TX39_CONF_CWFON))
|
||||
pr_info("TX3927 D-Cache WriteBack.\n");
|
||||
else
|
||||
pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
|
||||
}
|
||||
}
|
||||
|
||||
void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
|
||||
{
|
||||
txx9_clockevent_init(TX3927_TMR_REG(evt_tmrnr),
|
||||
TXX9_IRQ_BASE + TX3927_IR_TMR(evt_tmrnr),
|
||||
TXX9_IMCLK);
|
||||
txx9_clocksource_init(TX3927_TMR_REG(src_tmrnr), TXX9_IMCLK);
|
||||
}
|
||||
|
||||
void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
txx9_sio_init(TX3927_SIO_REG(i),
|
||||
TXX9_IRQ_BASE + TX3927_IR_SIO(i),
|
||||
i, sclk, (1 << i) & cts_mask);
|
||||
}
|
||||
|
||||
void __init tx3927_mtd_init(int ch)
|
||||
{
|
||||
struct physmap_flash_data pdata = {
|
||||
.width = TX3927_ROMC_WIDTH(ch) / 8,
|
||||
};
|
||||
unsigned long start = txx9_ce_res[ch].start;
|
||||
unsigned long size = txx9_ce_res[ch].end - start + 1;
|
||||
|
||||
if (!(tx3927_romcptr->cr[ch] & 0x8))
|
||||
return; /* disabled */
|
||||
txx9_physmap_flash_init(ch, start, size, &pdata);
|
||||
}
|
||||
340
arch/mips/txx9/generic/setup_tx4927.c
Normal file
340
arch/mips/txx9/generic/setup_tx4927.c
Normal file
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* TX4927 setup routines
|
||||
* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
|
||||
* and RBTX49xx patch from CELF patch archive.
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc.
|
||||
* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9tmr.h>
|
||||
#include <asm/txx9pio.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/dmac.h>
|
||||
#include <asm/txx9/tx4927.h>
|
||||
|
||||
static void __init tx4927_wdr_init(void)
|
||||
{
|
||||
/* report watchdog reset status */
|
||||
if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST)
|
||||
pr_warning("Watchdog reset detected at 0x%lx\n",
|
||||
read_c0_errorepc());
|
||||
/* clear WatchDogReset (W1C) */
|
||||
tx4927_ccfg_set(TX4927_CCFG_WDRST);
|
||||
/* do reset on watchdog */
|
||||
tx4927_ccfg_set(TX4927_CCFG_WR);
|
||||
}
|
||||
|
||||
void __init tx4927_wdt_init(void)
|
||||
{
|
||||
txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
|
||||
}
|
||||
|
||||
static void tx4927_machine_restart(char *command)
|
||||
{
|
||||
local_irq_disable();
|
||||
pr_emerg("Rebooting (with %s watchdog reset)...\n",
|
||||
(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) ?
|
||||
"external" : "internal");
|
||||
/* clear watchdog status */
|
||||
tx4927_ccfg_set(TX4927_CCFG_WDRST); /* W1C */
|
||||
txx9_wdt_now(TX4927_TMR_REG(2) & 0xfffffffffULL);
|
||||
while (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST))
|
||||
;
|
||||
mdelay(10);
|
||||
if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) {
|
||||
pr_emerg("Rebooting (with internal watchdog reset)...\n");
|
||||
/* External WDRST failed. Do internal watchdog reset */
|
||||
tx4927_ccfg_clear(TX4927_CCFG_WDREXEN);
|
||||
}
|
||||
/* fallback */
|
||||
(*_machine_halt)();
|
||||
}
|
||||
|
||||
void show_registers(struct pt_regs *regs);
|
||||
static int tx4927_be_handler(struct pt_regs *regs, int is_fixup)
|
||||
{
|
||||
int data = regs->cp0_cause & 4;
|
||||
console_verbose();
|
||||
pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
|
||||
pr_err("ccfg:%llx, toea:%llx\n",
|
||||
(unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4927_ccfgptr->toea));
|
||||
#ifdef CONFIG_PCI
|
||||
tx4927_report_pcic_status();
|
||||
#endif
|
||||
show_registers(regs);
|
||||
panic("BusError!");
|
||||
}
|
||||
static void __init tx4927_be_init(void)
|
||||
{
|
||||
board_be_handler = tx4927_be_handler;
|
||||
}
|
||||
|
||||
static struct resource tx4927_sdram_resource[4];
|
||||
|
||||
void __init tx4927_setup(void)
|
||||
{
|
||||
int i;
|
||||
__u32 divmode;
|
||||
unsigned int cpuclk = 0;
|
||||
u64 ccfg;
|
||||
|
||||
txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
|
||||
TX4927_REG_SIZE);
|
||||
set_c0_config(TX49_CONF_CWFON);
|
||||
|
||||
/* SDRAMC,EBUSC are configured by PROM */
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (!(TX4927_EBUSC_CR(i) & 0x8))
|
||||
continue; /* disabled */
|
||||
txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
|
||||
txx9_ce_res[i].end =
|
||||
txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
|
||||
request_resource(&iomem_resource, &txx9_ce_res[i]);
|
||||
}
|
||||
|
||||
/* clocks */
|
||||
ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
|
||||
if (txx9_master_clock) {
|
||||
/* calculate gbus_clock and cpu_clock from master_clock */
|
||||
divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
|
||||
switch (divmode) {
|
||||
case TX4927_CCFG_DIVMODE_8:
|
||||
case TX4927_CCFG_DIVMODE_10:
|
||||
case TX4927_CCFG_DIVMODE_12:
|
||||
case TX4927_CCFG_DIVMODE_16:
|
||||
txx9_gbus_clock = txx9_master_clock * 4; break;
|
||||
default:
|
||||
txx9_gbus_clock = txx9_master_clock;
|
||||
}
|
||||
switch (divmode) {
|
||||
case TX4927_CCFG_DIVMODE_2:
|
||||
case TX4927_CCFG_DIVMODE_8:
|
||||
cpuclk = txx9_gbus_clock * 2; break;
|
||||
case TX4927_CCFG_DIVMODE_2_5:
|
||||
case TX4927_CCFG_DIVMODE_10:
|
||||
cpuclk = txx9_gbus_clock * 5 / 2; break;
|
||||
case TX4927_CCFG_DIVMODE_3:
|
||||
case TX4927_CCFG_DIVMODE_12:
|
||||
cpuclk = txx9_gbus_clock * 3; break;
|
||||
case TX4927_CCFG_DIVMODE_4:
|
||||
case TX4927_CCFG_DIVMODE_16:
|
||||
cpuclk = txx9_gbus_clock * 4; break;
|
||||
}
|
||||
txx9_cpu_clock = cpuclk;
|
||||
} else {
|
||||
if (txx9_cpu_clock == 0)
|
||||
txx9_cpu_clock = 200000000; /* 200MHz */
|
||||
/* calculate gbus_clock and master_clock from cpu_clock */
|
||||
cpuclk = txx9_cpu_clock;
|
||||
divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
|
||||
switch (divmode) {
|
||||
case TX4927_CCFG_DIVMODE_2:
|
||||
case TX4927_CCFG_DIVMODE_8:
|
||||
txx9_gbus_clock = cpuclk / 2; break;
|
||||
case TX4927_CCFG_DIVMODE_2_5:
|
||||
case TX4927_CCFG_DIVMODE_10:
|
||||
txx9_gbus_clock = cpuclk * 2 / 5; break;
|
||||
case TX4927_CCFG_DIVMODE_3:
|
||||
case TX4927_CCFG_DIVMODE_12:
|
||||
txx9_gbus_clock = cpuclk / 3; break;
|
||||
case TX4927_CCFG_DIVMODE_4:
|
||||
case TX4927_CCFG_DIVMODE_16:
|
||||
txx9_gbus_clock = cpuclk / 4; break;
|
||||
}
|
||||
switch (divmode) {
|
||||
case TX4927_CCFG_DIVMODE_8:
|
||||
case TX4927_CCFG_DIVMODE_10:
|
||||
case TX4927_CCFG_DIVMODE_12:
|
||||
case TX4927_CCFG_DIVMODE_16:
|
||||
txx9_master_clock = txx9_gbus_clock / 4; break;
|
||||
default:
|
||||
txx9_master_clock = txx9_gbus_clock;
|
||||
}
|
||||
}
|
||||
/* change default value to udelay/mdelay take reasonable time */
|
||||
loops_per_jiffy = txx9_cpu_clock / HZ / 2;
|
||||
|
||||
/* CCFG */
|
||||
tx4927_wdr_init();
|
||||
/* clear BusErrorOnWrite flag (W1C) */
|
||||
tx4927_ccfg_set(TX4927_CCFG_BEOW);
|
||||
/* enable Timeout BusError */
|
||||
if (txx9_ccfg_toeon)
|
||||
tx4927_ccfg_set(TX4927_CCFG_TOE);
|
||||
|
||||
/* DMA selection */
|
||||
txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
|
||||
|
||||
/* Use external clock for external arbiter */
|
||||
if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
|
||||
txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
|
||||
|
||||
printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
|
||||
txx9_pcode_str,
|
||||
(cpuclk + 500000) / 1000000,
|
||||
(txx9_master_clock + 500000) / 1000000,
|
||||
(__u32)____raw_readq(&tx4927_ccfgptr->crir),
|
||||
(unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
|
||||
|
||||
printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
|
||||
for (i = 0; i < 4; i++) {
|
||||
__u64 cr = TX4927_SDRAMC_CR(i);
|
||||
unsigned long base, size;
|
||||
if (!((__u32)cr & 0x00000400))
|
||||
continue; /* disabled */
|
||||
base = (unsigned long)(cr >> 49) << 21;
|
||||
size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
|
||||
printk(" CR%d:%016llx", i, (unsigned long long)cr);
|
||||
tx4927_sdram_resource[i].name = "SDRAM";
|
||||
tx4927_sdram_resource[i].start = base;
|
||||
tx4927_sdram_resource[i].end = base + size - 1;
|
||||
tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
|
||||
}
|
||||
printk(" TR:%09llx\n",
|
||||
(unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
|
||||
|
||||
/* TMR */
|
||||
/* disable all timers */
|
||||
for (i = 0; i < TX4927_NR_TMR; i++)
|
||||
txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
|
||||
|
||||
/* PIO */
|
||||
txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
|
||||
__raw_writel(0, &tx4927_pioptr->maskcpu);
|
||||
__raw_writel(0, &tx4927_pioptr->maskext);
|
||||
|
||||
_machine_restart = tx4927_machine_restart;
|
||||
board_be_init = tx4927_be_init;
|
||||
}
|
||||
|
||||
void __init tx4927_time_init(unsigned int tmrnr)
|
||||
{
|
||||
if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
|
||||
txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
|
||||
TXX9_IMCLK);
|
||||
}
|
||||
|
||||
void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4927_IR_SIO(i),
|
||||
i, sclk, (1 << i) & cts_mask);
|
||||
}
|
||||
|
||||
void __init tx4927_mtd_init(int ch)
|
||||
{
|
||||
struct physmap_flash_data pdata = {
|
||||
.width = TX4927_EBUSC_WIDTH(ch) / 8,
|
||||
};
|
||||
unsigned long start = txx9_ce_res[ch].start;
|
||||
unsigned long size = txx9_ce_res[ch].end - start + 1;
|
||||
|
||||
if (!(TX4927_EBUSC_CR(ch) & 0x8))
|
||||
return; /* disabled */
|
||||
txx9_physmap_flash_init(ch, start, size, &pdata);
|
||||
}
|
||||
|
||||
void __init tx4927_dmac_init(int memcpy_chan)
|
||||
{
|
||||
struct txx9dmac_platform_data plat_data = {
|
||||
.memcpy_chan = memcpy_chan,
|
||||
.have_64bit_regs = true,
|
||||
};
|
||||
|
||||
txx9_dmac_init(0, TX4927_DMA_REG & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4927_IR_DMA(0), &plat_data);
|
||||
}
|
||||
|
||||
void __init tx4927_aclc_init(unsigned int dma_chan_out,
|
||||
unsigned int dma_chan_in)
|
||||
{
|
||||
u64 pcfg = __raw_readq(&tx4927_ccfgptr->pcfg);
|
||||
__u64 dmasel_mask = 0, dmasel = 0;
|
||||
unsigned long flags;
|
||||
|
||||
if (!(pcfg & TX4927_PCFG_SEL2))
|
||||
return;
|
||||
/* setup DMASEL (playback:ACLC ch0, capture:ACLC ch1) */
|
||||
switch (dma_chan_out) {
|
||||
case 0:
|
||||
dmasel_mask |= TX4927_PCFG_DMASEL0_MASK;
|
||||
dmasel |= TX4927_PCFG_DMASEL0_ACL0;
|
||||
break;
|
||||
case 2:
|
||||
dmasel_mask |= TX4927_PCFG_DMASEL2_MASK;
|
||||
dmasel |= TX4927_PCFG_DMASEL2_ACL0;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
switch (dma_chan_in) {
|
||||
case 1:
|
||||
dmasel_mask |= TX4927_PCFG_DMASEL1_MASK;
|
||||
dmasel |= TX4927_PCFG_DMASEL1_ACL1;
|
||||
break;
|
||||
case 3:
|
||||
dmasel_mask |= TX4927_PCFG_DMASEL3_MASK;
|
||||
dmasel |= TX4927_PCFG_DMASEL3_ACL1;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
local_irq_save(flags);
|
||||
txx9_clear64(&tx4927_ccfgptr->pcfg, dmasel_mask);
|
||||
txx9_set64(&tx4927_ccfgptr->pcfg, dmasel);
|
||||
local_irq_restore(flags);
|
||||
txx9_aclc_init(TX4927_ACLC_REG & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4927_IR_ACLC,
|
||||
0, dma_chan_out, dma_chan_in);
|
||||
}
|
||||
|
||||
static void __init tx4927_stop_unused_modules(void)
|
||||
{
|
||||
__u64 pcfg, rst = 0, ckd = 0;
|
||||
char buf[128];
|
||||
|
||||
buf[0] = '\0';
|
||||
local_irq_disable();
|
||||
pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg);
|
||||
if (!(pcfg & TX4927_PCFG_SEL2)) {
|
||||
rst |= TX4927_CLKCTR_ACLRST;
|
||||
ckd |= TX4927_CLKCTR_ACLCKD;
|
||||
strcat(buf, " ACLC");
|
||||
}
|
||||
if (rst | ckd) {
|
||||
txx9_set64(&tx4927_ccfgptr->clkctr, rst);
|
||||
txx9_set64(&tx4927_ccfgptr->clkctr, ckd);
|
||||
}
|
||||
local_irq_enable();
|
||||
if (buf[0])
|
||||
pr_info("%s: stop%s\n", txx9_pcode_str, buf);
|
||||
}
|
||||
|
||||
static int __init tx4927_late_init(void)
|
||||
{
|
||||
if (txx9_pcode != 0x4927)
|
||||
return -ENODEV;
|
||||
tx4927_stop_unused_modules();
|
||||
return 0;
|
||||
}
|
||||
late_initcall(tx4927_late_init);
|
||||
488
arch/mips/txx9/generic/setup_tx4938.c
Normal file
488
arch/mips/txx9/generic/setup_tx4938.c
Normal file
|
|
@ -0,0 +1,488 @@
|
|||
/*
|
||||
* TX4938/4937 setup routines
|
||||
* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
|
||||
* and RBTX49xx patch from CELF patch archive.
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc.
|
||||
* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9tmr.h>
|
||||
#include <asm/txx9pio.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/ndfmc.h>
|
||||
#include <asm/txx9/dmac.h>
|
||||
#include <asm/txx9/tx4938.h>
|
||||
|
||||
static void __init tx4938_wdr_init(void)
|
||||
{
|
||||
/* report watchdog reset status */
|
||||
if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)
|
||||
pr_warning("Watchdog reset detected at 0x%lx\n",
|
||||
read_c0_errorepc());
|
||||
/* clear WatchDogReset (W1C) */
|
||||
tx4938_ccfg_set(TX4938_CCFG_WDRST);
|
||||
/* do reset on watchdog */
|
||||
tx4938_ccfg_set(TX4938_CCFG_WR);
|
||||
}
|
||||
|
||||
void __init tx4938_wdt_init(void)
|
||||
{
|
||||
txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
|
||||
}
|
||||
|
||||
static void tx4938_machine_restart(char *command)
|
||||
{
|
||||
local_irq_disable();
|
||||
pr_emerg("Rebooting (with %s watchdog reset)...\n",
|
||||
(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ?
|
||||
"external" : "internal");
|
||||
/* clear watchdog status */
|
||||
tx4938_ccfg_set(TX4938_CCFG_WDRST); /* W1C */
|
||||
txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL);
|
||||
while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST))
|
||||
;
|
||||
mdelay(10);
|
||||
if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) {
|
||||
pr_emerg("Rebooting (with internal watchdog reset)...\n");
|
||||
/* External WDRST failed. Do internal watchdog reset */
|
||||
tx4938_ccfg_clear(TX4938_CCFG_WDREXEN);
|
||||
}
|
||||
/* fallback */
|
||||
(*_machine_halt)();
|
||||
}
|
||||
|
||||
void show_registers(struct pt_regs *regs);
|
||||
static int tx4938_be_handler(struct pt_regs *regs, int is_fixup)
|
||||
{
|
||||
int data = regs->cp0_cause & 4;
|
||||
console_verbose();
|
||||
pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
|
||||
pr_err("ccfg:%llx, toea:%llx\n",
|
||||
(unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4938_ccfgptr->toea));
|
||||
#ifdef CONFIG_PCI
|
||||
tx4927_report_pcic_status();
|
||||
#endif
|
||||
show_registers(regs);
|
||||
panic("BusError!");
|
||||
}
|
||||
static void __init tx4938_be_init(void)
|
||||
{
|
||||
board_be_handler = tx4938_be_handler;
|
||||
}
|
||||
|
||||
static struct resource tx4938_sdram_resource[4];
|
||||
static struct resource tx4938_sram_resource;
|
||||
|
||||
#define TX4938_SRAM_SIZE 0x800
|
||||
|
||||
void __init tx4938_setup(void)
|
||||
{
|
||||
int i;
|
||||
__u32 divmode;
|
||||
unsigned int cpuclk = 0;
|
||||
u64 ccfg;
|
||||
|
||||
txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
|
||||
TX4938_REG_SIZE);
|
||||
set_c0_config(TX49_CONF_CWFON);
|
||||
|
||||
/* SDRAMC,EBUSC are configured by PROM */
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (!(TX4938_EBUSC_CR(i) & 0x8))
|
||||
continue; /* disabled */
|
||||
txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
|
||||
txx9_ce_res[i].end =
|
||||
txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
|
||||
request_resource(&iomem_resource, &txx9_ce_res[i]);
|
||||
}
|
||||
|
||||
/* clocks */
|
||||
ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
|
||||
if (txx9_master_clock) {
|
||||
/* calculate gbus_clock and cpu_clock from master_clock */
|
||||
divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
|
||||
switch (divmode) {
|
||||
case TX4938_CCFG_DIVMODE_8:
|
||||
case TX4938_CCFG_DIVMODE_10:
|
||||
case TX4938_CCFG_DIVMODE_12:
|
||||
case TX4938_CCFG_DIVMODE_16:
|
||||
case TX4938_CCFG_DIVMODE_18:
|
||||
txx9_gbus_clock = txx9_master_clock * 4; break;
|
||||
default:
|
||||
txx9_gbus_clock = txx9_master_clock;
|
||||
}
|
||||
switch (divmode) {
|
||||
case TX4938_CCFG_DIVMODE_2:
|
||||
case TX4938_CCFG_DIVMODE_8:
|
||||
cpuclk = txx9_gbus_clock * 2; break;
|
||||
case TX4938_CCFG_DIVMODE_2_5:
|
||||
case TX4938_CCFG_DIVMODE_10:
|
||||
cpuclk = txx9_gbus_clock * 5 / 2; break;
|
||||
case TX4938_CCFG_DIVMODE_3:
|
||||
case TX4938_CCFG_DIVMODE_12:
|
||||
cpuclk = txx9_gbus_clock * 3; break;
|
||||
case TX4938_CCFG_DIVMODE_4:
|
||||
case TX4938_CCFG_DIVMODE_16:
|
||||
cpuclk = txx9_gbus_clock * 4; break;
|
||||
case TX4938_CCFG_DIVMODE_4_5:
|
||||
case TX4938_CCFG_DIVMODE_18:
|
||||
cpuclk = txx9_gbus_clock * 9 / 2; break;
|
||||
}
|
||||
txx9_cpu_clock = cpuclk;
|
||||
} else {
|
||||
if (txx9_cpu_clock == 0)
|
||||
txx9_cpu_clock = 300000000; /* 300MHz */
|
||||
/* calculate gbus_clock and master_clock from cpu_clock */
|
||||
cpuclk = txx9_cpu_clock;
|
||||
divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
|
||||
switch (divmode) {
|
||||
case TX4938_CCFG_DIVMODE_2:
|
||||
case TX4938_CCFG_DIVMODE_8:
|
||||
txx9_gbus_clock = cpuclk / 2; break;
|
||||
case TX4938_CCFG_DIVMODE_2_5:
|
||||
case TX4938_CCFG_DIVMODE_10:
|
||||
txx9_gbus_clock = cpuclk * 2 / 5; break;
|
||||
case TX4938_CCFG_DIVMODE_3:
|
||||
case TX4938_CCFG_DIVMODE_12:
|
||||
txx9_gbus_clock = cpuclk / 3; break;
|
||||
case TX4938_CCFG_DIVMODE_4:
|
||||
case TX4938_CCFG_DIVMODE_16:
|
||||
txx9_gbus_clock = cpuclk / 4; break;
|
||||
case TX4938_CCFG_DIVMODE_4_5:
|
||||
case TX4938_CCFG_DIVMODE_18:
|
||||
txx9_gbus_clock = cpuclk * 2 / 9; break;
|
||||
}
|
||||
switch (divmode) {
|
||||
case TX4938_CCFG_DIVMODE_8:
|
||||
case TX4938_CCFG_DIVMODE_10:
|
||||
case TX4938_CCFG_DIVMODE_12:
|
||||
case TX4938_CCFG_DIVMODE_16:
|
||||
case TX4938_CCFG_DIVMODE_18:
|
||||
txx9_master_clock = txx9_gbus_clock / 4; break;
|
||||
default:
|
||||
txx9_master_clock = txx9_gbus_clock;
|
||||
}
|
||||
}
|
||||
/* change default value to udelay/mdelay take reasonable time */
|
||||
loops_per_jiffy = txx9_cpu_clock / HZ / 2;
|
||||
|
||||
/* CCFG */
|
||||
tx4938_wdr_init();
|
||||
/* clear BusErrorOnWrite flag (W1C) */
|
||||
tx4938_ccfg_set(TX4938_CCFG_BEOW);
|
||||
/* enable Timeout BusError */
|
||||
if (txx9_ccfg_toeon)
|
||||
tx4938_ccfg_set(TX4938_CCFG_TOE);
|
||||
|
||||
/* DMA selection */
|
||||
txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
|
||||
|
||||
/* Use external clock for external arbiter */
|
||||
if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
|
||||
txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
|
||||
|
||||
printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
|
||||
txx9_pcode_str,
|
||||
(cpuclk + 500000) / 1000000,
|
||||
(txx9_master_clock + 500000) / 1000000,
|
||||
(__u32)____raw_readq(&tx4938_ccfgptr->crir),
|
||||
(unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
|
||||
|
||||
printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
|
||||
for (i = 0; i < 4; i++) {
|
||||
__u64 cr = TX4938_SDRAMC_CR(i);
|
||||
unsigned long base, size;
|
||||
if (!((__u32)cr & 0x00000400))
|
||||
continue; /* disabled */
|
||||
base = (unsigned long)(cr >> 49) << 21;
|
||||
size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
|
||||
printk(" CR%d:%016llx", i, (unsigned long long)cr);
|
||||
tx4938_sdram_resource[i].name = "SDRAM";
|
||||
tx4938_sdram_resource[i].start = base;
|
||||
tx4938_sdram_resource[i].end = base + size - 1;
|
||||
tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
|
||||
}
|
||||
printk(" TR:%09llx\n",
|
||||
(unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
|
||||
|
||||
/* SRAM */
|
||||
if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
|
||||
unsigned int size = TX4938_SRAM_SIZE;
|
||||
tx4938_sram_resource.name = "SRAM";
|
||||
tx4938_sram_resource.start =
|
||||
(____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
|
||||
& ~(size - 1);
|
||||
tx4938_sram_resource.end =
|
||||
tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
|
||||
tx4938_sram_resource.flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4938_sram_resource);
|
||||
}
|
||||
|
||||
/* TMR */
|
||||
/* disable all timers */
|
||||
for (i = 0; i < TX4938_NR_TMR; i++)
|
||||
txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
|
||||
|
||||
/* PIO */
|
||||
txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
|
||||
__raw_writel(0, &tx4938_pioptr->maskcpu);
|
||||
__raw_writel(0, &tx4938_pioptr->maskext);
|
||||
|
||||
if (txx9_pcode == 0x4938) {
|
||||
__u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
|
||||
/* set PCIC1 reset */
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
|
||||
if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
|
||||
mdelay(1); /* at least 128 cpu clock */
|
||||
/* clear PCIC1 reset */
|
||||
txx9_clear64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_PCIC1RST);
|
||||
} else {
|
||||
printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
|
||||
/* stop PCIC1 */
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_PCIC1CKD);
|
||||
}
|
||||
if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
|
||||
printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_ETH0RST);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_ETH0CKD);
|
||||
}
|
||||
if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
|
||||
printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_ETH1RST);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_ETH1CKD);
|
||||
}
|
||||
}
|
||||
|
||||
_machine_restart = tx4938_machine_restart;
|
||||
board_be_init = tx4938_be_init;
|
||||
}
|
||||
|
||||
void __init tx4938_time_init(unsigned int tmrnr)
|
||||
{
|
||||
if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
|
||||
txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
|
||||
TXX9_IMCLK);
|
||||
}
|
||||
|
||||
void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask)
|
||||
{
|
||||
int i;
|
||||
unsigned int ch_mask = 0;
|
||||
|
||||
if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
|
||||
ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
|
||||
for (i = 0; i < 2; i++) {
|
||||
if ((1 << i) & ch_mask)
|
||||
continue;
|
||||
txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4938_IR_SIO(i),
|
||||
i, sclk, (1 << i) & cts_mask);
|
||||
}
|
||||
}
|
||||
|
||||
void __init tx4938_spi_init(int busid)
|
||||
{
|
||||
txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4938_IR_SPI);
|
||||
}
|
||||
|
||||
void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
|
||||
{
|
||||
u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
|
||||
|
||||
if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL))
|
||||
txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0);
|
||||
if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
|
||||
txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
|
||||
}
|
||||
|
||||
void __init tx4938_mtd_init(int ch)
|
||||
{
|
||||
struct physmap_flash_data pdata = {
|
||||
.width = TX4938_EBUSC_WIDTH(ch) / 8,
|
||||
};
|
||||
unsigned long start = txx9_ce_res[ch].start;
|
||||
unsigned long size = txx9_ce_res[ch].end - start + 1;
|
||||
|
||||
if (!(TX4938_EBUSC_CR(ch) & 0x8))
|
||||
return; /* disabled */
|
||||
txx9_physmap_flash_init(ch, start, size, &pdata);
|
||||
}
|
||||
|
||||
void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
struct resource res[] = {
|
||||
{
|
||||
/* .start and .end are filled in later */
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
struct tx4938ide_platform_info pdata = {
|
||||
.ioport_shift = shift,
|
||||
/*
|
||||
* The IDE driver should not change bus timings if other ISA
|
||||
* devices existed.
|
||||
*/
|
||||
.gbus_clock = tune ? txx9_gbus_clock : 0,
|
||||
};
|
||||
u64 ebccr;
|
||||
int i;
|
||||
|
||||
if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
|
||||
(TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL))
|
||||
!= TX4938_PCFG_ATA_SEL)
|
||||
return;
|
||||
for (i = 0; i < 8; i++) {
|
||||
/* check EBCCRn.ISA, EBCCRn.BSZ, EBCCRn.ME */
|
||||
ebccr = __raw_readq(&tx4938_ebuscptr->cr[i]);
|
||||
if ((ebccr & 0x00f00008) == 0x00e00008)
|
||||
break;
|
||||
}
|
||||
if (i == 8)
|
||||
return;
|
||||
pdata.ebus_ch = i;
|
||||
res[0].start = ((ebccr >> 48) << 20) + 0x10000;
|
||||
res[0].end = res[0].start + 0x20000 - 1;
|
||||
pdev = platform_device_alloc("tx4938ide", -1);
|
||||
if (!pdev ||
|
||||
platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
|
||||
platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
|
||||
platform_device_add(pdev))
|
||||
platform_device_put(pdev);
|
||||
}
|
||||
|
||||
void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw)
|
||||
{
|
||||
struct txx9ndfmc_platform_data plat_data = {
|
||||
.shift = 1,
|
||||
.gbus_clock = txx9_gbus_clock,
|
||||
.hold = hold,
|
||||
.spw = spw,
|
||||
.ch_mask = 1,
|
||||
};
|
||||
unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL;
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
baseaddr += 4;
|
||||
#endif
|
||||
if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
|
||||
(TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) ==
|
||||
TX4938_PCFG_NDF_SEL)
|
||||
txx9_ndfmc_init(baseaddr, &plat_data);
|
||||
}
|
||||
|
||||
void __init tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1)
|
||||
{
|
||||
struct txx9dmac_platform_data plat_data = {
|
||||
.have_64bit_regs = true,
|
||||
};
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
|
||||
txx9_dmac_init(i, TX4938_DMA_REG(i) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4938_IR_DMA(i, 0),
|
||||
&plat_data);
|
||||
}
|
||||
}
|
||||
|
||||
void __init tx4938_aclc_init(void)
|
||||
{
|
||||
u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
|
||||
|
||||
if ((pcfg & TX4938_PCFG_SEL2) &&
|
||||
!(pcfg & TX4938_PCFG_ETH0_SEL))
|
||||
txx9_aclc_init(TX4938_ACLC_REG & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4938_IR_ACLC,
|
||||
1, 0, 1);
|
||||
}
|
||||
|
||||
void __init tx4938_sramc_init(void)
|
||||
{
|
||||
if (tx4938_sram_resource.start)
|
||||
txx9_sramc_init(&tx4938_sram_resource);
|
||||
}
|
||||
|
||||
static void __init tx4938_stop_unused_modules(void)
|
||||
{
|
||||
__u64 pcfg, rst = 0, ckd = 0;
|
||||
char buf[128];
|
||||
|
||||
buf[0] = '\0';
|
||||
local_irq_disable();
|
||||
pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
|
||||
switch (txx9_pcode) {
|
||||
case 0x4937:
|
||||
if (!(pcfg & TX4938_PCFG_SEL2)) {
|
||||
rst |= TX4938_CLKCTR_ACLRST;
|
||||
ckd |= TX4938_CLKCTR_ACLCKD;
|
||||
strcat(buf, " ACLC");
|
||||
}
|
||||
break;
|
||||
case 0x4938:
|
||||
if (!(pcfg & TX4938_PCFG_SEL2) ||
|
||||
(pcfg & TX4938_PCFG_ETH0_SEL)) {
|
||||
rst |= TX4938_CLKCTR_ACLRST;
|
||||
ckd |= TX4938_CLKCTR_ACLCKD;
|
||||
strcat(buf, " ACLC");
|
||||
}
|
||||
if ((pcfg &
|
||||
(TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL |
|
||||
TX4938_PCFG_NDF_SEL))
|
||||
!= TX4938_PCFG_NDF_SEL) {
|
||||
rst |= TX4938_CLKCTR_NDFRST;
|
||||
ckd |= TX4938_CLKCTR_NDFCKD;
|
||||
strcat(buf, " NDFMC");
|
||||
}
|
||||
if (!(pcfg & TX4938_PCFG_SPI_SEL)) {
|
||||
rst |= TX4938_CLKCTR_SPIRST;
|
||||
ckd |= TX4938_CLKCTR_SPICKD;
|
||||
strcat(buf, " SPI");
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (rst | ckd) {
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr, rst);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr, ckd);
|
||||
}
|
||||
local_irq_enable();
|
||||
if (buf[0])
|
||||
pr_info("%s: stop%s\n", txx9_pcode_str, buf);
|
||||
}
|
||||
|
||||
static int __init tx4938_late_init(void)
|
||||
{
|
||||
if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938)
|
||||
return -ENODEV;
|
||||
tx4938_stop_unused_modules();
|
||||
return 0;
|
||||
}
|
||||
late_initcall(tx4938_late_init);
|
||||
584
arch/mips/txx9/generic/setup_tx4939.c
Normal file
584
arch/mips/txx9/generic/setup_tx4939.c
Normal file
|
|
@ -0,0 +1,584 @@
|
|||
/*
|
||||
* TX4939 setup routines
|
||||
* Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
|
||||
* and RBTX49xx patch from CELF patch archive.
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc.
|
||||
* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/txx9irq.h>
|
||||
#include <asm/txx9tmr.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/ndfmc.h>
|
||||
#include <asm/txx9/dmac.h>
|
||||
#include <asm/txx9/tx4939.h>
|
||||
|
||||
static void __init tx4939_wdr_init(void)
|
||||
{
|
||||
/* report watchdog reset status */
|
||||
if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
|
||||
pr_warning("Watchdog reset detected at 0x%lx\n",
|
||||
read_c0_errorepc());
|
||||
/* clear WatchDogReset (W1C) */
|
||||
tx4939_ccfg_set(TX4939_CCFG_WDRST);
|
||||
/* do reset on watchdog */
|
||||
tx4939_ccfg_set(TX4939_CCFG_WR);
|
||||
}
|
||||
|
||||
void __init tx4939_wdt_init(void)
|
||||
{
|
||||
txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
|
||||
}
|
||||
|
||||
static void tx4939_machine_restart(char *command)
|
||||
{
|
||||
local_irq_disable();
|
||||
pr_emerg("Rebooting (with %s watchdog reset)...\n",
|
||||
(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
|
||||
"external" : "internal");
|
||||
/* clear watchdog status */
|
||||
tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
|
||||
txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
|
||||
while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
|
||||
;
|
||||
mdelay(10);
|
||||
if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
|
||||
pr_emerg("Rebooting (with internal watchdog reset)...\n");
|
||||
/* External WDRST failed. Do internal watchdog reset */
|
||||
tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
|
||||
}
|
||||
/* fallback */
|
||||
(*_machine_halt)();
|
||||
}
|
||||
|
||||
void show_registers(struct pt_regs *regs);
|
||||
static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
|
||||
{
|
||||
int data = regs->cp0_cause & 4;
|
||||
console_verbose();
|
||||
pr_err("%cBE exception at %#lx\n",
|
||||
data ? 'D' : 'I', regs->cp0_epc);
|
||||
pr_err("ccfg:%llx, toea:%llx\n",
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
|
||||
#ifdef CONFIG_PCI
|
||||
tx4927_report_pcic_status();
|
||||
#endif
|
||||
show_registers(regs);
|
||||
panic("BusError!");
|
||||
}
|
||||
static void __init tx4939_be_init(void)
|
||||
{
|
||||
board_be_handler = tx4939_be_handler;
|
||||
}
|
||||
|
||||
static struct resource tx4939_sdram_resource[4];
|
||||
static struct resource tx4939_sram_resource;
|
||||
#define TX4939_SRAM_SIZE 0x800
|
||||
|
||||
void __init tx4939_add_memory_regions(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long start, size;
|
||||
u64 win;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
|
||||
continue;
|
||||
win = ____raw_readq(&tx4939_ddrcptr->win[i]);
|
||||
start = (unsigned long)(win >> 48);
|
||||
size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
|
||||
add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
|
||||
}
|
||||
}
|
||||
|
||||
void __init tx4939_setup(void)
|
||||
{
|
||||
int i;
|
||||
__u32 divmode;
|
||||
__u64 pcfg;
|
||||
unsigned int cpuclk = 0;
|
||||
|
||||
txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
|
||||
TX4939_REG_SIZE);
|
||||
set_c0_config(TX49_CONF_CWFON);
|
||||
|
||||
/* SDRAMC,EBUSC are configured by PROM */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (!(TX4939_EBUSC_CR(i) & 0x8))
|
||||
continue; /* disabled */
|
||||
txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
|
||||
txx9_ce_res[i].end =
|
||||
txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
|
||||
request_resource(&iomem_resource, &txx9_ce_res[i]);
|
||||
}
|
||||
|
||||
/* clocks */
|
||||
if (txx9_master_clock) {
|
||||
/* calculate cpu_clock from master_clock */
|
||||
divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
|
||||
TX4939_CCFG_MULCLK_MASK;
|
||||
cpuclk = txx9_master_clock * 20 / 2;
|
||||
switch (divmode) {
|
||||
case TX4939_CCFG_MULCLK_8:
|
||||
cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
|
||||
case TX4939_CCFG_MULCLK_9:
|
||||
cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
|
||||
case TX4939_CCFG_MULCLK_10:
|
||||
cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
|
||||
case TX4939_CCFG_MULCLK_11:
|
||||
cpuclk = cpuclk / 6 * 11; break;
|
||||
case TX4939_CCFG_MULCLK_12:
|
||||
cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
|
||||
case TX4939_CCFG_MULCLK_13:
|
||||
cpuclk = cpuclk / 6 * 13; break;
|
||||
case TX4939_CCFG_MULCLK_14:
|
||||
cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
|
||||
case TX4939_CCFG_MULCLK_15:
|
||||
cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
|
||||
}
|
||||
txx9_cpu_clock = cpuclk;
|
||||
} else {
|
||||
if (txx9_cpu_clock == 0)
|
||||
txx9_cpu_clock = 400000000; /* 400MHz */
|
||||
/* calculate master_clock from cpu_clock */
|
||||
cpuclk = txx9_cpu_clock;
|
||||
divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
|
||||
TX4939_CCFG_MULCLK_MASK;
|
||||
switch (divmode) {
|
||||
case TX4939_CCFG_MULCLK_8:
|
||||
txx9_master_clock = cpuclk * 6 / 8; break;
|
||||
case TX4939_CCFG_MULCLK_9:
|
||||
txx9_master_clock = cpuclk * 6 / 9; break;
|
||||
case TX4939_CCFG_MULCLK_10:
|
||||
txx9_master_clock = cpuclk * 6 / 10; break;
|
||||
case TX4939_CCFG_MULCLK_11:
|
||||
txx9_master_clock = cpuclk * 6 / 11; break;
|
||||
case TX4939_CCFG_MULCLK_12:
|
||||
txx9_master_clock = cpuclk * 6 / 12; break;
|
||||
case TX4939_CCFG_MULCLK_13:
|
||||
txx9_master_clock = cpuclk * 6 / 13; break;
|
||||
case TX4939_CCFG_MULCLK_14:
|
||||
txx9_master_clock = cpuclk * 6 / 14; break;
|
||||
case TX4939_CCFG_MULCLK_15:
|
||||
txx9_master_clock = cpuclk * 6 / 15; break;
|
||||
}
|
||||
txx9_master_clock /= 10; /* * 2 / 20 */
|
||||
}
|
||||
/* calculate gbus_clock from cpu_clock */
|
||||
divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
|
||||
TX4939_CCFG_YDIVMODE_MASK;
|
||||
txx9_gbus_clock = txx9_cpu_clock;
|
||||
switch (divmode) {
|
||||
case TX4939_CCFG_YDIVMODE_2:
|
||||
txx9_gbus_clock /= 2; break;
|
||||
case TX4939_CCFG_YDIVMODE_3:
|
||||
txx9_gbus_clock /= 3; break;
|
||||
case TX4939_CCFG_YDIVMODE_5:
|
||||
txx9_gbus_clock /= 5; break;
|
||||
case TX4939_CCFG_YDIVMODE_6:
|
||||
txx9_gbus_clock /= 6; break;
|
||||
}
|
||||
/* change default value to udelay/mdelay take reasonable time */
|
||||
loops_per_jiffy = txx9_cpu_clock / HZ / 2;
|
||||
|
||||
/* CCFG */
|
||||
tx4939_wdr_init();
|
||||
/* clear BusErrorOnWrite flag (W1C) */
|
||||
tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
|
||||
/* enable Timeout BusError */
|
||||
if (txx9_ccfg_toeon)
|
||||
tx4939_ccfg_set(TX4939_CCFG_TOE);
|
||||
|
||||
/* DMA selection */
|
||||
txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
|
||||
|
||||
/* Use external clock for external arbiter */
|
||||
if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
|
||||
txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
|
||||
|
||||
pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
|
||||
txx9_pcode_str,
|
||||
(cpuclk + 500000) / 1000000,
|
||||
(txx9_master_clock + 500000) / 1000000,
|
||||
(txx9_gbus_clock + 500000) / 1000000,
|
||||
(__u32)____raw_readq(&tx4939_ccfgptr->crir),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
|
||||
|
||||
pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
|
||||
(__u32)____raw_readq(&tx4939_ddrcptr->winen));
|
||||
for (i = 0; i < 4; i++) {
|
||||
__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
|
||||
if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
|
||||
continue; /* disabled */
|
||||
printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
|
||||
tx4939_sdram_resource[i].name = "DDR SDRAM";
|
||||
tx4939_sdram_resource[i].start =
|
||||
(unsigned long)(win >> 48) << 20;
|
||||
tx4939_sdram_resource[i].end =
|
||||
((((unsigned long)(win >> 32) & 0xffff) + 1) <<
|
||||
20) - 1;
|
||||
tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
|
||||
}
|
||||
printk(KERN_CONT "\n");
|
||||
|
||||
/* SRAM */
|
||||
if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
|
||||
unsigned int size = TX4939_SRAM_SIZE;
|
||||
tx4939_sram_resource.name = "SRAM";
|
||||
tx4939_sram_resource.start =
|
||||
(____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
|
||||
& ~(size - 1);
|
||||
tx4939_sram_resource.end =
|
||||
tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
|
||||
tx4939_sram_resource.flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4939_sram_resource);
|
||||
}
|
||||
|
||||
/* TMR */
|
||||
/* disable all timers */
|
||||
for (i = 0; i < TX4939_NR_TMR; i++)
|
||||
txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
|
||||
|
||||
/* set PCIC1 reset (required to prevent hangup on BIST) */
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
|
||||
pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
|
||||
mdelay(1); /* at least 128 cpu clock */
|
||||
/* clear PCIC1 reset */
|
||||
txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
|
||||
} else {
|
||||
pr_info("%s: stop PCIC1\n", txx9_pcode_str);
|
||||
/* stop PCIC1 */
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ET0MODE)) {
|
||||
pr_info("%s: stop ETH0\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ET1MODE)) {
|
||||
pr_info("%s: stop ETH1\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
|
||||
}
|
||||
|
||||
_machine_restart = tx4939_machine_restart;
|
||||
board_be_init = tx4939_be_init;
|
||||
}
|
||||
|
||||
void __init tx4939_time_init(unsigned int tmrnr)
|
||||
{
|
||||
if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
|
||||
txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
|
||||
TXX9_IMCLK);
|
||||
}
|
||||
|
||||
void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
|
||||
{
|
||||
int i;
|
||||
unsigned int ch_mask = 0;
|
||||
__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
|
||||
cts_mask |= ~1; /* only SIO0 have RTS/CTS */
|
||||
if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
|
||||
cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
|
||||
if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
|
||||
ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
|
||||
if (pcfg & TX4939_PCFG_SIO3MODE)
|
||||
ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if ((1 << i) & ch_mask)
|
||||
continue;
|
||||
txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4939_IR_SIO(i),
|
||||
i, sclk, (1 << i) & cts_mask);
|
||||
}
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_TC35815)
|
||||
static u32 tx4939_get_eth_speed(struct net_device *dev)
|
||||
{
|
||||
struct ethtool_cmd cmd;
|
||||
if (__ethtool_get_settings(dev, &cmd))
|
||||
return 100; /* default 100Mbps */
|
||||
|
||||
return ethtool_cmd_speed(&cmd);
|
||||
}
|
||||
|
||||
static int tx4939_netdev_event(struct notifier_block *this,
|
||||
unsigned long event,
|
||||
void *ptr)
|
||||
{
|
||||
struct net_device *dev = netdev_notifier_info_to_dev(ptr);
|
||||
|
||||
if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
|
||||
__u64 bit = 0;
|
||||
if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
|
||||
bit = TX4939_PCFG_SPEED0;
|
||||
else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
|
||||
bit = TX4939_PCFG_SPEED1;
|
||||
if (bit) {
|
||||
if (tx4939_get_eth_speed(dev) == 100)
|
||||
txx9_set64(&tx4939_ccfgptr->pcfg, bit);
|
||||
else
|
||||
txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
|
||||
}
|
||||
}
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block tx4939_netdev_notifier = {
|
||||
.notifier_call = tx4939_netdev_event,
|
||||
.priority = 1,
|
||||
};
|
||||
|
||||
void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
|
||||
{
|
||||
u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
|
||||
if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
|
||||
txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
|
||||
if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
|
||||
txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
|
||||
register_netdevice_notifier(&tx4939_netdev_notifier);
|
||||
}
|
||||
#else
|
||||
void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
void __init tx4939_mtd_init(int ch)
|
||||
{
|
||||
struct physmap_flash_data pdata = {
|
||||
.width = TX4939_EBUSC_WIDTH(ch) / 8,
|
||||
};
|
||||
unsigned long start = txx9_ce_res[ch].start;
|
||||
unsigned long size = txx9_ce_res[ch].end - start + 1;
|
||||
|
||||
if (!(TX4939_EBUSC_CR(ch) & 0x8))
|
||||
return; /* disabled */
|
||||
txx9_physmap_flash_init(ch, start, size, &pdata);
|
||||
}
|
||||
|
||||
#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
|
||||
void __init tx4939_ata_init(void)
|
||||
{
|
||||
static struct resource ata0_res[] = {
|
||||
{
|
||||
.start = TX4939_ATA_REG_PHYS(0),
|
||||
.end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
static struct resource ata1_res[] = {
|
||||
{
|
||||
.start = TX4939_ATA_REG_PHYS(1),
|
||||
.end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
static struct platform_device ata0_dev = {
|
||||
.name = "tx4939ide",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(ata0_res),
|
||||
.resource = ata0_res,
|
||||
};
|
||||
static struct platform_device ata1_dev = {
|
||||
.name = "tx4939ide",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(ata1_res),
|
||||
.resource = ata1_res,
|
||||
};
|
||||
__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
|
||||
if (pcfg & TX4939_PCFG_ATA0MODE)
|
||||
platform_device_register(&ata0_dev);
|
||||
if ((pcfg & (TX4939_PCFG_ATA1MODE |
|
||||
TX4939_PCFG_ET1MODE |
|
||||
TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
|
||||
platform_device_register(&ata1_dev);
|
||||
}
|
||||
|
||||
void __init tx4939_rtc_init(void)
|
||||
{
|
||||
static struct resource res[] = {
|
||||
{
|
||||
.start = TX4939_RTC_REG & 0xfffffffffULL,
|
||||
.end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = TXX9_IRQ_BASE + TX4939_IR_RTC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
static struct platform_device rtc_dev = {
|
||||
.name = "tx4939rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(res),
|
||||
.resource = res,
|
||||
};
|
||||
|
||||
platform_device_register(&rtc_dev);
|
||||
}
|
||||
|
||||
void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
|
||||
unsigned char ch_mask, unsigned char wide_mask)
|
||||
{
|
||||
struct txx9ndfmc_platform_data plat_data = {
|
||||
.shift = 1,
|
||||
.gbus_clock = txx9_gbus_clock,
|
||||
.hold = hold,
|
||||
.spw = spw,
|
||||
.flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
|
||||
NDFMC_PLAT_FLAG_DUMMYWRITE,
|
||||
.ch_mask = ch_mask,
|
||||
.wide_mask = wide_mask,
|
||||
};
|
||||
txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
|
||||
}
|
||||
|
||||
void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
|
||||
{
|
||||
struct txx9dmac_platform_data plat_data = {
|
||||
.have_64bit_regs = true,
|
||||
};
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
|
||||
txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
|
||||
&plat_data);
|
||||
}
|
||||
}
|
||||
|
||||
void __init tx4939_aclc_init(void)
|
||||
{
|
||||
u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
|
||||
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
|
||||
txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
|
||||
TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
|
||||
}
|
||||
|
||||
void __init tx4939_sramc_init(void)
|
||||
{
|
||||
if (tx4939_sram_resource.start)
|
||||
txx9_sramc_init(&tx4939_sram_resource);
|
||||
}
|
||||
|
||||
void __init tx4939_rng_init(void)
|
||||
{
|
||||
static struct resource res = {
|
||||
.start = TX4939_RNG_REG & 0xfffffffffULL,
|
||||
.end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
static struct platform_device pdev = {
|
||||
.name = "tx4939-rng",
|
||||
.id = -1,
|
||||
.num_resources = 1,
|
||||
.resource = &res,
|
||||
};
|
||||
|
||||
platform_device_register(&pdev);
|
||||
}
|
||||
|
||||
static void __init tx4939_stop_unused_modules(void)
|
||||
{
|
||||
__u64 pcfg, rst = 0, ckd = 0;
|
||||
char buf[128];
|
||||
|
||||
buf[0] = '\0';
|
||||
local_irq_disable();
|
||||
pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
|
||||
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
||||
TX4939_PCFG_I2SMODE_ACLC) {
|
||||
rst |= TX4939_CLKCTR_ACLRST;
|
||||
ckd |= TX4939_CLKCTR_ACLCKD;
|
||||
strcat(buf, " ACLC");
|
||||
}
|
||||
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
||||
TX4939_PCFG_I2SMODE_I2S &&
|
||||
(pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
||||
TX4939_PCFG_I2SMODE_I2S_ALT) {
|
||||
rst |= TX4939_CLKCTR_I2SRST;
|
||||
ckd |= TX4939_CLKCTR_I2SCKD;
|
||||
strcat(buf, " I2S");
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
|
||||
rst |= TX4939_CLKCTR_ATA0RST;
|
||||
ckd |= TX4939_CLKCTR_ATA0CKD;
|
||||
strcat(buf, " ATA0");
|
||||
}
|
||||
if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
|
||||
rst |= TX4939_CLKCTR_ATA1RST;
|
||||
ckd |= TX4939_CLKCTR_ATA1CKD;
|
||||
strcat(buf, " ATA1");
|
||||
}
|
||||
if (pcfg & TX4939_PCFG_SPIMODE) {
|
||||
rst |= TX4939_CLKCTR_SPIRST;
|
||||
ckd |= TX4939_CLKCTR_SPICKD;
|
||||
strcat(buf, " SPI");
|
||||
}
|
||||
if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
|
||||
rst |= TX4939_CLKCTR_VPCRST;
|
||||
ckd |= TX4939_CLKCTR_VPCCKD;
|
||||
strcat(buf, " VPC");
|
||||
}
|
||||
if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
|
||||
rst |= TX4939_CLKCTR_SIO2RST;
|
||||
ckd |= TX4939_CLKCTR_SIO2CKD;
|
||||
strcat(buf, " SIO2");
|
||||
}
|
||||
if (pcfg & TX4939_PCFG_SIO3MODE) {
|
||||
rst |= TX4939_CLKCTR_SIO3RST;
|
||||
ckd |= TX4939_CLKCTR_SIO3CKD;
|
||||
strcat(buf, " SIO3");
|
||||
}
|
||||
if (rst | ckd) {
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, rst);
|
||||
txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
|
||||
}
|
||||
local_irq_enable();
|
||||
if (buf[0])
|
||||
pr_info("%s: stop%s\n", txx9_pcode_str, buf);
|
||||
}
|
||||
|
||||
static int __init tx4939_late_init(void)
|
||||
{
|
||||
if (txx9_pcode != 0x4939)
|
||||
return -ENODEV;
|
||||
tx4939_stop_unused_modules();
|
||||
return 0;
|
||||
}
|
||||
late_initcall(tx4939_late_init);
|
||||
172
arch/mips/txx9/generic/smsc_fdc37m81x.c
Normal file
172
arch/mips/txx9/generic/smsc_fdc37m81x.c
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* Interface for smsc fdc48m81x Super IO chip
|
||||
*
|
||||
* Author: MontaVista Software, Inc. source@mvista.com
|
||||
*
|
||||
* 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Copyright 2004 (c) MontaVista Software, Inc.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/txx9/smsc_fdc37m81x.h>
|
||||
|
||||
/* Common Registers */
|
||||
#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
|
||||
#define SMSC_FDC37M81X_CONFIG_DATA 0x01
|
||||
#define SMSC_FDC37M81X_CONF 0x02
|
||||
#define SMSC_FDC37M81X_INDEX 0x03
|
||||
#define SMSC_FDC37M81X_DNUM 0x07
|
||||
#define SMSC_FDC37M81X_DID 0x20
|
||||
#define SMSC_FDC37M81X_DREV 0x21
|
||||
#define SMSC_FDC37M81X_PCNT 0x22
|
||||
#define SMSC_FDC37M81X_PMGT 0x23
|
||||
#define SMSC_FDC37M81X_OSC 0x24
|
||||
#define SMSC_FDC37M81X_CONFPA0 0x26
|
||||
#define SMSC_FDC37M81X_CONFPA1 0x27
|
||||
#define SMSC_FDC37M81X_TEST4 0x2B
|
||||
#define SMSC_FDC37M81X_TEST5 0x2C
|
||||
#define SMSC_FDC37M81X_TEST1 0x2D
|
||||
#define SMSC_FDC37M81X_TEST2 0x2E
|
||||
#define SMSC_FDC37M81X_TEST3 0x2F
|
||||
|
||||
/* Logical device numbers */
|
||||
#define SMSC_FDC37M81X_FDD 0x00
|
||||
#define SMSC_FDC37M81X_SERIAL1 0x04
|
||||
#define SMSC_FDC37M81X_SERIAL2 0x05
|
||||
#define SMSC_FDC37M81X_KBD 0x07
|
||||
|
||||
/* Logical device Config Registers */
|
||||
#define SMSC_FDC37M81X_ACTIVE 0x30
|
||||
#define SMSC_FDC37M81X_BASEADDR0 0x60
|
||||
#define SMSC_FDC37M81X_BASEADDR1 0x61
|
||||
#define SMSC_FDC37M81X_INT 0x70
|
||||
#define SMSC_FDC37M81X_INT2 0x72
|
||||
#define SMSC_FDC37M81X_MODE 0xF0
|
||||
|
||||
/* Chip Config Values */
|
||||
#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
|
||||
#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
|
||||
#define SMSC_FDC37M81X_CHIP_ID 0x4d
|
||||
|
||||
static unsigned long g_smsc_fdc37m81x_base;
|
||||
|
||||
static inline unsigned char smsc_fdc37m81x_rd(unsigned char index)
|
||||
{
|
||||
outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
|
||||
|
||||
return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA);
|
||||
}
|
||||
|
||||
static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data)
|
||||
{
|
||||
outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
|
||||
outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA);
|
||||
}
|
||||
|
||||
void smsc_fdc37m81x_config_beg(void)
|
||||
{
|
||||
if (g_smsc_fdc37m81x_base) {
|
||||
outb(SMSC_FDC37M81X_CONFIG_ENTER,
|
||||
g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
|
||||
}
|
||||
}
|
||||
|
||||
void smsc_fdc37m81x_config_end(void)
|
||||
{
|
||||
if (g_smsc_fdc37m81x_base)
|
||||
outb(SMSC_FDC37M81X_CONFIG_EXIT,
|
||||
g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
|
||||
}
|
||||
|
||||
u8 smsc_fdc37m81x_config_get(u8 reg)
|
||||
{
|
||||
u8 val = 0;
|
||||
|
||||
if (g_smsc_fdc37m81x_base)
|
||||
val = smsc_fdc37m81x_rd(reg);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
void smsc_fdc37m81x_config_set(u8 reg, u8 val)
|
||||
{
|
||||
if (g_smsc_fdc37m81x_base)
|
||||
smsc_dc37m81x_wr(reg, val);
|
||||
}
|
||||
|
||||
unsigned long __init smsc_fdc37m81x_init(unsigned long port)
|
||||
{
|
||||
const int field = sizeof(unsigned long) * 2;
|
||||
u8 chip_id;
|
||||
|
||||
if (g_smsc_fdc37m81x_base)
|
||||
printk(KERN_WARNING "%s: stepping on old base=0x%0*lx\n",
|
||||
__func__,
|
||||
field, g_smsc_fdc37m81x_base);
|
||||
|
||||
g_smsc_fdc37m81x_base = port;
|
||||
|
||||
smsc_fdc37m81x_config_beg();
|
||||
|
||||
chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID);
|
||||
if (chip_id == SMSC_FDC37M81X_CHIP_ID)
|
||||
smsc_fdc37m81x_config_end();
|
||||
else {
|
||||
printk(KERN_WARNING "%s: unknown chip id 0x%02x\n", __func__,
|
||||
chip_id);
|
||||
g_smsc_fdc37m81x_base = 0;
|
||||
}
|
||||
|
||||
return g_smsc_fdc37m81x_base;
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg)
|
||||
{
|
||||
printk(KERN_INFO "%s: dev=0x%02x reg=0x%02x val=0x%02x\n",
|
||||
key, dev, reg,
|
||||
smsc_fdc37m81x_rd(reg));
|
||||
}
|
||||
|
||||
void smsc_fdc37m81x_config_dump(void)
|
||||
{
|
||||
u8 orig;
|
||||
const char *fname = __func__;
|
||||
|
||||
smsc_fdc37m81x_config_beg();
|
||||
|
||||
orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM);
|
||||
|
||||
printk(KERN_INFO "%s: common\n", fname);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
SMSC_FDC37M81X_DNUM);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
SMSC_FDC37M81X_DID);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
SMSC_FDC37M81X_DREV);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
SMSC_FDC37M81X_PCNT);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
SMSC_FDC37M81X_PMGT);
|
||||
|
||||
printk(KERN_INFO "%s: keyboard\n", fname);
|
||||
smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
|
||||
SMSC_FDC37M81X_ACTIVE);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
|
||||
SMSC_FDC37M81X_INT);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
|
||||
SMSC_FDC37M81X_INT2);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
|
||||
SMSC_FDC37M81X_LDCR_F0);
|
||||
|
||||
smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig);
|
||||
|
||||
smsc_fdc37m81x_config_end();
|
||||
}
|
||||
#endif
|
||||
105
arch/mips/txx9/generic/spi_eeprom.c
Normal file
105
arch/mips/txx9/generic/spi_eeprom.c
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* spi_eeprom.c
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/eeprom.h>
|
||||
#include <asm/txx9/spi.h>
|
||||
|
||||
#define AT250X0_PAGE_SIZE 8
|
||||
|
||||
/* register board information for at25 driver */
|
||||
int __init spi_eeprom_register(int busid, int chipid, int size)
|
||||
{
|
||||
struct spi_board_info info = {
|
||||
.modalias = "at25",
|
||||
.max_speed_hz = 1500000, /* 1.5Mbps */
|
||||
.bus_num = busid,
|
||||
.chip_select = chipid,
|
||||
/* Mode 0: High-Active, Sample-Then-Shift */
|
||||
};
|
||||
struct spi_eeprom *eeprom;
|
||||
eeprom = kzalloc(sizeof(*eeprom), GFP_KERNEL);
|
||||
if (!eeprom)
|
||||
return -ENOMEM;
|
||||
strcpy(eeprom->name, "at250x0");
|
||||
eeprom->byte_len = size;
|
||||
eeprom->page_size = AT250X0_PAGE_SIZE;
|
||||
eeprom->flags = EE_ADDR1;
|
||||
info.platform_data = eeprom;
|
||||
return spi_register_board_info(&info, 1);
|
||||
}
|
||||
|
||||
/* simple temporary spi driver to provide early access to seeprom. */
|
||||
|
||||
static struct read_param {
|
||||
int busid;
|
||||
int chipid;
|
||||
int address;
|
||||
unsigned char *buf;
|
||||
int len;
|
||||
} *read_param;
|
||||
|
||||
static int __init early_seeprom_probe(struct spi_device *spi)
|
||||
{
|
||||
int stat = 0;
|
||||
u8 cmd[2];
|
||||
int len = read_param->len;
|
||||
char *buf = read_param->buf;
|
||||
int address = read_param->address;
|
||||
|
||||
dev_info(&spi->dev, "spiclk %u KHz.\n",
|
||||
(spi->max_speed_hz + 500) / 1000);
|
||||
if (read_param->busid != spi->master->bus_num ||
|
||||
read_param->chipid != spi->chip_select)
|
||||
return -ENODEV;
|
||||
while (len > 0) {
|
||||
/* spi_write_then_read can only work with small chunk */
|
||||
int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE;
|
||||
cmd[0] = 0x03; /* AT25_READ */
|
||||
cmd[1] = address;
|
||||
stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c);
|
||||
buf += c;
|
||||
len -= c;
|
||||
address += c;
|
||||
}
|
||||
return stat;
|
||||
}
|
||||
|
||||
static struct spi_driver early_seeprom_driver __initdata = {
|
||||
.driver = {
|
||||
.name = "at25",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = early_seeprom_probe,
|
||||
};
|
||||
|
||||
int __init spi_eeprom_read(int busid, int chipid, int address,
|
||||
unsigned char *buf, int len)
|
||||
{
|
||||
int ret;
|
||||
struct read_param param = {
|
||||
.busid = busid,
|
||||
.chipid = chipid,
|
||||
.address = address,
|
||||
.buf = buf,
|
||||
.len = len
|
||||
};
|
||||
|
||||
read_param = ¶m;
|
||||
ret = spi_register_driver(&early_seeprom_driver);
|
||||
if (!ret)
|
||||
spi_unregister_driver(&early_seeprom_driver);
|
||||
return ret;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue