mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-03 01:25:36 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
340
arch/mips/txx9/generic/setup_tx4927.c
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340
arch/mips/txx9/generic/setup_tx4927.c
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/*
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* TX4927 setup routines
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* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* 2003-2005 (c) MontaVista Software, Inc.
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/param.h>
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#include <linux/ptrace.h>
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#include <linux/mtd/physmap.h>
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#include <asm/reboot.h>
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#include <asm/traps.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9tmr.h>
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#include <asm/txx9pio.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/dmac.h>
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#include <asm/txx9/tx4927.h>
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static void __init tx4927_wdr_init(void)
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{
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/* report watchdog reset status */
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if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST)
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pr_warning("Watchdog reset detected at 0x%lx\n",
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read_c0_errorepc());
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/* clear WatchDogReset (W1C) */
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tx4927_ccfg_set(TX4927_CCFG_WDRST);
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/* do reset on watchdog */
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tx4927_ccfg_set(TX4927_CCFG_WR);
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}
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void __init tx4927_wdt_init(void)
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{
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txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
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}
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static void tx4927_machine_restart(char *command)
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{
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local_irq_disable();
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pr_emerg("Rebooting (with %s watchdog reset)...\n",
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(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) ?
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"external" : "internal");
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/* clear watchdog status */
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tx4927_ccfg_set(TX4927_CCFG_WDRST); /* W1C */
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txx9_wdt_now(TX4927_TMR_REG(2) & 0xfffffffffULL);
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while (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDRST))
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;
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mdelay(10);
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if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_WDREXEN) {
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pr_emerg("Rebooting (with internal watchdog reset)...\n");
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/* External WDRST failed. Do internal watchdog reset */
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tx4927_ccfg_clear(TX4927_CCFG_WDREXEN);
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}
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/* fallback */
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(*_machine_halt)();
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}
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void show_registers(struct pt_regs *regs);
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static int tx4927_be_handler(struct pt_regs *regs, int is_fixup)
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{
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int data = regs->cp0_cause & 4;
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console_verbose();
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pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
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pr_err("ccfg:%llx, toea:%llx\n",
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(unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
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(unsigned long long)____raw_readq(&tx4927_ccfgptr->toea));
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#ifdef CONFIG_PCI
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tx4927_report_pcic_status();
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#endif
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show_registers(regs);
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panic("BusError!");
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}
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static void __init tx4927_be_init(void)
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{
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board_be_handler = tx4927_be_handler;
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}
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static struct resource tx4927_sdram_resource[4];
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void __init tx4927_setup(void)
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{
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int i;
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__u32 divmode;
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unsigned int cpuclk = 0;
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u64 ccfg;
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txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
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TX4927_REG_SIZE);
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set_c0_config(TX49_CONF_CWFON);
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/* SDRAMC,EBUSC are configured by PROM */
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for (i = 0; i < 8; i++) {
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if (!(TX4927_EBUSC_CR(i) & 0x8))
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continue; /* disabled */
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txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
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txx9_ce_res[i].end =
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txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
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request_resource(&iomem_resource, &txx9_ce_res[i]);
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}
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/* clocks */
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ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
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if (txx9_master_clock) {
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/* calculate gbus_clock and cpu_clock from master_clock */
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divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
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switch (divmode) {
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case TX4927_CCFG_DIVMODE_8:
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case TX4927_CCFG_DIVMODE_10:
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case TX4927_CCFG_DIVMODE_12:
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case TX4927_CCFG_DIVMODE_16:
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txx9_gbus_clock = txx9_master_clock * 4; break;
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default:
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txx9_gbus_clock = txx9_master_clock;
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}
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switch (divmode) {
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case TX4927_CCFG_DIVMODE_2:
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case TX4927_CCFG_DIVMODE_8:
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cpuclk = txx9_gbus_clock * 2; break;
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case TX4927_CCFG_DIVMODE_2_5:
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case TX4927_CCFG_DIVMODE_10:
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cpuclk = txx9_gbus_clock * 5 / 2; break;
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case TX4927_CCFG_DIVMODE_3:
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case TX4927_CCFG_DIVMODE_12:
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cpuclk = txx9_gbus_clock * 3; break;
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case TX4927_CCFG_DIVMODE_4:
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case TX4927_CCFG_DIVMODE_16:
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cpuclk = txx9_gbus_clock * 4; break;
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}
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txx9_cpu_clock = cpuclk;
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} else {
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if (txx9_cpu_clock == 0)
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txx9_cpu_clock = 200000000; /* 200MHz */
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/* calculate gbus_clock and master_clock from cpu_clock */
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cpuclk = txx9_cpu_clock;
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divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
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switch (divmode) {
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case TX4927_CCFG_DIVMODE_2:
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case TX4927_CCFG_DIVMODE_8:
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txx9_gbus_clock = cpuclk / 2; break;
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case TX4927_CCFG_DIVMODE_2_5:
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case TX4927_CCFG_DIVMODE_10:
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txx9_gbus_clock = cpuclk * 2 / 5; break;
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case TX4927_CCFG_DIVMODE_3:
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case TX4927_CCFG_DIVMODE_12:
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txx9_gbus_clock = cpuclk / 3; break;
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case TX4927_CCFG_DIVMODE_4:
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case TX4927_CCFG_DIVMODE_16:
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txx9_gbus_clock = cpuclk / 4; break;
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}
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switch (divmode) {
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case TX4927_CCFG_DIVMODE_8:
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case TX4927_CCFG_DIVMODE_10:
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case TX4927_CCFG_DIVMODE_12:
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case TX4927_CCFG_DIVMODE_16:
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txx9_master_clock = txx9_gbus_clock / 4; break;
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default:
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txx9_master_clock = txx9_gbus_clock;
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}
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}
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/* change default value to udelay/mdelay take reasonable time */
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loops_per_jiffy = txx9_cpu_clock / HZ / 2;
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/* CCFG */
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tx4927_wdr_init();
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/* clear BusErrorOnWrite flag (W1C) */
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tx4927_ccfg_set(TX4927_CCFG_BEOW);
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/* enable Timeout BusError */
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if (txx9_ccfg_toeon)
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tx4927_ccfg_set(TX4927_CCFG_TOE);
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/* DMA selection */
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txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
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/* Use external clock for external arbiter */
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if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
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txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
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printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
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txx9_pcode_str,
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(cpuclk + 500000) / 1000000,
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(txx9_master_clock + 500000) / 1000000,
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(__u32)____raw_readq(&tx4927_ccfgptr->crir),
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(unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
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(unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
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printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
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for (i = 0; i < 4; i++) {
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__u64 cr = TX4927_SDRAMC_CR(i);
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unsigned long base, size;
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if (!((__u32)cr & 0x00000400))
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continue; /* disabled */
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base = (unsigned long)(cr >> 49) << 21;
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size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
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printk(" CR%d:%016llx", i, (unsigned long long)cr);
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tx4927_sdram_resource[i].name = "SDRAM";
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tx4927_sdram_resource[i].start = base;
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tx4927_sdram_resource[i].end = base + size - 1;
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tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
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}
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printk(" TR:%09llx\n",
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(unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
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/* TMR */
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/* disable all timers */
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for (i = 0; i < TX4927_NR_TMR; i++)
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txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
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/* PIO */
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txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
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__raw_writel(0, &tx4927_pioptr->maskcpu);
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__raw_writel(0, &tx4927_pioptr->maskext);
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_machine_restart = tx4927_machine_restart;
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board_be_init = tx4927_be_init;
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}
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void __init tx4927_time_init(unsigned int tmrnr)
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{
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if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
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txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
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TXX9_IMCLK);
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}
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void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask)
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{
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int i;
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for (i = 0; i < 2; i++)
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txx9_sio_init(TX4927_SIO_REG(i) & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4927_IR_SIO(i),
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i, sclk, (1 << i) & cts_mask);
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}
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void __init tx4927_mtd_init(int ch)
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{
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struct physmap_flash_data pdata = {
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.width = TX4927_EBUSC_WIDTH(ch) / 8,
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};
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unsigned long start = txx9_ce_res[ch].start;
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unsigned long size = txx9_ce_res[ch].end - start + 1;
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if (!(TX4927_EBUSC_CR(ch) & 0x8))
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return; /* disabled */
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txx9_physmap_flash_init(ch, start, size, &pdata);
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}
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void __init tx4927_dmac_init(int memcpy_chan)
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{
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struct txx9dmac_platform_data plat_data = {
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.memcpy_chan = memcpy_chan,
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.have_64bit_regs = true,
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};
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txx9_dmac_init(0, TX4927_DMA_REG & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4927_IR_DMA(0), &plat_data);
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}
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void __init tx4927_aclc_init(unsigned int dma_chan_out,
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unsigned int dma_chan_in)
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{
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u64 pcfg = __raw_readq(&tx4927_ccfgptr->pcfg);
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__u64 dmasel_mask = 0, dmasel = 0;
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unsigned long flags;
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if (!(pcfg & TX4927_PCFG_SEL2))
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return;
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/* setup DMASEL (playback:ACLC ch0, capture:ACLC ch1) */
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switch (dma_chan_out) {
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case 0:
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dmasel_mask |= TX4927_PCFG_DMASEL0_MASK;
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dmasel |= TX4927_PCFG_DMASEL0_ACL0;
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break;
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case 2:
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dmasel_mask |= TX4927_PCFG_DMASEL2_MASK;
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dmasel |= TX4927_PCFG_DMASEL2_ACL0;
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break;
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default:
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return;
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}
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switch (dma_chan_in) {
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case 1:
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dmasel_mask |= TX4927_PCFG_DMASEL1_MASK;
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dmasel |= TX4927_PCFG_DMASEL1_ACL1;
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break;
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case 3:
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dmasel_mask |= TX4927_PCFG_DMASEL3_MASK;
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dmasel |= TX4927_PCFG_DMASEL3_ACL1;
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break;
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default:
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return;
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}
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local_irq_save(flags);
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txx9_clear64(&tx4927_ccfgptr->pcfg, dmasel_mask);
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txx9_set64(&tx4927_ccfgptr->pcfg, dmasel);
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local_irq_restore(flags);
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txx9_aclc_init(TX4927_ACLC_REG & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4927_IR_ACLC,
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0, dma_chan_out, dma_chan_in);
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}
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static void __init tx4927_stop_unused_modules(void)
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{
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__u64 pcfg, rst = 0, ckd = 0;
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char buf[128];
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buf[0] = '\0';
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local_irq_disable();
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pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg);
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if (!(pcfg & TX4927_PCFG_SEL2)) {
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rst |= TX4927_CLKCTR_ACLRST;
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ckd |= TX4927_CLKCTR_ACLCKD;
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strcat(buf, " ACLC");
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}
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if (rst | ckd) {
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txx9_set64(&tx4927_ccfgptr->clkctr, rst);
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txx9_set64(&tx4927_ccfgptr->clkctr, ckd);
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}
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local_irq_enable();
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if (buf[0])
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pr_info("%s: stop%s\n", txx9_pcode_str, buf);
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}
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static int __init tx4927_late_init(void)
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{
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if (txx9_pcode != 0x4927)
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return -ENODEV;
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tx4927_stop_unused_modules();
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return 0;
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}
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late_initcall(tx4927_late_init);
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