mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 09:05:37 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
257
arch/mips/vr41xx/common/cmu.c
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257
arch/mips/vr41xx/common/cmu.c
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/*
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* cmu.c, Clock Mask Unit routines for the NEC VR4100 series.
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*
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* Copyright (C) 2001-2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <source@mvista.com>
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* Copuright (C) 2003-2005 Yoichi Yuasa <yuasa@linux-mips.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Changes:
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* MontaVista Software Inc. <source@mvista.com>
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* - New creation, NEC VR4122 and VR4131 are supported.
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* - Added support for NEC VR4111 and VR4121.
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*
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* Yoichi Yuasa <yuasa@linux-mips.org>
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* - Added support for NEC VR4133.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/vr41xx/vr41xx.h>
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#define CMU_TYPE1_BASE 0x0b000060UL
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#define CMU_TYPE1_SIZE 0x4
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#define CMU_TYPE2_BASE 0x0f000060UL
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#define CMU_TYPE2_SIZE 0x4
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#define CMU_TYPE3_BASE 0x0f000060UL
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#define CMU_TYPE3_SIZE 0x8
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#define CMUCLKMSK 0x0
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#define MSKPIU 0x0001
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#define MSKSIU 0x0002
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#define MSKAIU 0x0004
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#define MSKKIU 0x0008
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#define MSKFIR 0x0010
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#define MSKDSIU 0x0820
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#define MSKCSI 0x0040
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#define MSKPCIU 0x0080
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#define MSKSSIU 0x0100
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#define MSKSHSP 0x0200
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#define MSKFFIR 0x0400
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#define MSKSCSI 0x1000
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#define MSKPPCIU 0x2000
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#define CMUCLKMSK2 0x4
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#define MSKCEU 0x0001
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#define MSKMAC0 0x0002
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#define MSKMAC1 0x0004
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static void __iomem *cmu_base;
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static uint16_t cmuclkmsk, cmuclkmsk2;
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static DEFINE_SPINLOCK(cmu_lock);
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#define cmu_read(offset) readw(cmu_base + (offset))
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#define cmu_write(offset, value) writew((value), cmu_base + (offset))
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void vr41xx_supply_clock(vr41xx_clock_t clock)
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{
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spin_lock_irq(&cmu_lock);
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switch (clock) {
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case PIU_CLOCK:
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cmuclkmsk |= MSKPIU;
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break;
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case SIU_CLOCK:
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cmuclkmsk |= MSKSIU | MSKSSIU;
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break;
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case AIU_CLOCK:
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cmuclkmsk |= MSKAIU;
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break;
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case KIU_CLOCK:
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cmuclkmsk |= MSKKIU;
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break;
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case FIR_CLOCK:
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cmuclkmsk |= MSKFIR | MSKFFIR;
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break;
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case DSIU_CLOCK:
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121)
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cmuclkmsk |= MSKDSIU;
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else
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cmuclkmsk |= MSKSIU | MSKDSIU;
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break;
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case CSI_CLOCK:
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cmuclkmsk |= MSKCSI | MSKSCSI;
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break;
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case PCIU_CLOCK:
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cmuclkmsk |= MSKPCIU;
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break;
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case HSP_CLOCK:
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cmuclkmsk |= MSKSHSP;
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break;
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case PCI_CLOCK:
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cmuclkmsk |= MSKPPCIU;
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break;
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case CEU_CLOCK:
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cmuclkmsk2 |= MSKCEU;
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break;
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case ETHER0_CLOCK:
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cmuclkmsk2 |= MSKMAC0;
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break;
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case ETHER1_CLOCK:
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cmuclkmsk2 |= MSKMAC1;
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break;
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default:
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break;
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}
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if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
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clock == ETHER1_CLOCK)
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cmu_write(CMUCLKMSK2, cmuclkmsk2);
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else
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cmu_write(CMUCLKMSK, cmuclkmsk);
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spin_unlock_irq(&cmu_lock);
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}
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EXPORT_SYMBOL_GPL(vr41xx_supply_clock);
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void vr41xx_mask_clock(vr41xx_clock_t clock)
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{
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spin_lock_irq(&cmu_lock);
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switch (clock) {
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case PIU_CLOCK:
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cmuclkmsk &= ~MSKPIU;
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break;
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case SIU_CLOCK:
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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cmuclkmsk &= ~(MSKSIU | MSKSSIU);
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} else {
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if (cmuclkmsk & MSKDSIU)
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cmuclkmsk &= ~MSKSSIU;
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else
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cmuclkmsk &= ~(MSKSIU | MSKSSIU);
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}
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break;
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case AIU_CLOCK:
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cmuclkmsk &= ~MSKAIU;
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break;
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case KIU_CLOCK:
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cmuclkmsk &= ~MSKKIU;
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break;
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case FIR_CLOCK:
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cmuclkmsk &= ~(MSKFIR | MSKFFIR);
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break;
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case DSIU_CLOCK:
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if (current_cpu_type() == CPU_VR4111 ||
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current_cpu_type() == CPU_VR4121) {
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cmuclkmsk &= ~MSKDSIU;
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} else {
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if (cmuclkmsk & MSKSSIU)
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cmuclkmsk &= ~MSKDSIU;
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else
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cmuclkmsk &= ~(MSKSIU | MSKDSIU);
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}
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break;
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case CSI_CLOCK:
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cmuclkmsk &= ~(MSKCSI | MSKSCSI);
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break;
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case PCIU_CLOCK:
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cmuclkmsk &= ~MSKPCIU;
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break;
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case HSP_CLOCK:
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cmuclkmsk &= ~MSKSHSP;
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break;
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case PCI_CLOCK:
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cmuclkmsk &= ~MSKPPCIU;
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break;
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case CEU_CLOCK:
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cmuclkmsk2 &= ~MSKCEU;
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break;
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case ETHER0_CLOCK:
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cmuclkmsk2 &= ~MSKMAC0;
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break;
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case ETHER1_CLOCK:
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cmuclkmsk2 &= ~MSKMAC1;
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break;
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default:
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break;
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}
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if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
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clock == ETHER1_CLOCK)
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cmu_write(CMUCLKMSK2, cmuclkmsk2);
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else
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cmu_write(CMUCLKMSK, cmuclkmsk);
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spin_unlock_irq(&cmu_lock);
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}
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EXPORT_SYMBOL_GPL(vr41xx_mask_clock);
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static int __init vr41xx_cmu_init(void)
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{
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unsigned long start, size;
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switch (current_cpu_type()) {
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case CPU_VR4111:
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case CPU_VR4121:
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start = CMU_TYPE1_BASE;
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size = CMU_TYPE1_SIZE;
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break;
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case CPU_VR4122:
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case CPU_VR4131:
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start = CMU_TYPE2_BASE;
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size = CMU_TYPE2_SIZE;
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break;
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case CPU_VR4133:
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start = CMU_TYPE3_BASE;
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size = CMU_TYPE3_SIZE;
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break;
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default:
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panic("Unexpected CPU of NEC VR4100 series");
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break;
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}
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if (request_mem_region(start, size, "CMU") == NULL)
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return -EBUSY;
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cmu_base = ioremap(start, size);
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if (cmu_base == NULL) {
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release_mem_region(start, size);
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return -EBUSY;
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}
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cmuclkmsk = cmu_read(CMUCLKMSK);
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if (current_cpu_type() == CPU_VR4133)
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cmuclkmsk2 = cmu_read(CMUCLKMSK2);
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spin_lock_init(&cmu_lock);
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return 0;
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}
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core_initcall(vr41xx_cmu_init);
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