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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
199
arch/mn10300/include/asm/atomic.h
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199
arch/mn10300/include/asm/atomic.h
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/* MN10300 Atomic counter operations
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <asm/irqflags.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#ifndef CONFIG_SMP
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#include <asm-generic/atomic.h>
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#else
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*/
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#define ATOMIC_INIT(i) { (i) }
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#ifdef __KERNEL__
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/**
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* atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v. Note that the guaranteed
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*/
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#define atomic_read(v) (ACCESS_ONCE((v)->counter))
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/**
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* atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i. Note that the guaranteed
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*/
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#define atomic_set(v, i) (((v)->counter) = (i))
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#define ATOMIC_OP(op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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int retval, status; \
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\
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asm volatile( \
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"1: mov %4,(_AAR,%3) \n" \
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" mov (_ADR,%3),%1 \n" \
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" " #op " %5,%1 \n" \
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" mov %1,(_ADR,%3) \n" \
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" mov (_ADR,%3),%0 \n" /* flush */ \
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" mov (_ASR,%3),%0 \n" \
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" or %0,%0 \n" \
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" bne 1b \n" \
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: "=&r"(status), "=&r"(retval), "=m"(v->counter) \
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
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: "memory", "cc"); \
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}
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#define ATOMIC_OP_RETURN(op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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int retval, status; \
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\
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asm volatile( \
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"1: mov %4,(_AAR,%3) \n" \
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" mov (_ADR,%3),%1 \n" \
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" " #op " %5,%1 \n" \
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" mov %1,(_ADR,%3) \n" \
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" mov (_ADR,%3),%0 \n" /* flush */ \
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" mov (_ASR,%3),%0 \n" \
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" or %0,%0 \n" \
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" bne 1b \n" \
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: "=&r"(status), "=&r"(retval), "=m"(v->counter) \
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
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: "memory", "cc"); \
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return retval; \
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}
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op)
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ATOMIC_OPS(add)
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ATOMIC_OPS(sub)
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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static inline int atomic_add_negative(int i, atomic_t *v)
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{
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return atomic_add_return(i, v) < 0;
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}
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static inline void atomic_inc(atomic_t *v)
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{
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atomic_add_return(1, v);
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}
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static inline void atomic_dec(atomic_t *v)
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{
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atomic_sub_return(1, v);
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}
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
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#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
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#define __atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
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c = old; \
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c; \
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})
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#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
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#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
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/**
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* atomic_clear_mask - Atomically clear bits in memory
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* @mask: Mask of the bits to be cleared
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* @v: pointer to word in memory
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*
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* Atomically clears the bits set in mask from the memory word specified.
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*/
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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{
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#ifdef CONFIG_SMP
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int status;
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asm volatile(
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"1: mov %3,(_AAR,%2) \n"
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" mov (_ADR,%2),%0 \n"
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" and %4,%0 \n"
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" mov %0,(_ADR,%2) \n"
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" mov (_ADR,%2),%0 \n" /* flush */
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" mov (_ASR,%2),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=m"(*addr)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(addr), "r"(~mask)
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: "memory", "cc");
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#else
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unsigned long flags;
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mask = ~mask;
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flags = arch_local_cli_save();
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*addr &= mask;
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arch_local_irq_restore(flags);
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#endif
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}
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/**
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* atomic_set_mask - Atomically set bits in memory
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* @mask: Mask of the bits to be set
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* @v: pointer to word in memory
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*
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* Atomically sets the bits set in mask from the memory word specified.
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*/
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static inline void atomic_set_mask(unsigned long mask, unsigned long *addr)
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{
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#ifdef CONFIG_SMP
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int status;
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asm volatile(
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"1: mov %3,(_AAR,%2) \n"
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" mov (_ADR,%2),%0 \n"
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" or %4,%0 \n"
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" mov %0,(_ADR,%2) \n"
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" mov (_ADR,%2),%0 \n" /* flush */
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" mov (_ASR,%2),%0 \n"
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" or %0,%0 \n"
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" bne 1b \n"
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: "=&r"(status), "=m"(*addr)
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: "a"(ATOMIC_OPS_BASE_ADDR), "r"(addr), "r"(mask)
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: "memory", "cc");
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#else
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unsigned long flags;
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flags = arch_local_cli_save();
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*addr |= mask;
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arch_local_irq_restore(flags);
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#endif
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}
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#endif /* __KERNEL__ */
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#endif /* CONFIG_SMP */
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#endif /* _ASM_ATOMIC_H */
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