mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
870
arch/parisc/kernel/traps.c
Normal file
870
arch/parisc/kernel/traps.c
Normal file
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@ -0,0 +1,870 @@
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/*
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* linux/arch/parisc/traps.c
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*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright (C) 1999, 2000 Philipp Rumpf <prumpf@tux.org>
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*/
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/*
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* 'Traps.c' handles hardware traps and faults after we have saved some
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* state in 'asm.s'.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/ptrace.h>
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#include <linux/timer.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/console.h>
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#include <linux/bug.h>
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#include <linux/ratelimit.h>
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#include <asm/assembly.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/traps.h>
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#include <asm/unaligned.h>
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#include <linux/atomic.h>
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#include <asm/smp.h>
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#include <asm/pdc.h>
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#include <asm/pdc_chassis.h>
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#include <asm/unwind.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include "../math-emu/math-emu.h" /* for handle_fpe() */
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#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_SPINLOCK)
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DEFINE_SPINLOCK(pa_dbit_lock);
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#endif
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static void parisc_show_stack(struct task_struct *task, unsigned long *sp,
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struct pt_regs *regs);
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static int printbinary(char *buf, unsigned long x, int nbits)
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{
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unsigned long mask = 1UL << (nbits - 1);
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while (mask != 0) {
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*buf++ = (mask & x ? '1' : '0');
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mask >>= 1;
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}
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*buf = '\0';
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return nbits;
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}
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#ifdef CONFIG_64BIT
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#define RFMT "%016lx"
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#else
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#define RFMT "%08lx"
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#endif
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#define FFMT "%016llx" /* fpregs are 64-bit always */
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#define PRINTREGS(lvl,r,f,fmt,x) \
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printk("%s%s%02d-%02d " fmt " " fmt " " fmt " " fmt "\n", \
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lvl, f, (x), (x+3), (r)[(x)+0], (r)[(x)+1], \
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(r)[(x)+2], (r)[(x)+3])
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static void print_gr(char *level, struct pt_regs *regs)
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{
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int i;
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char buf[64];
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printk("%s\n", level);
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printk("%s YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI\n", level);
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printbinary(buf, regs->gr[0], 32);
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printk("%sPSW: %s %s\n", level, buf, print_tainted());
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for (i = 0; i < 32; i += 4)
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PRINTREGS(level, regs->gr, "r", RFMT, i);
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}
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static void print_fr(char *level, struct pt_regs *regs)
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{
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int i;
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char buf[64];
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struct { u32 sw[2]; } s;
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/* FR are 64bit everywhere. Need to use asm to get the content
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* of fpsr/fper1, and we assume that we won't have a FP Identify
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* in our way, otherwise we're screwed.
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* The fldd is used to restore the T-bit if there was one, as the
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* store clears it anyway.
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* PA2.0 book says "thou shall not use fstw on FPSR/FPERs" - T-Bone */
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asm volatile ("fstd %%fr0,0(%1) \n\t"
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"fldd 0(%1),%%fr0 \n\t"
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: "=m" (s) : "r" (&s) : "r0");
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printk("%s\n", level);
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printk("%s VZOUICununcqcqcqcqcqcrmunTDVZOUI\n", level);
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printbinary(buf, s.sw[0], 32);
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printk("%sFPSR: %s\n", level, buf);
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printk("%sFPER1: %08x\n", level, s.sw[1]);
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/* here we'll print fr0 again, tho it'll be meaningless */
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for (i = 0; i < 32; i += 4)
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PRINTREGS(level, regs->fr, "fr", FFMT, i);
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}
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void show_regs(struct pt_regs *regs)
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{
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int i, user;
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char *level;
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unsigned long cr30, cr31;
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user = user_mode(regs);
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level = user ? KERN_DEBUG : KERN_CRIT;
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show_regs_print_info(level);
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print_gr(level, regs);
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for (i = 0; i < 8; i += 4)
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PRINTREGS(level, regs->sr, "sr", RFMT, i);
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if (user)
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print_fr(level, regs);
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cr30 = mfctl(30);
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cr31 = mfctl(31);
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printk("%s\n", level);
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printk("%sIASQ: " RFMT " " RFMT " IAOQ: " RFMT " " RFMT "\n",
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level, regs->iasq[0], regs->iasq[1], regs->iaoq[0], regs->iaoq[1]);
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printk("%s IIR: %08lx ISR: " RFMT " IOR: " RFMT "\n",
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level, regs->iir, regs->isr, regs->ior);
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printk("%s CPU: %8d CR30: " RFMT " CR31: " RFMT "\n",
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level, current_thread_info()->cpu, cr30, cr31);
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printk("%s ORIG_R28: " RFMT "\n", level, regs->orig_r28);
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if (user) {
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printk("%s IAOQ[0]: " RFMT "\n", level, regs->iaoq[0]);
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printk("%s IAOQ[1]: " RFMT "\n", level, regs->iaoq[1]);
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printk("%s RP(r2): " RFMT "\n", level, regs->gr[2]);
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} else {
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printk("%s IAOQ[0]: %pS\n", level, (void *) regs->iaoq[0]);
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printk("%s IAOQ[1]: %pS\n", level, (void *) regs->iaoq[1]);
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printk("%s RP(r2): %pS\n", level, (void *) regs->gr[2]);
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parisc_show_stack(current, NULL, regs);
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}
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}
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static DEFINE_RATELIMIT_STATE(_hppa_rs,
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DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST);
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#define parisc_printk_ratelimited(critical, regs, fmt, ...) { \
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if ((critical || show_unhandled_signals) && __ratelimit(&_hppa_rs)) { \
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printk(fmt, ##__VA_ARGS__); \
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show_regs(regs); \
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} \
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}
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static void do_show_stack(struct unwind_frame_info *info)
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{
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int i = 1;
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printk(KERN_CRIT "Backtrace:\n");
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while (i <= 16) {
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if (unwind_once(info) < 0 || info->ip == 0)
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break;
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if (__kernel_text_address(info->ip)) {
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printk(KERN_CRIT " [<" RFMT ">] %pS\n",
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info->ip, (void *) info->ip);
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i++;
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}
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}
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printk(KERN_CRIT "\n");
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}
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static void parisc_show_stack(struct task_struct *task, unsigned long *sp,
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struct pt_regs *regs)
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{
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struct unwind_frame_info info;
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struct task_struct *t;
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t = task ? task : current;
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if (regs) {
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unwind_frame_init(&info, t, regs);
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goto show_stack;
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}
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if (t == current) {
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unsigned long sp;
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HERE:
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asm volatile ("copy %%r30, %0" : "=r"(sp));
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{
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struct pt_regs r;
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memset(&r, 0, sizeof(struct pt_regs));
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r.iaoq[0] = (unsigned long)&&HERE;
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r.gr[2] = (unsigned long)__builtin_return_address(0);
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r.gr[30] = sp;
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unwind_frame_init(&info, current, &r);
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}
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} else {
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unwind_frame_init_from_blocked_task(&info, t);
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}
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show_stack:
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do_show_stack(&info);
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}
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void show_stack(struct task_struct *t, unsigned long *sp)
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{
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return parisc_show_stack(t, sp, NULL);
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}
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int is_valid_bugaddr(unsigned long iaoq)
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{
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return 1;
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}
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void die_if_kernel(char *str, struct pt_regs *regs, long err)
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{
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if (user_mode(regs)) {
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if (err == 0)
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return; /* STFU */
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parisc_printk_ratelimited(1, regs,
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KERN_CRIT "%s (pid %d): %s (code %ld) at " RFMT "\n",
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current->comm, task_pid_nr(current), str, err, regs->iaoq[0]);
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return;
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}
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oops_in_progress = 1;
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oops_enter();
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/* Amuse the user in a SPARC fashion */
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if (err) printk(KERN_CRIT
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" _______________________________ \n"
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" < Your System ate a SPARC! Gah! >\n"
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" ------------------------------- \n"
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" \\ ^__^\n"
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" (__)\\ )\\/\\\n"
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" U ||----w |\n"
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" || ||\n");
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/* unlock the pdc lock if necessary */
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pdc_emergency_unlock();
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/* maybe the kernel hasn't booted very far yet and hasn't been able
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* to initialize the serial or STI console. In that case we should
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* re-enable the pdc console, so that the user will be able to
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* identify the problem. */
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if (!console_drivers)
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pdc_console_restart();
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if (err)
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printk(KERN_CRIT "%s (pid %d): %s (code %ld)\n",
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current->comm, task_pid_nr(current), str, err);
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/* Wot's wrong wif bein' racy? */
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if (current->thread.flags & PARISC_KERNEL_DEATH) {
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printk(KERN_CRIT "%s() recursion detected.\n", __func__);
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local_irq_enable();
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while (1);
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}
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current->thread.flags |= PARISC_KERNEL_DEATH;
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show_regs(regs);
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dump_stack();
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add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
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if (in_interrupt())
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panic("Fatal exception in interrupt");
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if (panic_on_oops) {
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printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
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ssleep(5);
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panic("Fatal exception");
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}
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oops_exit();
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do_exit(SIGSEGV);
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}
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/* gdb uses break 4,8 */
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#define GDB_BREAK_INSN 0x10004
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static void handle_gdb_break(struct pt_regs *regs, int wot)
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{
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struct siginfo si;
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si.si_signo = SIGTRAP;
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si.si_errno = 0;
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si.si_code = wot;
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si.si_addr = (void __user *) (regs->iaoq[0] & ~3);
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force_sig_info(SIGTRAP, &si, current);
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}
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static void handle_break(struct pt_regs *regs)
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{
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unsigned iir = regs->iir;
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if (unlikely(iir == PARISC_BUG_BREAK_INSN && !user_mode(regs))) {
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/* check if a BUG() or WARN() trapped here. */
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enum bug_trap_type tt;
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tt = report_bug(regs->iaoq[0] & ~3, regs);
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if (tt == BUG_TRAP_TYPE_WARN) {
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regs->iaoq[0] += 4;
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regs->iaoq[1] += 4;
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return; /* return to next instruction when WARN_ON(). */
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}
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die_if_kernel("Unknown kernel breakpoint", regs,
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(tt == BUG_TRAP_TYPE_NONE) ? 9 : 0);
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}
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if (unlikely(iir != GDB_BREAK_INSN))
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parisc_printk_ratelimited(0, regs,
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KERN_DEBUG "break %d,%d: pid=%d command='%s'\n",
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iir & 31, (iir>>13) & ((1<<13)-1),
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task_pid_nr(current), current->comm);
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/* send standard GDB signal */
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handle_gdb_break(regs, TRAP_BRKPT);
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}
|
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static void default_trap(int code, struct pt_regs *regs)
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{
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printk(KERN_ERR "Trap %d on CPU %d\n", code, smp_processor_id());
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show_regs(regs);
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}
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void (*cpu_lpmc) (int code, struct pt_regs *regs) __read_mostly = default_trap;
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|
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|
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void transfer_pim_to_trap_frame(struct pt_regs *regs)
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{
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register int i;
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extern unsigned int hpmc_pim_data[];
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struct pdc_hpmc_pim_11 *pim_narrow;
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struct pdc_hpmc_pim_20 *pim_wide;
|
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|
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if (boot_cpu_data.cpu_type >= pcxu) {
|
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|
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pim_wide = (struct pdc_hpmc_pim_20 *)hpmc_pim_data;
|
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|
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/*
|
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* Note: The following code will probably generate a
|
||||
* bunch of truncation error warnings from the compiler.
|
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* Could be handled with an ifdef, but perhaps there
|
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* is a better way.
|
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*/
|
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|
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regs->gr[0] = pim_wide->cr[22];
|
||||
|
||||
for (i = 1; i < 32; i++)
|
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regs->gr[i] = pim_wide->gr[i];
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
regs->fr[i] = pim_wide->fr[i];
|
||||
|
||||
for (i = 0; i < 8; i++)
|
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regs->sr[i] = pim_wide->sr[i];
|
||||
|
||||
regs->iasq[0] = pim_wide->cr[17];
|
||||
regs->iasq[1] = pim_wide->iasq_back;
|
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regs->iaoq[0] = pim_wide->cr[18];
|
||||
regs->iaoq[1] = pim_wide->iaoq_back;
|
||||
|
||||
regs->sar = pim_wide->cr[11];
|
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regs->iir = pim_wide->cr[19];
|
||||
regs->isr = pim_wide->cr[20];
|
||||
regs->ior = pim_wide->cr[21];
|
||||
}
|
||||
else {
|
||||
pim_narrow = (struct pdc_hpmc_pim_11 *)hpmc_pim_data;
|
||||
|
||||
regs->gr[0] = pim_narrow->cr[22];
|
||||
|
||||
for (i = 1; i < 32; i++)
|
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regs->gr[i] = pim_narrow->gr[i];
|
||||
|
||||
for (i = 0; i < 32; i++)
|
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regs->fr[i] = pim_narrow->fr[i];
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
regs->sr[i] = pim_narrow->sr[i];
|
||||
|
||||
regs->iasq[0] = pim_narrow->cr[17];
|
||||
regs->iasq[1] = pim_narrow->iasq_back;
|
||||
regs->iaoq[0] = pim_narrow->cr[18];
|
||||
regs->iaoq[1] = pim_narrow->iaoq_back;
|
||||
|
||||
regs->sar = pim_narrow->cr[11];
|
||||
regs->iir = pim_narrow->cr[19];
|
||||
regs->isr = pim_narrow->cr[20];
|
||||
regs->ior = pim_narrow->cr[21];
|
||||
}
|
||||
|
||||
/*
|
||||
* The following fields only have meaning if we came through
|
||||
* another path. So just zero them here.
|
||||
*/
|
||||
|
||||
regs->ksp = 0;
|
||||
regs->kpc = 0;
|
||||
regs->orig_r28 = 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* This routine is called as a last resort when everything else
|
||||
* has gone clearly wrong. We get called for faults in kernel space,
|
||||
* and HPMC's.
|
||||
*/
|
||||
void parisc_terminate(char *msg, struct pt_regs *regs, int code, unsigned long offset)
|
||||
{
|
||||
static DEFINE_SPINLOCK(terminate_lock);
|
||||
|
||||
oops_in_progress = 1;
|
||||
|
||||
set_eiem(0);
|
||||
local_irq_disable();
|
||||
spin_lock(&terminate_lock);
|
||||
|
||||
/* unlock the pdc lock if necessary */
|
||||
pdc_emergency_unlock();
|
||||
|
||||
/* restart pdc console if necessary */
|
||||
if (!console_drivers)
|
||||
pdc_console_restart();
|
||||
|
||||
/* Not all paths will gutter the processor... */
|
||||
switch(code){
|
||||
|
||||
case 1:
|
||||
transfer_pim_to_trap_frame(regs);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Fall through */
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
{
|
||||
/* show_stack(NULL, (unsigned long *)regs->gr[30]); */
|
||||
struct unwind_frame_info info;
|
||||
unwind_frame_init(&info, current, regs);
|
||||
do_show_stack(&info);
|
||||
}
|
||||
|
||||
printk("\n");
|
||||
printk(KERN_CRIT "%s: Code=%d regs=%p (Addr=" RFMT ")\n",
|
||||
msg, code, regs, offset);
|
||||
show_regs(regs);
|
||||
|
||||
spin_unlock(&terminate_lock);
|
||||
|
||||
/* put soft power button back under hardware control;
|
||||
* if the user had pressed it once at any time, the
|
||||
* system will shut down immediately right here. */
|
||||
pdc_soft_power_button(0);
|
||||
|
||||
/* Call kernel panic() so reboot timeouts work properly
|
||||
* FIXME: This function should be on the list of
|
||||
* panic notifiers, and we should call panic
|
||||
* directly from the location that we wish.
|
||||
* e.g. We should not call panic from
|
||||
* parisc_terminate, but rather the oter way around.
|
||||
* This hack works, prints the panic message twice,
|
||||
* and it enables reboot timers!
|
||||
*/
|
||||
panic(msg);
|
||||
}
|
||||
|
||||
void notrace handle_interruption(int code, struct pt_regs *regs)
|
||||
{
|
||||
unsigned long fault_address = 0;
|
||||
unsigned long fault_space = 0;
|
||||
struct siginfo si;
|
||||
|
||||
if (code == 1)
|
||||
pdc_console_restart(); /* switch back to pdc if HPMC */
|
||||
else
|
||||
local_irq_enable();
|
||||
|
||||
/* Security check:
|
||||
* If the priority level is still user, and the
|
||||
* faulting space is not equal to the active space
|
||||
* then the user is attempting something in a space
|
||||
* that does not belong to them. Kill the process.
|
||||
*
|
||||
* This is normally the situation when the user
|
||||
* attempts to jump into the kernel space at the
|
||||
* wrong offset, be it at the gateway page or a
|
||||
* random location.
|
||||
*
|
||||
* We cannot normally signal the process because it
|
||||
* could *be* on the gateway page, and processes
|
||||
* executing on the gateway page can't have signals
|
||||
* delivered.
|
||||
*
|
||||
* We merely readjust the address into the users
|
||||
* space, at a destination address of zero, and
|
||||
* allow processing to continue.
|
||||
*/
|
||||
if (((unsigned long)regs->iaoq[0] & 3) &&
|
||||
((unsigned long)regs->iasq[0] != (unsigned long)regs->sr[7])) {
|
||||
/* Kill the user process later */
|
||||
regs->iaoq[0] = 0 | 3;
|
||||
regs->iaoq[1] = regs->iaoq[0] + 4;
|
||||
regs->iasq[0] = regs->iasq[1] = regs->sr[7];
|
||||
regs->gr[0] &= ~PSW_B;
|
||||
return;
|
||||
}
|
||||
|
||||
#if 0
|
||||
printk(KERN_CRIT "Interruption # %d\n", code);
|
||||
#endif
|
||||
|
||||
switch(code) {
|
||||
|
||||
case 1:
|
||||
/* High-priority machine check (HPMC) */
|
||||
|
||||
/* set up a new led state on systems shipped with a LED State panel */
|
||||
pdc_chassis_send_status(PDC_CHASSIS_DIRECT_HPMC);
|
||||
|
||||
parisc_terminate("High Priority Machine Check (HPMC)",
|
||||
regs, code, 0);
|
||||
/* NOT REACHED */
|
||||
|
||||
case 2:
|
||||
/* Power failure interrupt */
|
||||
printk(KERN_CRIT "Power failure interrupt !\n");
|
||||
return;
|
||||
|
||||
case 3:
|
||||
/* Recovery counter trap */
|
||||
regs->gr[0] &= ~PSW_R;
|
||||
if (user_space(regs))
|
||||
handle_gdb_break(regs, TRAP_TRACE);
|
||||
/* else this must be the start of a syscall - just let it run */
|
||||
return;
|
||||
|
||||
case 5:
|
||||
/* Low-priority machine check */
|
||||
pdc_chassis_send_status(PDC_CHASSIS_DIRECT_LPMC);
|
||||
|
||||
flush_cache_all();
|
||||
flush_tlb_all();
|
||||
cpu_lpmc(5, regs);
|
||||
return;
|
||||
|
||||
case 6:
|
||||
/* Instruction TLB miss fault/Instruction page fault */
|
||||
fault_address = regs->iaoq[0];
|
||||
fault_space = regs->iasq[0];
|
||||
break;
|
||||
|
||||
case 8:
|
||||
/* Illegal instruction trap */
|
||||
die_if_kernel("Illegal instruction", regs, code);
|
||||
si.si_code = ILL_ILLOPC;
|
||||
goto give_sigill;
|
||||
|
||||
case 9:
|
||||
/* Break instruction trap */
|
||||
handle_break(regs);
|
||||
return;
|
||||
|
||||
case 10:
|
||||
/* Privileged operation trap */
|
||||
die_if_kernel("Privileged operation", regs, code);
|
||||
si.si_code = ILL_PRVOPC;
|
||||
goto give_sigill;
|
||||
|
||||
case 11:
|
||||
/* Privileged register trap */
|
||||
if ((regs->iir & 0xffdfffe0) == 0x034008a0) {
|
||||
|
||||
/* This is a MFCTL cr26/cr27 to gr instruction.
|
||||
* PCXS traps on this, so we need to emulate it.
|
||||
*/
|
||||
|
||||
if (regs->iir & 0x00200000)
|
||||
regs->gr[regs->iir & 0x1f] = mfctl(27);
|
||||
else
|
||||
regs->gr[regs->iir & 0x1f] = mfctl(26);
|
||||
|
||||
regs->iaoq[0] = regs->iaoq[1];
|
||||
regs->iaoq[1] += 4;
|
||||
regs->iasq[0] = regs->iasq[1];
|
||||
return;
|
||||
}
|
||||
|
||||
die_if_kernel("Privileged register usage", regs, code);
|
||||
si.si_code = ILL_PRVREG;
|
||||
give_sigill:
|
||||
si.si_signo = SIGILL;
|
||||
si.si_errno = 0;
|
||||
si.si_addr = (void __user *) regs->iaoq[0];
|
||||
force_sig_info(SIGILL, &si, current);
|
||||
return;
|
||||
|
||||
case 12:
|
||||
/* Overflow Trap, let the userland signal handler do the cleanup */
|
||||
si.si_signo = SIGFPE;
|
||||
si.si_code = FPE_INTOVF;
|
||||
si.si_addr = (void __user *) regs->iaoq[0];
|
||||
force_sig_info(SIGFPE, &si, current);
|
||||
return;
|
||||
|
||||
case 13:
|
||||
/* Conditional Trap
|
||||
The condition succeeds in an instruction which traps
|
||||
on condition */
|
||||
if(user_mode(regs)){
|
||||
si.si_signo = SIGFPE;
|
||||
/* Set to zero, and let the userspace app figure it out from
|
||||
the insn pointed to by si_addr */
|
||||
si.si_code = 0;
|
||||
si.si_addr = (void __user *) regs->iaoq[0];
|
||||
force_sig_info(SIGFPE, &si, current);
|
||||
return;
|
||||
}
|
||||
/* The kernel doesn't want to handle condition codes */
|
||||
break;
|
||||
|
||||
case 14:
|
||||
/* Assist Exception Trap, i.e. floating point exception. */
|
||||
die_if_kernel("Floating point exception", regs, 0); /* quiet */
|
||||
__inc_irq_stat(irq_fpassist_count);
|
||||
handle_fpe(regs);
|
||||
return;
|
||||
|
||||
case 15:
|
||||
/* Data TLB miss fault/Data page fault */
|
||||
/* Fall through */
|
||||
case 16:
|
||||
/* Non-access instruction TLB miss fault */
|
||||
/* The instruction TLB entry needed for the target address of the FIC
|
||||
is absent, and hardware can't find it, so we get to cleanup */
|
||||
/* Fall through */
|
||||
case 17:
|
||||
/* Non-access data TLB miss fault/Non-access data page fault */
|
||||
/* FIXME:
|
||||
Still need to add slow path emulation code here!
|
||||
If the insn used a non-shadow register, then the tlb
|
||||
handlers could not have their side-effect (e.g. probe
|
||||
writing to a target register) emulated since rfir would
|
||||
erase the changes to said register. Instead we have to
|
||||
setup everything, call this function we are in, and emulate
|
||||
by hand. Technically we need to emulate:
|
||||
fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw
|
||||
*/
|
||||
fault_address = regs->ior;
|
||||
fault_space = regs->isr;
|
||||
break;
|
||||
|
||||
case 18:
|
||||
/* PCXS only -- later cpu's split this into types 26,27 & 28 */
|
||||
/* Check for unaligned access */
|
||||
if (check_unaligned(regs)) {
|
||||
handle_unaligned(regs);
|
||||
return;
|
||||
}
|
||||
/* Fall Through */
|
||||
case 26:
|
||||
/* PCXL: Data memory access rights trap */
|
||||
fault_address = regs->ior;
|
||||
fault_space = regs->isr;
|
||||
break;
|
||||
|
||||
case 19:
|
||||
/* Data memory break trap */
|
||||
regs->gr[0] |= PSW_X; /* So we can single-step over the trap */
|
||||
/* fall thru */
|
||||
case 21:
|
||||
/* Page reference trap */
|
||||
handle_gdb_break(regs, TRAP_HWBKPT);
|
||||
return;
|
||||
|
||||
case 25:
|
||||
/* Taken branch trap */
|
||||
regs->gr[0] &= ~PSW_T;
|
||||
if (user_space(regs))
|
||||
handle_gdb_break(regs, TRAP_BRANCH);
|
||||
/* else this must be the start of a syscall - just let it
|
||||
* run.
|
||||
*/
|
||||
return;
|
||||
|
||||
case 7:
|
||||
/* Instruction access rights */
|
||||
/* PCXL: Instruction memory protection trap */
|
||||
|
||||
/*
|
||||
* This could be caused by either: 1) a process attempting
|
||||
* to execute within a vma that does not have execute
|
||||
* permission, or 2) an access rights violation caused by a
|
||||
* flush only translation set up by ptep_get_and_clear().
|
||||
* So we check the vma permissions to differentiate the two.
|
||||
* If the vma indicates we have execute permission, then
|
||||
* the cause is the latter one. In this case, we need to
|
||||
* call do_page_fault() to fix the problem.
|
||||
*/
|
||||
|
||||
if (user_mode(regs)) {
|
||||
struct vm_area_struct *vma;
|
||||
|
||||
down_read(¤t->mm->mmap_sem);
|
||||
vma = find_vma(current->mm,regs->iaoq[0]);
|
||||
if (vma && (regs->iaoq[0] >= vma->vm_start)
|
||||
&& (vma->vm_flags & VM_EXEC)) {
|
||||
|
||||
fault_address = regs->iaoq[0];
|
||||
fault_space = regs->iasq[0];
|
||||
|
||||
up_read(¤t->mm->mmap_sem);
|
||||
break; /* call do_page_fault() */
|
||||
}
|
||||
up_read(¤t->mm->mmap_sem);
|
||||
}
|
||||
/* Fall Through */
|
||||
case 27:
|
||||
/* Data memory protection ID trap */
|
||||
if (code == 27 && !user_mode(regs) &&
|
||||
fixup_exception(regs))
|
||||
return;
|
||||
|
||||
die_if_kernel("Protection id trap", regs, code);
|
||||
si.si_code = SEGV_MAPERR;
|
||||
si.si_signo = SIGSEGV;
|
||||
si.si_errno = 0;
|
||||
if (code == 7)
|
||||
si.si_addr = (void __user *) regs->iaoq[0];
|
||||
else
|
||||
si.si_addr = (void __user *) regs->ior;
|
||||
force_sig_info(SIGSEGV, &si, current);
|
||||
return;
|
||||
|
||||
case 28:
|
||||
/* Unaligned data reference trap */
|
||||
handle_unaligned(regs);
|
||||
return;
|
||||
|
||||
default:
|
||||
if (user_mode(regs)) {
|
||||
parisc_printk_ratelimited(0, regs, KERN_DEBUG
|
||||
"handle_interruption() pid=%d command='%s'\n",
|
||||
task_pid_nr(current), current->comm);
|
||||
/* SIGBUS, for lack of a better one. */
|
||||
si.si_signo = SIGBUS;
|
||||
si.si_code = BUS_OBJERR;
|
||||
si.si_errno = 0;
|
||||
si.si_addr = (void __user *) regs->ior;
|
||||
force_sig_info(SIGBUS, &si, current);
|
||||
return;
|
||||
}
|
||||
pdc_chassis_send_status(PDC_CHASSIS_DIRECT_PANIC);
|
||||
|
||||
parisc_terminate("Unexpected interruption", regs, code, 0);
|
||||
/* NOT REACHED */
|
||||
}
|
||||
|
||||
if (user_mode(regs)) {
|
||||
if ((fault_space >> SPACEID_SHIFT) != (regs->sr[7] >> SPACEID_SHIFT)) {
|
||||
parisc_printk_ratelimited(0, regs, KERN_DEBUG
|
||||
"User fault %d on space 0x%08lx, pid=%d command='%s'\n",
|
||||
code, fault_space,
|
||||
task_pid_nr(current), current->comm);
|
||||
si.si_signo = SIGSEGV;
|
||||
si.si_errno = 0;
|
||||
si.si_code = SEGV_MAPERR;
|
||||
si.si_addr = (void __user *) regs->ior;
|
||||
force_sig_info(SIGSEGV, &si, current);
|
||||
return;
|
||||
}
|
||||
}
|
||||
else {
|
||||
|
||||
/*
|
||||
* The kernel should never fault on its own address space,
|
||||
* unless pagefault_disable() was called before.
|
||||
*/
|
||||
|
||||
if (fault_space == 0 && !in_atomic())
|
||||
{
|
||||
pdc_chassis_send_status(PDC_CHASSIS_DIRECT_PANIC);
|
||||
parisc_terminate("Kernel Fault", regs, code, fault_address);
|
||||
}
|
||||
}
|
||||
|
||||
do_page_fault(regs, code, fault_address);
|
||||
}
|
||||
|
||||
|
||||
int __init check_ivt(void *iva)
|
||||
{
|
||||
extern u32 os_hpmc_size;
|
||||
extern const u32 os_hpmc[];
|
||||
|
||||
int i;
|
||||
u32 check = 0;
|
||||
u32 *ivap;
|
||||
u32 *hpmcp;
|
||||
u32 length;
|
||||
|
||||
if (strcmp((char *)iva, "cows can fly"))
|
||||
return -1;
|
||||
|
||||
ivap = (u32 *)iva;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
*ivap++ = 0;
|
||||
|
||||
/* Compute Checksum for HPMC handler */
|
||||
length = os_hpmc_size;
|
||||
ivap[7] = length;
|
||||
|
||||
hpmcp = (u32 *)os_hpmc;
|
||||
|
||||
for (i=0; i<length/4; i++)
|
||||
check += *hpmcp++;
|
||||
|
||||
for (i=0; i<8; i++)
|
||||
check += ivap[i];
|
||||
|
||||
ivap[5] = -check;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_64BIT
|
||||
extern const void fault_vector_11;
|
||||
#endif
|
||||
extern const void fault_vector_20;
|
||||
|
||||
void __init trap_init(void)
|
||||
{
|
||||
void *iva;
|
||||
|
||||
if (boot_cpu_data.cpu_type >= pcxu)
|
||||
iva = (void *) &fault_vector_20;
|
||||
else
|
||||
#ifdef CONFIG_64BIT
|
||||
panic("Can't boot 64-bit OS on PA1.1 processor!");
|
||||
#else
|
||||
iva = (void *) &fault_vector_11;
|
||||
#endif
|
||||
|
||||
if (check_ivt(iva))
|
||||
panic("IVT invalid");
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue