mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
16
arch/powerpc/boot/44x.h
Normal file
16
arch/powerpc/boot/44x.h
Normal file
|
|
@ -0,0 +1,16 @@
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|||
/*
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* PowerPC 44x related functions
|
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*
|
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* Copyright 2007 David Gibson, IBM Corporation.
|
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*
|
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* This file is licensed under the terms of the GNU General Public
|
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* License version 2. This program is licensed "as is" without any
|
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* warranty of any kind, whether express or implied.
|
||||
*/
|
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#ifndef _PPC_BOOT_44X_H_
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#define _PPC_BOOT_44X_H_
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void ebony_init(void *mac0, void *mac1);
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void bamboo_init(void *mac0, void *mac1);
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|
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#endif /* _PPC_BOOT_44X_H_ */
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803
arch/powerpc/boot/4xx.c
Normal file
803
arch/powerpc/boot/4xx.c
Normal file
|
|
@ -0,0 +1,803 @@
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|||
/*
|
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* Copyright 2007 David Gibson, IBM Corporation.
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*
|
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* Based on earlier code:
|
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* Matt Porter <mporter@kernel.crashing.org>
|
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* Copyright 2002-2005 MontaVista Software Inc.
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*
|
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
|
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* Copyright (c) 2003, 2004 Zultys Technologies
|
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*
|
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* Copyright (C) 2009 Wind River Systems, Inc.
|
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* Updated for supporting PPC405EX on Kilauea.
|
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* Tiejun Chen <tiejun.chen@windriver.com>
|
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*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
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*/
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#include <stddef.h>
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#include "types.h"
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#include "string.h"
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#include "stdio.h"
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#include "ops.h"
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#include "reg.h"
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#include "dcr.h"
|
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|
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static unsigned long chip_11_errata(unsigned long memsize)
|
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{
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unsigned long pvr;
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pvr = mfpvr();
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|
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switch (pvr & 0xf0000ff0) {
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case 0x40000850:
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case 0x400008d0:
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case 0x200008d0:
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memsize -= 4096;
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break;
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default:
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break;
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}
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return memsize;
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}
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|
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/* Read the 4xx SDRAM controller to get size of system memory. */
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void ibm4xx_sdram_fixup_memsize(void)
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{
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int i;
|
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unsigned long memsize, bank_config;
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|
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memsize = 0;
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for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
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bank_config = SDRAM0_READ(sdram_bxcr[i]);
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if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
|
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memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
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}
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|
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memsize = chip_11_errata(memsize);
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dt_fixup_memory(0, memsize);
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}
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|
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/* Read the 440SPe MQ controller to get size of system memory. */
|
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#define DCRN_MQ0_B0BAS 0x40
|
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#define DCRN_MQ0_B1BAS 0x41
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#define DCRN_MQ0_B2BAS 0x42
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#define DCRN_MQ0_B3BAS 0x43
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|
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static u64 ibm440spe_decode_bas(u32 bas)
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{
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u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
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|
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/* open coded because I'm paranoid about invalid values */
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switch ((bas >> 4) & 0xFFF) {
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case 0:
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return 0;
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case 0xffc:
|
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return base + 0x000800000ull;
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case 0xff8:
|
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return base + 0x001000000ull;
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case 0xff0:
|
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return base + 0x002000000ull;
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case 0xfe0:
|
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return base + 0x004000000ull;
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||||
case 0xfc0:
|
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return base + 0x008000000ull;
|
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case 0xf80:
|
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return base + 0x010000000ull;
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case 0xf00:
|
||||
return base + 0x020000000ull;
|
||||
case 0xe00:
|
||||
return base + 0x040000000ull;
|
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case 0xc00:
|
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return base + 0x080000000ull;
|
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case 0x800:
|
||||
return base + 0x100000000ull;
|
||||
}
|
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printf("Memory BAS value 0x%08x unsupported !\n", bas);
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return 0;
|
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}
|
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|
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void ibm440spe_fixup_memsize(void)
|
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{
|
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u64 banktop, memsize = 0;
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|
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/* Ultimately, we should directly construct the memory node
|
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* so we are able to handle holes in the memory address space
|
||||
*/
|
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
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if (banktop > memsize)
|
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memsize = banktop;
|
||||
banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
|
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if (banktop > memsize)
|
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memsize = banktop;
|
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
|
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if (banktop > memsize)
|
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memsize = banktop;
|
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
|
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if (banktop > memsize)
|
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memsize = banktop;
|
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|
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dt_fixup_memory(0, memsize);
|
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}
|
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|
||||
|
||||
/* 4xx DDR1/2 Denali memory controller support */
|
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/* DDR0 registers */
|
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#define DDR0_02 2
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#define DDR0_08 8
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#define DDR0_10 10
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#define DDR0_14 14
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#define DDR0_42 42
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#define DDR0_43 43
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/* DDR0_02 */
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#define DDR_START 0x1
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#define DDR_START_SHIFT 0
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#define DDR_MAX_CS_REG 0x3
|
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#define DDR_MAX_CS_REG_SHIFT 24
|
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#define DDR_MAX_COL_REG 0xf
|
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#define DDR_MAX_COL_REG_SHIFT 16
|
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#define DDR_MAX_ROW_REG 0xf
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#define DDR_MAX_ROW_REG_SHIFT 8
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/* DDR0_08 */
|
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#define DDR_DDR2_MODE 0x1
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#define DDR_DDR2_MODE_SHIFT 0
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/* DDR0_10 */
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#define DDR_CS_MAP 0x3
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#define DDR_CS_MAP_SHIFT 8
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/* DDR0_14 */
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#define DDR_REDUC 0x1
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#define DDR_REDUC_SHIFT 16
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/* DDR0_42 */
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#define DDR_APIN 0x7
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#define DDR_APIN_SHIFT 24
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/* DDR0_43 */
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#define DDR_COL_SZ 0x7
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#define DDR_COL_SZ_SHIFT 8
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#define DDR_BANK8 0x1
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#define DDR_BANK8_SHIFT 0
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#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
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/*
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* Some U-Boot versions set the number of chipselects to two
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* for Sequoia/Rainier boards while they only have one chipselect
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* hardwired. Hardcode the number of chipselects to one
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* for sequioa/rainer board models or read the actual value
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* from the memory controller register DDR0_10 otherwise.
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*/
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static inline u32 ibm4xx_denali_get_cs(void)
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{
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void *devp;
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char model[64];
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u32 val, cs;
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devp = finddevice("/");
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if (!devp)
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goto read_cs;
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if (getprop(devp, "model", model, sizeof(model)) <= 0)
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goto read_cs;
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model[sizeof(model)-1] = 0;
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if (!strcmp(model, "amcc,sequoia") ||
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!strcmp(model, "amcc,rainier"))
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return 1;
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read_cs:
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/* get CS value */
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val = SDRAM0_READ(DDR0_10);
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val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
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cs = 0;
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while (val) {
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if (val & 0x1)
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cs++;
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val = val >> 1;
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}
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return cs;
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}
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void ibm4xx_denali_fixup_memsize(void)
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{
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u32 val, max_cs, max_col, max_row;
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u32 cs, col, row, bank, dpath;
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unsigned long memsize;
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val = SDRAM0_READ(DDR0_02);
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if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
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fatal("DDR controller is not initialized\n");
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/* get maximum cs col and row values */
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max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
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max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
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max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
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cs = ibm4xx_denali_get_cs();
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if (!cs)
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fatal("No memory installed\n");
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if (cs > max_cs)
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fatal("DDR wrong CS configuration\n");
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/* get data path bytes */
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val = SDRAM0_READ(DDR0_14);
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if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
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dpath = 4; /* 32 bits */
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else
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dpath = 8; /* 64 bits */
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|
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/* get address pins (rows) */
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val = SDRAM0_READ(DDR0_42);
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|
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row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
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if (row > max_row)
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fatal("DDR wrong APIN configuration\n");
|
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row = max_row - row;
|
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|
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/* get collomn size and banks */
|
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val = SDRAM0_READ(DDR0_43);
|
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|
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col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
|
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if (col > max_col)
|
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fatal("DDR wrong COL configuration\n");
|
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col = max_col - col;
|
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|
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if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
|
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bank = 8; /* 8 banks */
|
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else
|
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bank = 4; /* 4 banks */
|
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|
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memsize = cs * (1 << (col+row)) * bank * dpath;
|
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memsize = chip_11_errata(memsize);
|
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dt_fixup_memory(0, memsize);
|
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}
|
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|
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#define SPRN_DBCR0_40X 0x3F2
|
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#define SPRN_DBCR0_44X 0x134
|
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#define DBCR0_RST_SYSTEM 0x30000000
|
||||
|
||||
void ibm44x_dbcr_reset(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
asm volatile (
|
||||
"mfspr %0,%1\n"
|
||||
"oris %0,%0,%2@h\n"
|
||||
"mtspr %1,%0"
|
||||
: "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
void ibm40x_dbcr_reset(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
asm volatile (
|
||||
"mfspr %0,%1\n"
|
||||
"oris %0,%0,%2@h\n"
|
||||
"mtspr %1,%0"
|
||||
: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
|
||||
);
|
||||
}
|
||||
|
||||
#define EMAC_RESET 0x20000000
|
||||
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
|
||||
{
|
||||
/* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
|
||||
* do this for us
|
||||
*/
|
||||
if (emac0)
|
||||
*emac0 = EMAC_RESET;
|
||||
if (emac1)
|
||||
*emac1 = EMAC_RESET;
|
||||
|
||||
mtdcr(DCRN_MAL0_CFG, MAL_RESET);
|
||||
while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
|
||||
; /* loop until reset takes effect */
|
||||
}
|
||||
|
||||
/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
|
||||
* banks into the OPB address space */
|
||||
void ibm4xx_fixup_ebc_ranges(const char *ebc)
|
||||
{
|
||||
void *devp;
|
||||
u32 bxcr;
|
||||
u32 ranges[EBC_NUM_BANKS*4];
|
||||
u32 *p = ranges;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < EBC_NUM_BANKS; i++) {
|
||||
mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
|
||||
bxcr = mfdcr(DCRN_EBC0_CFGDATA);
|
||||
|
||||
if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
|
||||
*p++ = i;
|
||||
*p++ = 0;
|
||||
*p++ = bxcr & EBC_BXCR_BAS;
|
||||
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
|
||||
}
|
||||
}
|
||||
|
||||
devp = finddevice(ebc);
|
||||
if (! devp)
|
||||
fatal("Couldn't locate EBC node %s\n\r", ebc);
|
||||
|
||||
setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
|
||||
}
|
||||
|
||||
/* Calculate 440GP clocks */
|
||||
void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
|
||||
{
|
||||
u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
|
||||
u32 cr0 = mfdcr(DCRN_CPC0_CR0);
|
||||
u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
|
||||
u32 opdv = CPC0_SYS0_OPDV(sys0);
|
||||
u32 epdv = CPC0_SYS0_EPDV(sys0);
|
||||
|
||||
if (sys0 & CPC0_SYS0_BYPASS) {
|
||||
/* Bypass system PLL */
|
||||
cpu = plb = sys_clk;
|
||||
} else {
|
||||
if (sys0 & CPC0_SYS0_EXTSL)
|
||||
/* PerClk */
|
||||
m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
|
||||
else
|
||||
/* CPU clock */
|
||||
m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
|
||||
cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
|
||||
plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
|
||||
}
|
||||
|
||||
opb = plb / opdv;
|
||||
ebc = opb / epdv;
|
||||
|
||||
/* FIXME: Check if this is for all 440GP, or just Ebony */
|
||||
if ((mfpvr() & 0xf0000fff) == 0x40000440)
|
||||
/* Rev. B 440GP, use external system clock */
|
||||
tb = sys_clk;
|
||||
else
|
||||
/* Rev. C 440GP, errata force us to use internal clock */
|
||||
tb = cpu;
|
||||
|
||||
if (cr0 & CPC0_CR0_U0EC)
|
||||
/* External UART clock */
|
||||
uart0 = ser_clk;
|
||||
else
|
||||
/* Internal UART clock */
|
||||
uart0 = plb / CPC0_CR0_UDIV(cr0);
|
||||
|
||||
if (cr0 & CPC0_CR0_U1EC)
|
||||
/* External UART clock */
|
||||
uart1 = ser_clk;
|
||||
else
|
||||
/* Internal UART clock */
|
||||
uart1 = plb / CPC0_CR0_UDIV(cr0);
|
||||
|
||||
printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
|
||||
(sys_clk + 500000) / 1000000, sys_clk);
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/opb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@40000200", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@40000300", uart1);
|
||||
}
|
||||
|
||||
#define SPRN_CCR1 0x378
|
||||
|
||||
static inline u32 __fix_zero(u32 v, u32 def)
|
||||
{
|
||||
return v ? v : def;
|
||||
}
|
||||
|
||||
static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int tmr_clk,
|
||||
int per_clk_from_opb)
|
||||
{
|
||||
/* PLL config */
|
||||
u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
|
||||
u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
|
||||
|
||||
/* Dividers */
|
||||
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
|
||||
u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
|
||||
u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
|
||||
u32 lfbdv = __fix_zero(plld & 0x3f, 64);
|
||||
u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
|
||||
u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
|
||||
u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
|
||||
u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
|
||||
|
||||
/* Input clocks for primary dividers */
|
||||
u32 clk_a, clk_b;
|
||||
|
||||
/* Resulting clocks */
|
||||
u32 cpu, plb, opb, ebc, vco;
|
||||
|
||||
/* Timebase */
|
||||
u32 ccr1, tb = tmr_clk;
|
||||
|
||||
if (pllc & 0x40000000) {
|
||||
u32 m;
|
||||
|
||||
/* Feedback path */
|
||||
switch ((pllc >> 24) & 7) {
|
||||
case 0:
|
||||
/* PLLOUTx */
|
||||
m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
|
||||
break;
|
||||
case 1:
|
||||
/* CPU */
|
||||
m = fwdva * pradv0;
|
||||
break;
|
||||
case 5:
|
||||
/* PERClk */
|
||||
m = fwdvb * prbdv0 * opbdv0 * perdv0;
|
||||
break;
|
||||
default:
|
||||
printf("WARNING ! Invalid PLL feedback source !\n");
|
||||
goto bypass;
|
||||
}
|
||||
m *= fbdv;
|
||||
vco = sys_clk * m;
|
||||
clk_a = vco / fwdva;
|
||||
clk_b = vco / fwdvb;
|
||||
} else {
|
||||
bypass:
|
||||
/* Bypass system PLL */
|
||||
vco = 0;
|
||||
clk_a = clk_b = sys_clk;
|
||||
}
|
||||
|
||||
cpu = clk_a / pradv0;
|
||||
plb = clk_b / prbdv0;
|
||||
opb = plb / opbdv0;
|
||||
ebc = (per_clk_from_opb ? opb : plb) / perdv0;
|
||||
|
||||
/* Figure out timebase. Either CPU or default TmrClk */
|
||||
ccr1 = mfspr(SPRN_CCR1);
|
||||
|
||||
/* If passed a 0 tmr_clk, force CPU clock */
|
||||
if (tb == 0) {
|
||||
ccr1 &= ~0x80u;
|
||||
mtspr(SPRN_CCR1, ccr1);
|
||||
}
|
||||
if ((ccr1 & 0x0080) == 0)
|
||||
tb = cpu;
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/opb/ebc", ebc);
|
||||
|
||||
return plb;
|
||||
}
|
||||
|
||||
static void eplike_fixup_uart_clk(int index, const char *path,
|
||||
unsigned int ser_clk,
|
||||
unsigned int plb_clk)
|
||||
{
|
||||
unsigned int sdr;
|
||||
unsigned int clock;
|
||||
|
||||
switch (index) {
|
||||
case 0:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART0);
|
||||
break;
|
||||
case 1:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART1);
|
||||
break;
|
||||
case 2:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART2);
|
||||
break;
|
||||
case 3:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART3);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
if (sdr & 0x00800000u)
|
||||
clock = ser_clk;
|
||||
else
|
||||
clock = plb_clk / __fix_zero(sdr & 0xff, 256);
|
||||
|
||||
dt_fixup_clock(path, clock);
|
||||
}
|
||||
|
||||
void ibm440ep_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int ser_clk,
|
||||
unsigned int tmr_clk)
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
|
||||
|
||||
/* serial clocks need fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
|
||||
}
|
||||
|
||||
void ibm440gx_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int ser_clk,
|
||||
unsigned int tmr_clk)
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
|
||||
|
||||
/* serial clocks need fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
|
||||
}
|
||||
|
||||
void ibm440spe_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int ser_clk,
|
||||
unsigned int tmr_clk)
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
|
||||
|
||||
/* serial clocks need fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
|
||||
}
|
||||
|
||||
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
|
||||
{
|
||||
u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
|
||||
u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
|
||||
u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
|
||||
u32 psr = mfdcr(DCRN_405_CPC0_PSR);
|
||||
u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
|
||||
u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
|
||||
|
||||
fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
|
||||
fbdv = (pllmr & 0x1e000000) >> 25;
|
||||
if (fbdv == 0)
|
||||
fbdv = 16;
|
||||
cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
|
||||
opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
|
||||
ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
|
||||
epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
|
||||
udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
|
||||
|
||||
/* check for 405GPr */
|
||||
if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
|
||||
fwdvb = 8 - (pllmr & 0x00000007);
|
||||
if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
|
||||
if (psr & 0x00000020) /* New mode enable */
|
||||
m = fwdvb * 2 * ppdv;
|
||||
else
|
||||
m = fwdvb * cbdv * ppdv;
|
||||
else if (psr & 0x00000020) /* New mode enable */
|
||||
if (psr & 0x00000800) /* PerClk synch mode */
|
||||
m = fwdvb * 2 * epdv;
|
||||
else
|
||||
m = fbdv * fwdv;
|
||||
else if (epdv == fbdv)
|
||||
m = fbdv * cbdv * epdv;
|
||||
else
|
||||
m = fbdv * fwdvb * cbdv;
|
||||
|
||||
cpu = sys_clk * m / fwdv;
|
||||
plb = sys_clk * m / (fwdvb * cbdv);
|
||||
} else {
|
||||
m = fwdv * fbdv * cbdv;
|
||||
cpu = sys_clk * m / fwdv;
|
||||
plb = cpu / cbdv;
|
||||
}
|
||||
opb = plb / opdv;
|
||||
ebc = plb / epdv;
|
||||
|
||||
if (cpc0_cr0 & 0x80)
|
||||
/* uart0 uses the external clock */
|
||||
uart0 = ser_clk;
|
||||
else
|
||||
uart0 = cpu / udiv;
|
||||
|
||||
if (cpc0_cr0 & 0x40)
|
||||
/* uart1 uses the external clock */
|
||||
uart1 = ser_clk;
|
||||
else
|
||||
uart1 = cpu / udiv;
|
||||
|
||||
/* setup the timebase clock to tick at the cpu frequency */
|
||||
cpc0_cr1 = cpc0_cr1 & ~0x00800000;
|
||||
mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
|
||||
tb = cpu;
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
|
||||
}
|
||||
|
||||
|
||||
void ibm405ep_fixup_clocks(unsigned int sys_clk)
|
||||
{
|
||||
u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
|
||||
u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
|
||||
u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
|
||||
u32 cpu, plb, opb, ebc, uart0, uart1;
|
||||
u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
|
||||
u32 pllmr0_ccdv, tb, m;
|
||||
|
||||
fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
|
||||
fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
|
||||
fbdv = (pllmr1 & 0x00f00000) >> 20;
|
||||
if (fbdv == 0)
|
||||
fbdv = 16;
|
||||
|
||||
cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
|
||||
epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
|
||||
opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
|
||||
|
||||
m = fbdv * fwdvb;
|
||||
|
||||
pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
|
||||
if (pllmr1 & 0x80000000)
|
||||
cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
|
||||
else
|
||||
cpu = sys_clk / pllmr0_ccdv;
|
||||
|
||||
plb = cpu / cbdv;
|
||||
opb = plb / opdv;
|
||||
ebc = plb / epdv;
|
||||
tb = cpu;
|
||||
uart0 = cpu / (cpc0_ucr & 0x0000007f);
|
||||
uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
|
||||
}
|
||||
|
||||
static u8 ibm405ex_fwdv_multi_bits[] = {
|
||||
/* values for: 1 - 16 */
|
||||
0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
|
||||
0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
|
||||
};
|
||||
|
||||
u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)
|
||||
{
|
||||
u32 index;
|
||||
|
||||
for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)
|
||||
if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])
|
||||
return index + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 ibm405ex_fbdv_multi_bits[] = {
|
||||
/* values for: 1 - 100 */
|
||||
0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
|
||||
0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
|
||||
0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
|
||||
0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
|
||||
0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
|
||||
0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
|
||||
0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
|
||||
0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
|
||||
0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
|
||||
0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
|
||||
/* values for: 101 - 200 */
|
||||
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
|
||||
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
|
||||
0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
|
||||
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
|
||||
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
|
||||
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
|
||||
0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
|
||||
0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
|
||||
0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
|
||||
0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
|
||||
/* values for: 201 - 255 */
|
||||
0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
|
||||
0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
|
||||
0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
|
||||
0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
|
||||
0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
|
||||
0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
|
||||
};
|
||||
|
||||
u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)
|
||||
{
|
||||
u32 index;
|
||||
|
||||
for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)
|
||||
if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])
|
||||
return index + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
|
||||
{
|
||||
/* PLL config */
|
||||
u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
|
||||
u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
|
||||
u32 cpud = CPR0_READ(DCRN_CPR0_PRIMAD);
|
||||
u32 plbd = CPR0_READ(DCRN_CPR0_PRIMBD);
|
||||
u32 opbd = CPR0_READ(DCRN_CPR0_OPBD);
|
||||
u32 perd = CPR0_READ(DCRN_CPR0_PERD);
|
||||
|
||||
/* Dividers */
|
||||
u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
|
||||
|
||||
u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
|
||||
|
||||
u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
|
||||
|
||||
/* PLBDV0 is hardwared to 010. */
|
||||
u32 plbdv0 = 2;
|
||||
u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
|
||||
|
||||
u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
|
||||
|
||||
u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
|
||||
|
||||
/* Resulting clocks */
|
||||
u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
|
||||
|
||||
/* PLL's VCO is the source for primary forward ? */
|
||||
if (pllc & 0x40000000) {
|
||||
u32 m;
|
||||
|
||||
/* Feedback path */
|
||||
switch ((pllc >> 24) & 7) {
|
||||
case 0:
|
||||
/* PLLOUTx */
|
||||
m = fbdv;
|
||||
break;
|
||||
case 1:
|
||||
/* CPU */
|
||||
m = fbdv * fwdva * cpudv0;
|
||||
break;
|
||||
case 5:
|
||||
/* PERClk */
|
||||
m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
|
||||
break;
|
||||
default:
|
||||
printf("WARNING ! Invalid PLL feedback source !\n");
|
||||
goto bypass;
|
||||
}
|
||||
|
||||
vco = (unsigned int)(sys_clk * m);
|
||||
} else {
|
||||
bypass:
|
||||
/* Bypass system PLL */
|
||||
vco = 0;
|
||||
}
|
||||
|
||||
/* CPU = VCO / ( FWDVA x CPUDV0) */
|
||||
cpu = vco / (fwdva * cpudv0);
|
||||
/* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
|
||||
plb = vco / (fwdva * plb2xdv0 * plbdv0);
|
||||
/* OPB = PLB / OPBDV0 */
|
||||
opb = plb / opbdv0;
|
||||
/* EBC = OPB / PERDV0 */
|
||||
ebc = opb / perdv0;
|
||||
|
||||
tb = cpu;
|
||||
uart0 = uart1 = uart_clk;
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/opb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
|
||||
}
|
||||
33
arch/powerpc/boot/4xx.h
Normal file
33
arch/powerpc/boot/4xx.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* PowerPC 4xx related functions
|
||||
*
|
||||
* Copyright 2007 IBM Corporation.
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#ifndef _POWERPC_BOOT_4XX_H_
|
||||
#define _POWERPC_BOOT_4XX_H_
|
||||
|
||||
void ibm4xx_sdram_fixup_memsize(void);
|
||||
void ibm440spe_fixup_memsize(void);
|
||||
void ibm4xx_denali_fixup_memsize(void);
|
||||
void ibm44x_dbcr_reset(void);
|
||||
void ibm40x_dbcr_reset(void);
|
||||
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
|
||||
void ibm4xx_fixup_ebc_ranges(const char *ebc);
|
||||
|
||||
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
|
||||
void ibm405ep_fixup_clocks(unsigned int sys_clk);
|
||||
void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk);
|
||||
void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
|
||||
void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
|
||||
unsigned int tmr_clk);
|
||||
void ibm440gx_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
|
||||
unsigned int tmr_clk);
|
||||
void ibm440spe_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
|
||||
unsigned int tmr_clk);
|
||||
|
||||
#endif /* _POWERPC_BOOT_4XX_H_ */
|
||||
457
arch/powerpc/boot/Makefile
Normal file
457
arch/powerpc/boot/Makefile
Normal file
|
|
@ -0,0 +1,457 @@
|
|||
# Makefile for making ELF bootable images for booting on CHRP
|
||||
# using Open Firmware.
|
||||
#
|
||||
# Geert Uytterhoeven September 1997
|
||||
#
|
||||
# Based on coffboot by Paul Mackerras
|
||||
# Simplified for ppc64 by Todd Inglett
|
||||
#
|
||||
# NOTE: this code is built for 32 bit in ELF32 format even though
|
||||
# it packages a 64 bit kernel. We do this to simplify the
|
||||
# bootloader and increase compatibility with OpenFirmware.
|
||||
#
|
||||
# To this end we need to define BOOTCC, etc, as the tools
|
||||
# needed to build the 32 bit image. That's normally the same
|
||||
# compiler for the rest of the kernel, with the -m32 flag added.
|
||||
# To make it easier to setup a cross compiler,
|
||||
# CROSS32_COMPILE is setup as a prefix just like CROSS_COMPILE
|
||||
# in the toplevel makefile.
|
||||
|
||||
all: $(obj)/zImage
|
||||
|
||||
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
|
||||
-fno-strict-aliasing -Os -msoft-float -pipe \
|
||||
-fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
|
||||
-isystem $(shell $(CROSS32CC) -print-file-name=include)
|
||||
ifdef CONFIG_PPC64_BOOT_WRAPPER
|
||||
BOOTCFLAGS += -m64
|
||||
endif
|
||||
ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
BOOTCFLAGS += -mbig-endian
|
||||
endif
|
||||
|
||||
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
|
||||
|
||||
ifdef CONFIG_DEBUG_INFO
|
||||
BOOTCFLAGS += -g
|
||||
endif
|
||||
|
||||
ifeq ($(call cc-option-yn, -fstack-protector),y)
|
||||
BOOTCFLAGS += -fno-stack-protector
|
||||
endif
|
||||
|
||||
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj)
|
||||
|
||||
DTC_FLAGS ?= -p 1024
|
||||
|
||||
$(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
|
||||
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
|
||||
|
||||
|
||||
zlib := inffast.c inflate.c inftrees.c
|
||||
zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
|
||||
zliblinuxheader := zlib.h zconf.h zutil.h
|
||||
|
||||
$(addprefix $(obj)/,$(zlib) cuboot-c2k.o gunzip_util.o main.o): \
|
||||
$(addprefix $(obj)/,$(zliblinuxheader)) $(addprefix $(obj)/,$(zlibheader))
|
||||
|
||||
libfdt := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
|
||||
libfdtheader := fdt.h libfdt.h libfdt_internal.h
|
||||
|
||||
$(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o): \
|
||||
$(addprefix $(obj)/,$(libfdtheader))
|
||||
|
||||
src-wlib-y := string.S crt0.S crtsavres.S stdio.c main.c \
|
||||
$(libfdt) libfdt-wrapper.c \
|
||||
ns16550.c serial.c simple_alloc.c div64.S util.S \
|
||||
gunzip_util.c elf_util.c $(zlib) devtree.c stdlib.c \
|
||||
oflib.c ofconsole.c cuboot.c mpsc.c cpm-serial.c \
|
||||
uartlite.c mpc52xx-psc.c
|
||||
src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
|
||||
src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
|
||||
src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c fsl-soc.c
|
||||
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
|
||||
src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c fsl-soc.c
|
||||
|
||||
src-plat-y := of.c epapr.c
|
||||
src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
|
||||
treeboot-walnut.c cuboot-acadia.c \
|
||||
cuboot-kilauea.c simpleboot.c \
|
||||
virtex405-head.S virtex.c
|
||||
src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
|
||||
cuboot-bamboo.c cuboot-sam440ep.c \
|
||||
cuboot-sequoia.c cuboot-rainier.c \
|
||||
cuboot-taishan.c cuboot-katmai.c \
|
||||
cuboot-warp.c cuboot-yosemite.c \
|
||||
treeboot-iss4xx.c treeboot-currituck.c \
|
||||
treeboot-akebono.c \
|
||||
simpleboot.c fixed-head.S virtex.c
|
||||
src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
|
||||
src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
|
||||
src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
|
||||
src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
|
||||
src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
|
||||
src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
|
||||
cuboot-c2k.c gamecube-head.S \
|
||||
gamecube.c wii-head.S wii.c holly.c \
|
||||
fixed-head.S mvme5100.c
|
||||
src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
|
||||
src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
|
||||
src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c epapr-wrapper.c
|
||||
src-plat-$(CONFIG_PPC_PSERIES) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S
|
||||
src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S
|
||||
|
||||
src-wlib := $(sort $(src-wlib-y))
|
||||
src-plat := $(sort $(src-plat-y))
|
||||
src-boot := $(src-wlib) $(src-plat) empty.c
|
||||
|
||||
src-boot := $(addprefix $(obj)/, $(src-boot))
|
||||
obj-boot := $(addsuffix .o, $(basename $(src-boot)))
|
||||
obj-wlib := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-wlib))))
|
||||
obj-plat := $(addsuffix .o, $(basename $(addprefix $(obj)/, $(src-plat))))
|
||||
obj-plat: $(libfdt)
|
||||
|
||||
quiet_cmd_copy_zlib = COPY $@
|
||||
cmd_copy_zlib = sed "s@__used@@;s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
|
||||
|
||||
quiet_cmd_copy_zlibheader = COPY $@
|
||||
cmd_copy_zlibheader = sed "s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
|
||||
# stddef.h for NULL
|
||||
quiet_cmd_copy_zliblinuxheader = COPY $@
|
||||
cmd_copy_zliblinuxheader = sed "s@<linux/string.h>@\"string.h\"@;s@<linux/kernel.h>@<stddef.h>@;s@<linux/\([^>]*\).*@\"\1\"@" $< > $@
|
||||
|
||||
$(addprefix $(obj)/,$(zlib)): $(obj)/%: $(srctree)/lib/zlib_inflate/%
|
||||
$(call cmd,copy_zlib)
|
||||
|
||||
$(addprefix $(obj)/,$(zlibheader)): $(obj)/%: $(srctree)/lib/zlib_inflate/%
|
||||
$(call cmd,copy_zlibheader)
|
||||
|
||||
$(addprefix $(obj)/,$(zliblinuxheader)): $(obj)/%: $(srctree)/include/linux/%
|
||||
$(call cmd,copy_zliblinuxheader)
|
||||
|
||||
quiet_cmd_copy_libfdt = COPY $@
|
||||
cmd_copy_libfdt = cp $< $@
|
||||
|
||||
$(addprefix $(obj)/,$(libfdt) $(libfdtheader)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/%
|
||||
$(call cmd,copy_libfdt)
|
||||
|
||||
$(obj)/empty.c:
|
||||
@touch $@
|
||||
|
||||
$(obj)/zImage.lds: $(obj)/%: $(srctree)/$(src)/%.S
|
||||
$(CROSS32CC) $(cpp_flags) -E -Wp,-MD,$(depfile) -P -Upowerpc \
|
||||
-D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
|
||||
|
||||
$(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds : $(obj)/%: $(srctree)/$(src)/%.S
|
||||
@cp $< $@
|
||||
|
||||
clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \
|
||||
$(libfdt) $(libfdtheader) \
|
||||
empty.c zImage.coff.lds zImage.ps3.lds zImage.lds
|
||||
|
||||
quiet_cmd_bootcc = BOOTCC $@
|
||||
cmd_bootcc = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTCFLAGS) -c -o $@ $<
|
||||
|
||||
quiet_cmd_bootas = BOOTAS $@
|
||||
cmd_bootas = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTAFLAGS) -c -o $@ $<
|
||||
|
||||
quiet_cmd_bootar = BOOTAR $@
|
||||
cmd_bootar = $(CROSS32AR) -cr$(KBUILD_ARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
|
||||
|
||||
$(obj-libfdt): $(obj)/%.o: $(srctree)/scripts/dtc/libfdt/%.c FORCE
|
||||
$(call if_changed_dep,bootcc)
|
||||
$(patsubst %.c,%.o, $(filter %.c, $(src-boot))): %.o: %.c FORCE
|
||||
$(Q)mkdir -p $(dir $@)
|
||||
$(call if_changed_dep,bootcc)
|
||||
$(patsubst %.S,%.o, $(filter %.S, $(src-boot))): %.o: %.S FORCE
|
||||
$(Q)mkdir -p $(dir $@)
|
||||
$(call if_changed_dep,bootas)
|
||||
|
||||
$(obj)/wrapper.a: $(obj-wlib) FORCE
|
||||
$(call if_changed,bootar)
|
||||
|
||||
hostprogs-y := addnote hack-coff mktree
|
||||
|
||||
targets += $(patsubst $(obj)/%,%,$(obj-boot) wrapper.a)
|
||||
extra-y := $(obj)/wrapper.a $(obj-plat) $(obj)/empty.o \
|
||||
$(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds
|
||||
|
||||
dtstree := $(srctree)/$(src)/dts
|
||||
|
||||
wrapper :=$(srctree)/$(src)/wrapper
|
||||
wrapperbits := $(extra-y) $(addprefix $(obj)/,addnote hack-coff mktree) \
|
||||
$(wrapper) FORCE
|
||||
|
||||
#############
|
||||
# Bits for building various flavours of zImage
|
||||
|
||||
ifneq ($(CROSS32_COMPILE),)
|
||||
CROSSWRAP := -C "$(CROSS32_COMPILE)"
|
||||
else
|
||||
ifneq ($(CROSS_COMPILE),)
|
||||
CROSSWRAP := -C "$(CROSS_COMPILE)"
|
||||
endif
|
||||
endif
|
||||
|
||||
# args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd
|
||||
quiet_cmd_wrap = WRAP $@
|
||||
cmd_wrap =$(CONFIG_SHELL) $(wrapper) -c -o $@ -p $2 $(CROSSWRAP) \
|
||||
$(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) vmlinux
|
||||
|
||||
image-$(CONFIG_PPC_PSERIES) += zImage.pseries
|
||||
image-$(CONFIG_PPC_POWERNV) += zImage.pseries
|
||||
image-$(CONFIG_PPC_MAPLE) += zImage.maple
|
||||
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
|
||||
image-$(CONFIG_PPC_PS3) += dtbImage.ps3
|
||||
image-$(CONFIG_PPC_CELLEB) += zImage.pseries
|
||||
image-$(CONFIG_PPC_CELL_QPACE) += zImage.pseries
|
||||
image-$(CONFIG_PPC_CHRP) += zImage.chrp
|
||||
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
|
||||
image-$(CONFIG_PPC_PMAC) += zImage.pmac
|
||||
image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
|
||||
image-$(CONFIG_DEFAULT_UIMAGE) += uImage
|
||||
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
|
||||
|
||||
#
|
||||
# Targets which embed a device tree blob
|
||||
#
|
||||
# Theses are default targets to build images which embed device tree blobs.
|
||||
# They are only required on boards which do not have FDT support in firmware.
|
||||
# Boards with newish u-boot firmware can use the uImage target above
|
||||
#
|
||||
|
||||
# Board ports in arch/powerpc/platform/40x/Kconfig
|
||||
image-$(CONFIG_EP405) += dtbImage.ep405
|
||||
image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
|
||||
image-$(CONFIG_WALNUT) += treeImage.walnut
|
||||
image-$(CONFIG_ACADIA) += cuImage.acadia
|
||||
image-$(CONFIG_OBS600) += uImage.obs600
|
||||
|
||||
# Board ports in arch/powerpc/platform/44x/Kconfig
|
||||
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
|
||||
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
|
||||
image-$(CONFIG_SAM440EP) += cuImage.sam440ep
|
||||
image-$(CONFIG_SEQUOIA) += cuImage.sequoia
|
||||
image-$(CONFIG_RAINIER) += cuImage.rainier
|
||||
image-$(CONFIG_TAISHAN) += cuImage.taishan
|
||||
image-$(CONFIG_KATMAI) += cuImage.katmai
|
||||
image-$(CONFIG_WARP) += cuImage.warp
|
||||
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
|
||||
image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
|
||||
treeImage.iss4xx-mpic
|
||||
image-$(CONFIG_CURRITUCK) += treeImage.currituck
|
||||
image-$(CONFIG_AKEBONO) += treeImage.akebono
|
||||
|
||||
# Board ports in arch/powerpc/platform/8xx/Kconfig
|
||||
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
|
||||
image-$(CONFIG_MPC885ADS) += cuImage.mpc885ads
|
||||
image-$(CONFIG_PPC_EP88XC) += dtbImage.ep88xc
|
||||
image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
|
||||
dtbImage.adder875-redboot
|
||||
|
||||
# Board ports in arch/powerpc/platform/52xx/Kconfig
|
||||
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
|
||||
image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
|
||||
image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
|
||||
|
||||
# Board ports in arch/powerpc/platform/82xx/Kconfig
|
||||
image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
|
||||
image-$(CONFIG_PQ2FADS) += cuImage.pq2fads
|
||||
image-$(CONFIG_EP8248E) += dtbImage.ep8248e
|
||||
|
||||
# Board ports in arch/powerpc/platform/83xx/Kconfig
|
||||
image-$(CONFIG_MPC832x_MDS) += cuImage.mpc832x_mds
|
||||
image-$(CONFIG_MPC832x_RDB) += cuImage.mpc832x_rdb
|
||||
image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \
|
||||
cuImage.mpc8349emitxgp
|
||||
image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
|
||||
image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
|
||||
image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
|
||||
|
||||
# Board ports in arch/powerpc/platform/85xx/Kconfig
|
||||
image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
|
||||
image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads
|
||||
image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \
|
||||
cuImage.mpc8548cds_32b \
|
||||
cuImage.mpc8555cds
|
||||
image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds
|
||||
image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \
|
||||
cuImage.mpc8572ds
|
||||
image-$(CONFIG_TQM8540) += cuImage.tqm8540
|
||||
image-$(CONFIG_TQM8541) += cuImage.tqm8541
|
||||
image-$(CONFIG_TQM8548) += cuImage.tqm8548
|
||||
image-$(CONFIG_TQM8555) += cuImage.tqm8555
|
||||
image-$(CONFIG_TQM8560) += cuImage.tqm8560
|
||||
image-$(CONFIG_SBC8548) += cuImage.sbc8548
|
||||
image-$(CONFIG_KSI8560) += cuImage.ksi8560
|
||||
|
||||
# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
|
||||
image-$(CONFIG_STORCENTER) += cuImage.storcenter
|
||||
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
|
||||
image-$(CONFIG_PPC_C2K) += cuImage.c2k
|
||||
image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
|
||||
image-$(CONFIG_WII) += dtbImage.wii
|
||||
image-$(CONFIG_MVME5100) += dtbImage.mvme5100
|
||||
|
||||
# Board port in arch/powerpc/platform/amigaone/Kconfig
|
||||
image-$(CONFIG_AMIGAONE) += cuImage.amigaone
|
||||
|
||||
# For 32-bit powermacs, build the COFF and miboot images
|
||||
# as well as the ELF images.
|
||||
ifeq ($(CONFIG_PPC32),y)
|
||||
image-$(CONFIG_PPC_PMAC) += zImage.coff zImage.miboot
|
||||
endif
|
||||
|
||||
# Allow extra targets to be added to the defconfig
|
||||
image-y += $(subst ",,$(CONFIG_EXTRA_TARGETS))
|
||||
|
||||
initrd- := $(patsubst zImage%, zImage.initrd%, $(image-n) $(image-))
|
||||
initrd-y := $(patsubst zImage%, zImage.initrd%, \
|
||||
$(patsubst dtbImage%, dtbImage.initrd%, \
|
||||
$(patsubst simpleImage%, simpleImage.initrd%, \
|
||||
$(patsubst treeImage%, treeImage.initrd%, $(image-y)))))
|
||||
initrd-y := $(filter-out $(image-y), $(initrd-y))
|
||||
targets += $(image-y) $(initrd-y)
|
||||
|
||||
$(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
|
||||
|
||||
# Don't put the ramdisk on the pattern rule; when its missing make will try
|
||||
# the pattern rule with less dependencies that also matches (even with the
|
||||
# hard dependency listed).
|
||||
$(obj)/zImage.initrd.%: vmlinux $(wrapperbits)
|
||||
$(call if_changed,wrap,$*,,,$(obj)/ramdisk.image.gz)
|
||||
|
||||
$(addprefix $(obj)/, $(sort $(filter zImage.%, $(image-y)))): vmlinux $(wrapperbits)
|
||||
$(call if_changed,wrap,$(subst $(obj)/zImage.,,$@))
|
||||
|
||||
# dtbImage% - a dtbImage is a zImage with an embedded device tree blob
|
||||
$(obj)/dtbImage.initrd.%: vmlinux $(wrapperbits) $(obj)/%.dtb
|
||||
$(call if_changed,wrap,$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
|
||||
|
||||
$(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
|
||||
$(call if_changed,wrap,$*,,$(obj)/$*.dtb)
|
||||
|
||||
# This cannot be in the root of $(src) as the zImage rule always adds a $(obj)
|
||||
# prefix
|
||||
$(obj)/vmlinux.strip: vmlinux
|
||||
$(STRIP) -s -R .comment $< -o $@
|
||||
|
||||
$(obj)/uImage: vmlinux $(wrapperbits)
|
||||
$(call if_changed,wrap,uboot)
|
||||
|
||||
$(obj)/uImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
|
||||
|
||||
$(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
|
||||
|
||||
$(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
|
||||
|
||||
$(obj)/cuImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb)
|
||||
|
||||
$(obj)/simpleImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
|
||||
|
||||
$(obj)/simpleImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,simpleboot-$*,,$(obj)/$*.dtb)
|
||||
|
||||
$(obj)/treeImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
|
||||
|
||||
$(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
|
||||
$(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
|
||||
|
||||
# Rule to build device tree blobs
|
||||
$(obj)/%.dtb: $(src)/dts/%.dts FORCE
|
||||
$(call if_changed_dep,dtc)
|
||||
|
||||
# If there isn't a platform selected then just strip the vmlinux.
|
||||
ifeq (,$(image-y))
|
||||
image-y := vmlinux.strip
|
||||
endif
|
||||
|
||||
$(obj)/zImage: $(addprefix $(obj)/, $(image-y))
|
||||
@rm -f $@; ln $< $@
|
||||
$(obj)/zImage.initrd: $(addprefix $(obj)/, $(initrd-y))
|
||||
@rm -f $@; ln $< $@
|
||||
|
||||
# Only install the vmlinux
|
||||
install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
|
||||
sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)"
|
||||
|
||||
# Install the vmlinux and other built boot targets.
|
||||
zInstall: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
|
||||
sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $^
|
||||
|
||||
# anything not in $(targets)
|
||||
clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
|
||||
zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
|
||||
zImage.miboot zImage.pmac zImage.pseries \
|
||||
zImage.maple simpleImage.* otheros.bld *.dtb
|
||||
|
||||
# clean up files cached by wrapper
|
||||
clean-kernel := vmlinux.strip vmlinux.bin
|
||||
clean-kernel += $(addsuffix .gz,$(clean-kernel))
|
||||
# If not absolute clean-files are relative to $(obj).
|
||||
clean-files += $(addprefix $(objtree)/, $(clean-kernel))
|
||||
|
||||
WRAPPER_OBJDIR := /usr/lib/kernel-wrapper
|
||||
WRAPPER_DTSDIR := /usr/lib/kernel-wrapper/dts
|
||||
WRAPPER_BINDIR := /usr/sbin
|
||||
INSTALL := install
|
||||
|
||||
extra-installed := $(patsubst $(obj)/%, $(DESTDIR)$(WRAPPER_OBJDIR)/%, $(extra-y))
|
||||
hostprogs-installed := $(patsubst %, $(DESTDIR)$(WRAPPER_BINDIR)/%, $(hostprogs-y))
|
||||
wrapper-installed := $(DESTDIR)$(WRAPPER_BINDIR)/wrapper
|
||||
dts-installed := $(patsubst $(dtstree)/%, $(DESTDIR)$(WRAPPER_DTSDIR)/%, $(wildcard $(dtstree)/*.dts))
|
||||
|
||||
all-installed := $(extra-installed) $(hostprogs-installed) $(wrapper-installed) $(dts-installed)
|
||||
|
||||
quiet_cmd_mkdir = MKDIR $(patsubst $(INSTALL_HDR_PATH)/%,%,$@)
|
||||
cmd_mkdir = mkdir -p $@
|
||||
|
||||
quiet_cmd_install = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_OBJDIR)/%,%,$@)
|
||||
cmd_install = $(INSTALL) -m0644 $(patsubst $(DESTDIR)$(WRAPPER_OBJDIR)/%,$(obj)/%,$@) $@
|
||||
|
||||
quiet_cmd_install_dts = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_DTSDIR)/%,dts/%,$@)
|
||||
cmd_install_dts = $(INSTALL) -m0644 $(patsubst $(DESTDIR)$(WRAPPER_DTSDIR)/%,$(srctree)/$(obj)/dts/%,$@) $@
|
||||
|
||||
quiet_cmd_install_exe = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,%,$@)
|
||||
cmd_install_exe = $(INSTALL) -m0755 $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,$(obj)/%,$@) $@
|
||||
|
||||
quiet_cmd_install_wrapper = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,%,$@)
|
||||
cmd_install_wrapper = $(INSTALL) -m0755 $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,$(srctree)/$(obj)/%,$@) $@ ;\
|
||||
sed -i $@ -e 's%^object=.*%object=$(WRAPPER_OBJDIR)%' \
|
||||
-e 's%^objbin=.*%objbin=$(WRAPPER_BINDIR)%' \
|
||||
|
||||
|
||||
$(DESTDIR)$(WRAPPER_OBJDIR) $(DESTDIR)$(WRAPPER_DTSDIR) $(DESTDIR)$(WRAPPER_BINDIR):
|
||||
$(call cmd,mkdir)
|
||||
|
||||
$(extra-installed) : $(DESTDIR)$(WRAPPER_OBJDIR)/% : $(obj)/% | $(DESTDIR)$(WRAPPER_OBJDIR)
|
||||
$(call cmd,install)
|
||||
|
||||
$(hostprogs-installed) : $(DESTDIR)$(WRAPPER_BINDIR)/% : $(obj)/% | $(DESTDIR)$(WRAPPER_BINDIR)
|
||||
$(call cmd,install_exe)
|
||||
|
||||
$(dts-installed) : $(DESTDIR)$(WRAPPER_DTSDIR)/% : $(srctree)/$(obj)/dts/% | $(DESTDIR)$(WRAPPER_DTSDIR)
|
||||
$(call cmd,install_dts)
|
||||
|
||||
$(wrapper-installed): $(DESTDIR)$(WRAPPER_BINDIR) $(srctree)/$(obj)/wrapper | $(DESTDIR)$(WRAPPER_BINDIR)
|
||||
$(call cmd,install_wrapper)
|
||||
|
||||
$(obj)/bootwrapper_install: $(all-installed)
|
||||
11
arch/powerpc/boot/README
Normal file
11
arch/powerpc/boot/README
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
|
||||
To extract the kernel vmlinux, System.map, .config or initrd from the zImage binary:
|
||||
|
||||
objcopy -j .kernel:vmlinux -O binary zImage vmlinux.gz
|
||||
objcopy -j .kernel:System.map -O binary zImage System.map.gz
|
||||
objcopy -j .kernel:.config -O binary zImage config.gz
|
||||
objcopy -j .kernel:initrd -O binary zImage.initrd initrd.gz
|
||||
|
||||
|
||||
Peter
|
||||
|
||||
247
arch/powerpc/boot/addnote.c
Normal file
247
arch/powerpc/boot/addnote.c
Normal file
|
|
@ -0,0 +1,247 @@
|
|||
/*
|
||||
* Program to hack in a PT_NOTE program header entry in an ELF file.
|
||||
* This is needed for OF on RS/6000s to load an image correctly.
|
||||
* Note that OF needs a program header entry for the note, not an
|
||||
* ELF section.
|
||||
*
|
||||
* Copyright 2000 Paul Mackerras.
|
||||
*
|
||||
* Adapted for 64 bit little endian images by Andrew Tauferner.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* Usage: addnote zImage
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <fcntl.h>
|
||||
#include <unistd.h>
|
||||
#include <string.h>
|
||||
|
||||
/* CHRP note section */
|
||||
static const char arch[] = "PowerPC";
|
||||
|
||||
#define N_DESCR 6
|
||||
unsigned int descr[N_DESCR] = {
|
||||
0xffffffff, /* real-mode = true */
|
||||
0x02000000, /* real-base, i.e. where we expect OF to be */
|
||||
0xffffffff, /* real-size */
|
||||
0xffffffff, /* virt-base */
|
||||
0xffffffff, /* virt-size */
|
||||
0x4000, /* load-base */
|
||||
};
|
||||
|
||||
/* RPA note section */
|
||||
static const char rpaname[] = "IBM,RPA-Client-Config";
|
||||
|
||||
/*
|
||||
* Note: setting ignore_my_client_config *should* mean that OF ignores
|
||||
* all the other fields, but there is a firmware bug which means that
|
||||
* it looks at the splpar field at least. So these values need to be
|
||||
* reasonable.
|
||||
*/
|
||||
#define N_RPA_DESCR 8
|
||||
unsigned int rpanote[N_RPA_DESCR] = {
|
||||
0, /* lparaffinity */
|
||||
64, /* min_rmo_size */
|
||||
0, /* min_rmo_percent */
|
||||
40, /* max_pft_size */
|
||||
1, /* splpar */
|
||||
-1, /* min_load */
|
||||
0, /* new_mem_def */
|
||||
1, /* ignore_my_client_config */
|
||||
};
|
||||
|
||||
#define ROUNDUP(len) (((len) + 3) & ~3)
|
||||
|
||||
unsigned char buf[1024];
|
||||
#define ELFDATA2LSB 1
|
||||
#define ELFDATA2MSB 2
|
||||
static int e_data = ELFDATA2MSB;
|
||||
#define ELFCLASS32 1
|
||||
#define ELFCLASS64 2
|
||||
static int e_class = ELFCLASS32;
|
||||
|
||||
#define GET_16BE(off) ((buf[off] << 8) + (buf[(off)+1]))
|
||||
#define GET_32BE(off) ((GET_16BE(off) << 16U) + GET_16BE((off)+2U))
|
||||
#define GET_64BE(off) ((((unsigned long long)GET_32BE(off)) << 32ULL) + \
|
||||
((unsigned long long)GET_32BE((off)+4ULL)))
|
||||
#define PUT_16BE(off, v)(buf[off] = ((v) >> 8) & 0xff, \
|
||||
buf[(off) + 1] = (v) & 0xff)
|
||||
#define PUT_32BE(off, v)(PUT_16BE((off), (v) >> 16L), PUT_16BE((off) + 2, (v)))
|
||||
#define PUT_64BE(off, v)((PUT_32BE((off), (v) >> 32L), \
|
||||
PUT_32BE((off) + 4, (v))))
|
||||
|
||||
#define GET_16LE(off) ((buf[off]) + (buf[(off)+1] << 8))
|
||||
#define GET_32LE(off) (GET_16LE(off) + (GET_16LE((off)+2U) << 16U))
|
||||
#define GET_64LE(off) ((unsigned long long)GET_32LE(off) + \
|
||||
(((unsigned long long)GET_32LE((off)+4ULL)) << 32ULL))
|
||||
#define PUT_16LE(off, v) (buf[off] = (v) & 0xff, \
|
||||
buf[(off) + 1] = ((v) >> 8) & 0xff)
|
||||
#define PUT_32LE(off, v) (PUT_16LE((off), (v)), PUT_16LE((off) + 2, (v) >> 16L))
|
||||
#define PUT_64LE(off, v) (PUT_32LE((off), (v)), PUT_32LE((off) + 4, (v) >> 32L))
|
||||
|
||||
#define GET_16(off) (e_data == ELFDATA2MSB ? GET_16BE(off) : GET_16LE(off))
|
||||
#define GET_32(off) (e_data == ELFDATA2MSB ? GET_32BE(off) : GET_32LE(off))
|
||||
#define GET_64(off) (e_data == ELFDATA2MSB ? GET_64BE(off) : GET_64LE(off))
|
||||
#define PUT_16(off, v) (e_data == ELFDATA2MSB ? PUT_16BE(off, v) : \
|
||||
PUT_16LE(off, v))
|
||||
#define PUT_32(off, v) (e_data == ELFDATA2MSB ? PUT_32BE(off, v) : \
|
||||
PUT_32LE(off, v))
|
||||
#define PUT_64(off, v) (e_data == ELFDATA2MSB ? PUT_64BE(off, v) : \
|
||||
PUT_64LE(off, v))
|
||||
|
||||
/* Structure of an ELF file */
|
||||
#define E_IDENT 0 /* ELF header */
|
||||
#define E_PHOFF (e_class == ELFCLASS32 ? 28 : 32)
|
||||
#define E_PHENTSIZE (e_class == ELFCLASS32 ? 42 : 54)
|
||||
#define E_PHNUM (e_class == ELFCLASS32 ? 44 : 56)
|
||||
#define E_HSIZE (e_class == ELFCLASS32 ? 52 : 64)
|
||||
|
||||
#define EI_MAGIC 0 /* offsets in E_IDENT area */
|
||||
#define EI_CLASS 4
|
||||
#define EI_DATA 5
|
||||
|
||||
#define PH_TYPE 0 /* ELF program header */
|
||||
#define PH_OFFSET (e_class == ELFCLASS32 ? 4 : 8)
|
||||
#define PH_FILESZ (e_class == ELFCLASS32 ? 16 : 32)
|
||||
#define PH_HSIZE (e_class == ELFCLASS32 ? 32 : 56)
|
||||
|
||||
#define PT_NOTE 4 /* Program header type = note */
|
||||
|
||||
|
||||
unsigned char elf_magic[4] = { 0x7f, 'E', 'L', 'F' };
|
||||
|
||||
int
|
||||
main(int ac, char **av)
|
||||
{
|
||||
int fd, n, i;
|
||||
unsigned long ph, ps, np;
|
||||
long nnote, nnote2, ns;
|
||||
|
||||
if (ac != 2) {
|
||||
fprintf(stderr, "Usage: %s elf-file\n", av[0]);
|
||||
exit(1);
|
||||
}
|
||||
fd = open(av[1], O_RDWR);
|
||||
if (fd < 0) {
|
||||
perror(av[1]);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
nnote = 12 + ROUNDUP(strlen(arch) + 1) + sizeof(descr);
|
||||
nnote2 = 12 + ROUNDUP(strlen(rpaname) + 1) + sizeof(rpanote);
|
||||
|
||||
n = read(fd, buf, sizeof(buf));
|
||||
if (n < 0) {
|
||||
perror("read");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
if (memcmp(&buf[E_IDENT+EI_MAGIC], elf_magic, 4) != 0)
|
||||
goto notelf;
|
||||
e_class = buf[E_IDENT+EI_CLASS];
|
||||
if (e_class != ELFCLASS32 && e_class != ELFCLASS64)
|
||||
goto notelf;
|
||||
e_data = buf[E_IDENT+EI_DATA];
|
||||
if (e_data != ELFDATA2MSB && e_data != ELFDATA2LSB)
|
||||
goto notelf;
|
||||
if (n < E_HSIZE)
|
||||
goto notelf;
|
||||
|
||||
ph = (e_class == ELFCLASS32 ? GET_32(E_PHOFF) : GET_64(E_PHOFF));
|
||||
ps = GET_16(E_PHENTSIZE);
|
||||
np = GET_16(E_PHNUM);
|
||||
if (ph < E_HSIZE || ps < PH_HSIZE || np < 1)
|
||||
goto notelf;
|
||||
if (ph + (np + 2) * ps + nnote + nnote2 > n)
|
||||
goto nospace;
|
||||
|
||||
for (i = 0; i < np; ++i) {
|
||||
if (GET_32(ph + PH_TYPE) == PT_NOTE) {
|
||||
fprintf(stderr, "%s already has a note entry\n",
|
||||
av[1]);
|
||||
exit(0);
|
||||
}
|
||||
ph += ps;
|
||||
}
|
||||
|
||||
/* XXX check that the area we want to use is all zeroes */
|
||||
for (i = 0; i < 2 * ps + nnote + nnote2; ++i)
|
||||
if (buf[ph + i] != 0)
|
||||
goto nospace;
|
||||
|
||||
/* fill in the program header entry */
|
||||
ns = ph + 2 * ps;
|
||||
PUT_32(ph + PH_TYPE, PT_NOTE);
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_OFFSET, ns);
|
||||
else
|
||||
PUT_64(ph + PH_OFFSET, ns);
|
||||
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_FILESZ, nnote);
|
||||
else
|
||||
PUT_64(ph + PH_FILESZ, nnote);
|
||||
|
||||
/* fill in the note area we point to */
|
||||
/* XXX we should probably make this a proper section */
|
||||
PUT_32(ns, strlen(arch) + 1);
|
||||
PUT_32(ns + 4, N_DESCR * 4);
|
||||
PUT_32(ns + 8, 0x1275);
|
||||
strcpy((char *) &buf[ns + 12], arch);
|
||||
ns += 12 + strlen(arch) + 1;
|
||||
for (i = 0; i < N_DESCR; ++i, ns += 4)
|
||||
PUT_32BE(ns, descr[i]);
|
||||
|
||||
/* fill in the second program header entry and the RPA note area */
|
||||
ph += ps;
|
||||
PUT_32(ph + PH_TYPE, PT_NOTE);
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_OFFSET, ns);
|
||||
else
|
||||
PUT_64(ph + PH_OFFSET, ns);
|
||||
|
||||
if (e_class == ELFCLASS32)
|
||||
PUT_32(ph + PH_FILESZ, nnote);
|
||||
else
|
||||
PUT_64(ph + PH_FILESZ, nnote2);
|
||||
|
||||
/* fill in the note area we point to */
|
||||
PUT_32(ns, strlen(rpaname) + 1);
|
||||
PUT_32(ns + 4, sizeof(rpanote));
|
||||
PUT_32(ns + 8, 0x12759999);
|
||||
strcpy((char *) &buf[ns + 12], rpaname);
|
||||
ns += 12 + ROUNDUP(strlen(rpaname) + 1);
|
||||
for (i = 0; i < N_RPA_DESCR; ++i, ns += 4)
|
||||
PUT_32BE(ns, rpanote[i]);
|
||||
|
||||
/* Update the number of program headers */
|
||||
PUT_16(E_PHNUM, np + 2);
|
||||
|
||||
/* write back */
|
||||
lseek(fd, (long) 0, SEEK_SET);
|
||||
i = write(fd, buf, n);
|
||||
if (i < 0) {
|
||||
perror("write");
|
||||
exit(1);
|
||||
}
|
||||
if (i < n) {
|
||||
fprintf(stderr, "%s: write truncated\n", av[1]);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
exit(0);
|
||||
|
||||
notelf:
|
||||
fprintf(stderr, "%s does not appear to be an ELF file\n", av[1]);
|
||||
exit(1);
|
||||
|
||||
nospace:
|
||||
fprintf(stderr, "sorry, I can't find space in %s to put the note\n",
|
||||
av[1]);
|
||||
exit(1);
|
||||
}
|
||||
48
arch/powerpc/boot/bamboo.c
Normal file
48
arch/powerpc/boot/bamboo.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright IBM Corporation, 2007
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Based on ebony wrapper:
|
||||
* Copyright 2007 David Gibson, IBM Corporation.
|
||||
*
|
||||
* Clocking code based on code by:
|
||||
* Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2 of the License
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "elf.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "page.h"
|
||||
#include "ops.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
|
||||
static u8 *bamboo_mac0, *bamboo_mac1;
|
||||
|
||||
static void bamboo_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bamboo_mac0);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bamboo_mac1);
|
||||
}
|
||||
|
||||
void bamboo_init(void *mac0, void *mac1)
|
||||
{
|
||||
platform_ops.fixups = bamboo_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
bamboo_mac0 = mac0;
|
||||
bamboo_mac1 = mac1;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
294
arch/powerpc/boot/cpm-serial.c
Normal file
294
arch/powerpc/boot/cpm-serial.c
Normal file
|
|
@ -0,0 +1,294 @@
|
|||
/*
|
||||
* CPM serial console support.
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* It is assumed that the firmware (or the platform file) has already set
|
||||
* up the port.
|
||||
*/
|
||||
|
||||
#include "types.h"
|
||||
#include "io.h"
|
||||
#include "ops.h"
|
||||
#include "page.h"
|
||||
|
||||
struct cpm_scc {
|
||||
u32 gsmrl;
|
||||
u32 gsmrh;
|
||||
u16 psmr;
|
||||
u8 res1[2];
|
||||
u16 todr;
|
||||
u16 dsr;
|
||||
u16 scce;
|
||||
u8 res2[2];
|
||||
u16 sccm;
|
||||
u8 res3;
|
||||
u8 sccs;
|
||||
u8 res4[8];
|
||||
};
|
||||
|
||||
struct cpm_smc {
|
||||
u8 res1[2];
|
||||
u16 smcmr;
|
||||
u8 res2[2];
|
||||
u8 smce;
|
||||
u8 res3[3];
|
||||
u8 smcm;
|
||||
u8 res4[5];
|
||||
};
|
||||
|
||||
struct cpm_param {
|
||||
u16 rbase;
|
||||
u16 tbase;
|
||||
u8 rfcr;
|
||||
u8 tfcr;
|
||||
u16 mrblr;
|
||||
u32 rstate;
|
||||
u8 res1[4];
|
||||
u16 rbptr;
|
||||
u8 res2[6];
|
||||
u32 tstate;
|
||||
u8 res3[4];
|
||||
u16 tbptr;
|
||||
u8 res4[6];
|
||||
u16 maxidl;
|
||||
u16 idlc;
|
||||
u16 brkln;
|
||||
u16 brkec;
|
||||
u16 brkcr;
|
||||
u16 rmask;
|
||||
u8 res5[4];
|
||||
};
|
||||
|
||||
struct cpm_bd {
|
||||
u16 sc; /* Status and Control */
|
||||
u16 len; /* Data length in buffer */
|
||||
u8 *addr; /* Buffer address in host memory */
|
||||
};
|
||||
|
||||
static void *cpcr;
|
||||
static struct cpm_param *param;
|
||||
static struct cpm_smc *smc;
|
||||
static struct cpm_scc *scc;
|
||||
static struct cpm_bd *tbdf, *rbdf;
|
||||
static u32 cpm_cmd;
|
||||
static void *cbd_addr;
|
||||
static u32 cbd_offset;
|
||||
|
||||
static void (*do_cmd)(int op);
|
||||
static void (*enable_port)(void);
|
||||
static void (*disable_port)(void);
|
||||
|
||||
#define CPM_CMD_STOP_TX 4
|
||||
#define CPM_CMD_RESTART_TX 6
|
||||
#define CPM_CMD_INIT_RX_TX 0
|
||||
|
||||
static void cpm1_cmd(int op)
|
||||
{
|
||||
while (in_be16(cpcr) & 1)
|
||||
;
|
||||
|
||||
out_be16(cpcr, (op << 8) | cpm_cmd | 1);
|
||||
|
||||
while (in_be16(cpcr) & 1)
|
||||
;
|
||||
}
|
||||
|
||||
static void cpm2_cmd(int op)
|
||||
{
|
||||
while (in_be32(cpcr) & 0x10000)
|
||||
;
|
||||
|
||||
out_be32(cpcr, op | cpm_cmd | 0x10000);
|
||||
|
||||
while (in_be32(cpcr) & 0x10000)
|
||||
;
|
||||
}
|
||||
|
||||
static void smc_disable_port(void)
|
||||
{
|
||||
do_cmd(CPM_CMD_STOP_TX);
|
||||
out_be16(&smc->smcmr, in_be16(&smc->smcmr) & ~3);
|
||||
}
|
||||
|
||||
static void scc_disable_port(void)
|
||||
{
|
||||
do_cmd(CPM_CMD_STOP_TX);
|
||||
out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) & ~0x30);
|
||||
}
|
||||
|
||||
static void smc_enable_port(void)
|
||||
{
|
||||
out_be16(&smc->smcmr, in_be16(&smc->smcmr) | 3);
|
||||
do_cmd(CPM_CMD_RESTART_TX);
|
||||
}
|
||||
|
||||
static void scc_enable_port(void)
|
||||
{
|
||||
out_be32(&scc->gsmrl, in_be32(&scc->gsmrl) | 0x30);
|
||||
do_cmd(CPM_CMD_RESTART_TX);
|
||||
}
|
||||
|
||||
static int cpm_serial_open(void)
|
||||
{
|
||||
disable_port();
|
||||
|
||||
out_8(¶m->rfcr, 0x10);
|
||||
out_8(¶m->tfcr, 0x10);
|
||||
out_be16(¶m->mrblr, 1);
|
||||
out_be16(¶m->maxidl, 0);
|
||||
out_be16(¶m->brkec, 0);
|
||||
out_be16(¶m->brkln, 0);
|
||||
out_be16(¶m->brkcr, 0);
|
||||
|
||||
rbdf = cbd_addr;
|
||||
rbdf->addr = (u8 *)rbdf - 1;
|
||||
rbdf->sc = 0xa000;
|
||||
rbdf->len = 1;
|
||||
|
||||
tbdf = rbdf + 1;
|
||||
tbdf->addr = (u8 *)rbdf - 2;
|
||||
tbdf->sc = 0x2000;
|
||||
tbdf->len = 1;
|
||||
|
||||
sync();
|
||||
out_be16(¶m->rbase, cbd_offset);
|
||||
out_be16(¶m->tbase, cbd_offset + sizeof(struct cpm_bd));
|
||||
|
||||
do_cmd(CPM_CMD_INIT_RX_TX);
|
||||
|
||||
enable_port();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cpm_serial_putc(unsigned char c)
|
||||
{
|
||||
while (tbdf->sc & 0x8000)
|
||||
barrier();
|
||||
|
||||
sync();
|
||||
|
||||
tbdf->addr[0] = c;
|
||||
eieio();
|
||||
tbdf->sc |= 0x8000;
|
||||
}
|
||||
|
||||
static unsigned char cpm_serial_tstc(void)
|
||||
{
|
||||
barrier();
|
||||
return !(rbdf->sc & 0x8000);
|
||||
}
|
||||
|
||||
static unsigned char cpm_serial_getc(void)
|
||||
{
|
||||
unsigned char c;
|
||||
|
||||
while (!cpm_serial_tstc())
|
||||
;
|
||||
|
||||
sync();
|
||||
c = rbdf->addr[0];
|
||||
eieio();
|
||||
rbdf->sc |= 0x8000;
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
int cpm_console_init(void *devp, struct serial_console_data *scdp)
|
||||
{
|
||||
void *vreg[2];
|
||||
u32 reg[2];
|
||||
int is_smc = 0, is_cpm2 = 0;
|
||||
void *parent, *muram;
|
||||
void *muram_addr;
|
||||
unsigned long muram_offset, muram_size;
|
||||
|
||||
if (dt_is_compatible(devp, "fsl,cpm1-smc-uart")) {
|
||||
is_smc = 1;
|
||||
} else if (dt_is_compatible(devp, "fsl,cpm2-scc-uart")) {
|
||||
is_cpm2 = 1;
|
||||
} else if (dt_is_compatible(devp, "fsl,cpm2-smc-uart")) {
|
||||
is_cpm2 = 1;
|
||||
is_smc = 1;
|
||||
}
|
||||
|
||||
if (is_smc) {
|
||||
enable_port = smc_enable_port;
|
||||
disable_port = smc_disable_port;
|
||||
} else {
|
||||
enable_port = scc_enable_port;
|
||||
disable_port = scc_disable_port;
|
||||
}
|
||||
|
||||
if (is_cpm2)
|
||||
do_cmd = cpm2_cmd;
|
||||
else
|
||||
do_cmd = cpm1_cmd;
|
||||
|
||||
if (getprop(devp, "fsl,cpm-command", &cpm_cmd, 4) < 4)
|
||||
return -1;
|
||||
|
||||
if (dt_get_virtual_reg(devp, vreg, 2) < 2)
|
||||
return -1;
|
||||
|
||||
if (is_smc)
|
||||
smc = vreg[0];
|
||||
else
|
||||
scc = vreg[0];
|
||||
|
||||
param = vreg[1];
|
||||
|
||||
parent = get_parent(devp);
|
||||
if (!parent)
|
||||
return -1;
|
||||
|
||||
if (dt_get_virtual_reg(parent, &cpcr, 1) < 1)
|
||||
return -1;
|
||||
|
||||
muram = finddevice("/soc/cpm/muram/data");
|
||||
if (!muram)
|
||||
return -1;
|
||||
|
||||
/* For bootwrapper-compatible device trees, we assume that the first
|
||||
* entry has at least 128 bytes, and that #address-cells/#data-cells
|
||||
* is one for both parent and child.
|
||||
*/
|
||||
|
||||
if (dt_get_virtual_reg(muram, &muram_addr, 1) < 1)
|
||||
return -1;
|
||||
|
||||
if (getprop(muram, "reg", reg, 8) < 8)
|
||||
return -1;
|
||||
|
||||
muram_offset = reg[0];
|
||||
muram_size = reg[1];
|
||||
|
||||
/* Store the buffer descriptors at the end of the first muram chunk.
|
||||
* For SMC ports on CPM2-based platforms, relocate the parameter RAM
|
||||
* just before the buffer descriptors.
|
||||
*/
|
||||
|
||||
cbd_offset = muram_offset + muram_size - 2 * sizeof(struct cpm_bd);
|
||||
|
||||
if (is_cpm2 && is_smc) {
|
||||
u16 *smc_base = (u16 *)param;
|
||||
u16 pram_offset;
|
||||
|
||||
pram_offset = cbd_offset - 64;
|
||||
pram_offset = _ALIGN_DOWN(pram_offset, 64);
|
||||
|
||||
disable_port();
|
||||
out_be16(smc_base, pram_offset);
|
||||
param = muram_addr - muram_offset + pram_offset;
|
||||
}
|
||||
|
||||
cbd_addr = muram_addr - muram_offset + cbd_offset;
|
||||
|
||||
scdp->open = cpm_serial_open;
|
||||
scdp->putc = cpm_serial_putc;
|
||||
scdp->getc = cpm_serial_getc;
|
||||
scdp->tstc = cpm_serial_tstc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
300
arch/powerpc/boot/crt0.S
Normal file
300
arch/powerpc/boot/crt0.S
Normal file
|
|
@ -0,0 +1,300 @@
|
|||
/*
|
||||
* Copyright (C) Paul Mackerras 1997.
|
||||
*
|
||||
* Adapted for 64 bit LE PowerPC by Andrew Tauferner
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "ppc_asm.h"
|
||||
|
||||
RELA = 7
|
||||
RELACOUNT = 0x6ffffff9
|
||||
|
||||
.text
|
||||
/* A procedure descriptor used when booting this as a COFF file.
|
||||
* When making COFF, this comes first in the link and we're
|
||||
* linked at 0x500000.
|
||||
*/
|
||||
.globl _zimage_start_opd
|
||||
_zimage_start_opd:
|
||||
.long 0x500000, 0, 0, 0
|
||||
|
||||
#ifdef __powerpc64__
|
||||
.balign 8
|
||||
p_start: .llong _start
|
||||
p_etext: .llong _etext
|
||||
p_bss_start: .llong __bss_start
|
||||
p_end: .llong _end
|
||||
|
||||
p_toc: .llong __toc_start + 0x8000 - p_base
|
||||
p_dyn: .llong __dynamic_start - p_base
|
||||
p_rela: .llong __rela_dyn_start - p_base
|
||||
p_prom: .llong 0
|
||||
.weak _platform_stack_top
|
||||
p_pstack: .llong _platform_stack_top
|
||||
#else
|
||||
p_start: .long _start
|
||||
p_etext: .long _etext
|
||||
p_bss_start: .long __bss_start
|
||||
p_end: .long _end
|
||||
|
||||
.weak _platform_stack_top
|
||||
p_pstack: .long _platform_stack_top
|
||||
#endif
|
||||
|
||||
.weak _zimage_start
|
||||
.globl _zimage_start
|
||||
_zimage_start:
|
||||
.globl _zimage_start_lib
|
||||
_zimage_start_lib:
|
||||
/* Work out the offset between the address we were linked at
|
||||
and the address where we're running. */
|
||||
bl .+4
|
||||
p_base: mflr r10 /* r10 now points to runtime addr of p_base */
|
||||
#ifndef __powerpc64__
|
||||
/* grab the link address of the dynamic section in r11 */
|
||||
addis r11,r10,(_GLOBAL_OFFSET_TABLE_-p_base)@ha
|
||||
lwz r11,(_GLOBAL_OFFSET_TABLE_-p_base)@l(r11)
|
||||
cmpwi r11,0
|
||||
beq 3f /* if not linked -pie */
|
||||
/* get the runtime address of the dynamic section in r12 */
|
||||
.weak __dynamic_start
|
||||
addis r12,r10,(__dynamic_start-p_base)@ha
|
||||
addi r12,r12,(__dynamic_start-p_base)@l
|
||||
subf r11,r11,r12 /* runtime - linktime offset */
|
||||
|
||||
/* The dynamic section contains a series of tagged entries.
|
||||
* We need the RELA and RELACOUNT entries. */
|
||||
li r9,0
|
||||
li r0,0
|
||||
9: lwz r8,0(r12) /* get tag */
|
||||
cmpwi r8,0
|
||||
beq 10f /* end of list */
|
||||
cmpwi r8,RELA
|
||||
bne 11f
|
||||
lwz r9,4(r12) /* get RELA pointer in r9 */
|
||||
b 12f
|
||||
11: addis r8,r8,(-RELACOUNT)@ha
|
||||
cmpwi r8,RELACOUNT@l
|
||||
bne 12f
|
||||
lwz r0,4(r12) /* get RELACOUNT value in r0 */
|
||||
12: addi r12,r12,8
|
||||
b 9b
|
||||
|
||||
/* The relocation section contains a list of relocations.
|
||||
* We now do the R_PPC_RELATIVE ones, which point to words
|
||||
* which need to be initialized with addend + offset.
|
||||
* The R_PPC_RELATIVE ones come first and there are RELACOUNT
|
||||
* of them. */
|
||||
10: /* skip relocation if we don't have both */
|
||||
cmpwi r0,0
|
||||
beq 3f
|
||||
cmpwi r9,0
|
||||
beq 3f
|
||||
|
||||
add r9,r9,r11 /* Relocate RELA pointer */
|
||||
mtctr r0
|
||||
2: lbz r0,4+3(r9) /* ELF32_R_INFO(reloc->r_info) */
|
||||
cmpwi r0,22 /* R_PPC_RELATIVE */
|
||||
bne 3f
|
||||
lwz r12,0(r9) /* reloc->r_offset */
|
||||
lwz r0,8(r9) /* reloc->r_addend */
|
||||
add r0,r0,r11
|
||||
stwx r0,r11,r12
|
||||
addi r9,r9,12
|
||||
bdnz 2b
|
||||
|
||||
/* Do a cache flush for our text, in case the loader didn't */
|
||||
3: lwz r9,p_start-p_base(r10) /* note: these are relocated now */
|
||||
lwz r8,p_etext-p_base(r10)
|
||||
4: dcbf r0,r9
|
||||
icbi r0,r9
|
||||
addi r9,r9,0x20
|
||||
cmplw cr0,r9,r8
|
||||
blt 4b
|
||||
sync
|
||||
isync
|
||||
|
||||
/* Clear the BSS */
|
||||
lwz r9,p_bss_start-p_base(r10)
|
||||
lwz r8,p_end-p_base(r10)
|
||||
li r0,0
|
||||
5: stw r0,0(r9)
|
||||
addi r9,r9,4
|
||||
cmplw cr0,r9,r8
|
||||
blt 5b
|
||||
|
||||
/* Possibly set up a custom stack */
|
||||
lwz r8,p_pstack-p_base(r10)
|
||||
cmpwi r8,0
|
||||
beq 6f
|
||||
lwz r1,0(r8)
|
||||
li r0,0
|
||||
stwu r0,-16(r1) /* establish a stack frame */
|
||||
6:
|
||||
#else /* __powerpc64__ */
|
||||
/* Save the prom pointer at p_prom. */
|
||||
std r5,(p_prom-p_base)(r10)
|
||||
|
||||
/* Set r2 to the TOC. */
|
||||
ld r2,(p_toc-p_base)(r10)
|
||||
add r2,r2,r10
|
||||
|
||||
/* Grab the link address of the dynamic section in r11. */
|
||||
ld r11,-32768(r2)
|
||||
cmpwi r11,0
|
||||
beq 3f /* if not linked -pie then no dynamic section */
|
||||
|
||||
ld r11,(p_dyn-p_base)(r10)
|
||||
add r11,r11,r10
|
||||
ld r9,(p_rela-p_base)(r10)
|
||||
add r9,r9,r10
|
||||
|
||||
li r7,0
|
||||
li r8,0
|
||||
9: ld r6,0(r11) /* get tag */
|
||||
cmpdi r6,0
|
||||
beq 12f /* end of list */
|
||||
cmpdi r6,RELA
|
||||
bne 10f
|
||||
ld r7,8(r11) /* get RELA pointer in r7 */
|
||||
b 11f
|
||||
10: addis r6,r6,(-RELACOUNT)@ha
|
||||
cmpdi r6,RELACOUNT@l
|
||||
bne 11f
|
||||
ld r8,8(r11) /* get RELACOUNT value in r8 */
|
||||
11: addi r11,r11,16
|
||||
b 9b
|
||||
12:
|
||||
cmpdi r7,0 /* check we have both RELA and RELACOUNT */
|
||||
cmpdi cr1,r8,0
|
||||
beq 3f
|
||||
beq cr1,3f
|
||||
|
||||
/* Calcuate the runtime offset. */
|
||||
subf r7,r7,r9
|
||||
|
||||
/* Run through the list of relocations and process the
|
||||
* R_PPC64_RELATIVE ones. */
|
||||
mtctr r8
|
||||
13: ld r0,8(r9) /* ELF64_R_TYPE(reloc->r_info) */
|
||||
cmpdi r0,22 /* R_PPC64_RELATIVE */
|
||||
bne 3f
|
||||
ld r6,0(r9) /* reloc->r_offset */
|
||||
ld r0,16(r9) /* reloc->r_addend */
|
||||
add r0,r0,r7
|
||||
stdx r0,r7,r6
|
||||
addi r9,r9,24
|
||||
bdnz 13b
|
||||
|
||||
/* Do a cache flush for our text, in case the loader didn't */
|
||||
3: ld r9,p_start-p_base(r10) /* note: these are relocated now */
|
||||
ld r8,p_etext-p_base(r10)
|
||||
4: dcbf r0,r9
|
||||
icbi r0,r9
|
||||
addi r9,r9,0x20
|
||||
cmpld cr0,r9,r8
|
||||
blt 4b
|
||||
sync
|
||||
isync
|
||||
|
||||
/* Clear the BSS */
|
||||
ld r9,p_bss_start-p_base(r10)
|
||||
ld r8,p_end-p_base(r10)
|
||||
li r0,0
|
||||
5: std r0,0(r9)
|
||||
addi r9,r9,8
|
||||
cmpld cr0,r9,r8
|
||||
blt 5b
|
||||
|
||||
/* Possibly set up a custom stack */
|
||||
ld r8,p_pstack-p_base(r10)
|
||||
cmpdi r8,0
|
||||
beq 6f
|
||||
ld r1,0(r8)
|
||||
li r0,0
|
||||
stdu r0,-16(r1) /* establish a stack frame */
|
||||
6:
|
||||
#endif /* __powerpc64__ */
|
||||
/* Call platform_init() */
|
||||
bl platform_init
|
||||
|
||||
/* Call start */
|
||||
b start
|
||||
|
||||
#ifdef __powerpc64__
|
||||
|
||||
#define PROM_FRAME_SIZE 512
|
||||
#define SAVE_GPR(n, base) std n,8*(n)(base)
|
||||
#define REST_GPR(n, base) ld n,8*(n)(base)
|
||||
#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
|
||||
#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
|
||||
#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
|
||||
#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
|
||||
#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
|
||||
#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
|
||||
#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
|
||||
#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
|
||||
|
||||
/* prom handles the jump into and return from firmware. The prom args pointer
|
||||
is loaded in r3. */
|
||||
.globl prom
|
||||
prom:
|
||||
mflr r0
|
||||
std r0,16(r1)
|
||||
stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
|
||||
|
||||
SAVE_GPR(2, r1)
|
||||
SAVE_GPR(13, r1)
|
||||
SAVE_8GPRS(14, r1)
|
||||
SAVE_10GPRS(22, r1)
|
||||
mfcr r10
|
||||
std r10,8*32(r1)
|
||||
mfmsr r10
|
||||
std r10,8*33(r1)
|
||||
|
||||
/* remove MSR_LE from msr but keep MSR_SF */
|
||||
mfmsr r10
|
||||
rldicr r10,r10,0,62
|
||||
mtsrr1 r10
|
||||
|
||||
/* Load FW address, set LR to label 1, and jump to FW */
|
||||
bl 0f
|
||||
0: mflr r10
|
||||
addi r11,r10,(1f-0b)
|
||||
mtlr r11
|
||||
|
||||
ld r10,(p_prom-0b)(r10)
|
||||
mtsrr0 r10
|
||||
|
||||
rfid
|
||||
|
||||
1: /* Return from OF */
|
||||
FIXUP_ENDIAN
|
||||
|
||||
/* Restore registers and return. */
|
||||
rldicl r1,r1,0,32
|
||||
|
||||
/* Restore the MSR (back to 64 bits) */
|
||||
ld r10,8*(33)(r1)
|
||||
mtmsr r10
|
||||
isync
|
||||
|
||||
/* Restore other registers */
|
||||
REST_GPR(2, r1)
|
||||
REST_GPR(13, r1)
|
||||
REST_8GPRS(14, r1)
|
||||
REST_10GPRS(22, r1)
|
||||
ld r10,8*32(r1)
|
||||
mtcr r10
|
||||
|
||||
addi r1,r1,PROM_FRAME_SIZE
|
||||
ld r0,16(r1)
|
||||
mtlr r0
|
||||
blr
|
||||
#endif
|
||||
233
arch/powerpc/boot/crtsavres.S
Normal file
233
arch/powerpc/boot/crtsavres.S
Normal file
|
|
@ -0,0 +1,233 @@
|
|||
/*
|
||||
* Special support for eabi and SVR4
|
||||
*
|
||||
* Copyright (C) 1995, 1996, 1998, 2000, 2001 Free Software Foundation, Inc.
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
* Written By Michael Meissner
|
||||
*
|
||||
* Based on gcc/config/rs6000/crtsavres.asm from gcc
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2, or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* In addition to the permissions in the GNU General Public License, the
|
||||
* Free Software Foundation gives you unlimited permission to link the
|
||||
* compiled version of this file with other programs, and to distribute
|
||||
* those programs without any restriction coming from the use of this
|
||||
* file. (The General Public License restrictions do apply in other
|
||||
* respects; for example, they cover modification of the file, and
|
||||
* distribution when not linked into another program.)
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, 51 Franklin Street, Fifth Floor,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*
|
||||
* As a special exception, if you link this library with files
|
||||
* compiled with GCC to produce an executable, this does not cause
|
||||
* the resulting executable to be covered by the GNU General Public License.
|
||||
* This exception does not however invalidate any other reasons why
|
||||
* the executable file might be covered by the GNU General Public License.
|
||||
*/
|
||||
|
||||
.file "crtsavres.S"
|
||||
.section ".text"
|
||||
|
||||
/* On PowerPC64 Linux, these functions are provided by the linker. */
|
||||
#ifndef __powerpc64__
|
||||
|
||||
#define _GLOBAL(name) \
|
||||
.type name,@function; \
|
||||
.globl name; \
|
||||
name:
|
||||
|
||||
/* Routines for saving integer registers, called by the compiler. */
|
||||
/* Called with r11 pointing to the stack header word of the caller of the */
|
||||
/* function, just beyond the end of the integer save area. */
|
||||
|
||||
_GLOBAL(_savegpr_14)
|
||||
_GLOBAL(_save32gpr_14)
|
||||
stw 14,-72(11) /* save gp registers */
|
||||
_GLOBAL(_savegpr_15)
|
||||
_GLOBAL(_save32gpr_15)
|
||||
stw 15,-68(11)
|
||||
_GLOBAL(_savegpr_16)
|
||||
_GLOBAL(_save32gpr_16)
|
||||
stw 16,-64(11)
|
||||
_GLOBAL(_savegpr_17)
|
||||
_GLOBAL(_save32gpr_17)
|
||||
stw 17,-60(11)
|
||||
_GLOBAL(_savegpr_18)
|
||||
_GLOBAL(_save32gpr_18)
|
||||
stw 18,-56(11)
|
||||
_GLOBAL(_savegpr_19)
|
||||
_GLOBAL(_save32gpr_19)
|
||||
stw 19,-52(11)
|
||||
_GLOBAL(_savegpr_20)
|
||||
_GLOBAL(_save32gpr_20)
|
||||
stw 20,-48(11)
|
||||
_GLOBAL(_savegpr_21)
|
||||
_GLOBAL(_save32gpr_21)
|
||||
stw 21,-44(11)
|
||||
_GLOBAL(_savegpr_22)
|
||||
_GLOBAL(_save32gpr_22)
|
||||
stw 22,-40(11)
|
||||
_GLOBAL(_savegpr_23)
|
||||
_GLOBAL(_save32gpr_23)
|
||||
stw 23,-36(11)
|
||||
_GLOBAL(_savegpr_24)
|
||||
_GLOBAL(_save32gpr_24)
|
||||
stw 24,-32(11)
|
||||
_GLOBAL(_savegpr_25)
|
||||
_GLOBAL(_save32gpr_25)
|
||||
stw 25,-28(11)
|
||||
_GLOBAL(_savegpr_26)
|
||||
_GLOBAL(_save32gpr_26)
|
||||
stw 26,-24(11)
|
||||
_GLOBAL(_savegpr_27)
|
||||
_GLOBAL(_save32gpr_27)
|
||||
stw 27,-20(11)
|
||||
_GLOBAL(_savegpr_28)
|
||||
_GLOBAL(_save32gpr_28)
|
||||
stw 28,-16(11)
|
||||
_GLOBAL(_savegpr_29)
|
||||
_GLOBAL(_save32gpr_29)
|
||||
stw 29,-12(11)
|
||||
_GLOBAL(_savegpr_30)
|
||||
_GLOBAL(_save32gpr_30)
|
||||
stw 30,-8(11)
|
||||
_GLOBAL(_savegpr_31)
|
||||
_GLOBAL(_save32gpr_31)
|
||||
stw 31,-4(11)
|
||||
blr
|
||||
|
||||
/* Routines for restoring integer registers, called by the compiler. */
|
||||
/* Called with r11 pointing to the stack header word of the caller of the */
|
||||
/* function, just beyond the end of the integer restore area. */
|
||||
|
||||
_GLOBAL(_restgpr_14)
|
||||
_GLOBAL(_rest32gpr_14)
|
||||
lwz 14,-72(11) /* restore gp registers */
|
||||
_GLOBAL(_restgpr_15)
|
||||
_GLOBAL(_rest32gpr_15)
|
||||
lwz 15,-68(11)
|
||||
_GLOBAL(_restgpr_16)
|
||||
_GLOBAL(_rest32gpr_16)
|
||||
lwz 16,-64(11)
|
||||
_GLOBAL(_restgpr_17)
|
||||
_GLOBAL(_rest32gpr_17)
|
||||
lwz 17,-60(11)
|
||||
_GLOBAL(_restgpr_18)
|
||||
_GLOBAL(_rest32gpr_18)
|
||||
lwz 18,-56(11)
|
||||
_GLOBAL(_restgpr_19)
|
||||
_GLOBAL(_rest32gpr_19)
|
||||
lwz 19,-52(11)
|
||||
_GLOBAL(_restgpr_20)
|
||||
_GLOBAL(_rest32gpr_20)
|
||||
lwz 20,-48(11)
|
||||
_GLOBAL(_restgpr_21)
|
||||
_GLOBAL(_rest32gpr_21)
|
||||
lwz 21,-44(11)
|
||||
_GLOBAL(_restgpr_22)
|
||||
_GLOBAL(_rest32gpr_22)
|
||||
lwz 22,-40(11)
|
||||
_GLOBAL(_restgpr_23)
|
||||
_GLOBAL(_rest32gpr_23)
|
||||
lwz 23,-36(11)
|
||||
_GLOBAL(_restgpr_24)
|
||||
_GLOBAL(_rest32gpr_24)
|
||||
lwz 24,-32(11)
|
||||
_GLOBAL(_restgpr_25)
|
||||
_GLOBAL(_rest32gpr_25)
|
||||
lwz 25,-28(11)
|
||||
_GLOBAL(_restgpr_26)
|
||||
_GLOBAL(_rest32gpr_26)
|
||||
lwz 26,-24(11)
|
||||
_GLOBAL(_restgpr_27)
|
||||
_GLOBAL(_rest32gpr_27)
|
||||
lwz 27,-20(11)
|
||||
_GLOBAL(_restgpr_28)
|
||||
_GLOBAL(_rest32gpr_28)
|
||||
lwz 28,-16(11)
|
||||
_GLOBAL(_restgpr_29)
|
||||
_GLOBAL(_rest32gpr_29)
|
||||
lwz 29,-12(11)
|
||||
_GLOBAL(_restgpr_30)
|
||||
_GLOBAL(_rest32gpr_30)
|
||||
lwz 30,-8(11)
|
||||
_GLOBAL(_restgpr_31)
|
||||
_GLOBAL(_rest32gpr_31)
|
||||
lwz 31,-4(11)
|
||||
blr
|
||||
|
||||
/* Routines for restoring integer registers, called by the compiler. */
|
||||
/* Called with r11 pointing to the stack header word of the caller of the */
|
||||
/* function, just beyond the end of the integer restore area. */
|
||||
|
||||
_GLOBAL(_restgpr_14_x)
|
||||
_GLOBAL(_rest32gpr_14_x)
|
||||
lwz 14,-72(11) /* restore gp registers */
|
||||
_GLOBAL(_restgpr_15_x)
|
||||
_GLOBAL(_rest32gpr_15_x)
|
||||
lwz 15,-68(11)
|
||||
_GLOBAL(_restgpr_16_x)
|
||||
_GLOBAL(_rest32gpr_16_x)
|
||||
lwz 16,-64(11)
|
||||
_GLOBAL(_restgpr_17_x)
|
||||
_GLOBAL(_rest32gpr_17_x)
|
||||
lwz 17,-60(11)
|
||||
_GLOBAL(_restgpr_18_x)
|
||||
_GLOBAL(_rest32gpr_18_x)
|
||||
lwz 18,-56(11)
|
||||
_GLOBAL(_restgpr_19_x)
|
||||
_GLOBAL(_rest32gpr_19_x)
|
||||
lwz 19,-52(11)
|
||||
_GLOBAL(_restgpr_20_x)
|
||||
_GLOBAL(_rest32gpr_20_x)
|
||||
lwz 20,-48(11)
|
||||
_GLOBAL(_restgpr_21_x)
|
||||
_GLOBAL(_rest32gpr_21_x)
|
||||
lwz 21,-44(11)
|
||||
_GLOBAL(_restgpr_22_x)
|
||||
_GLOBAL(_rest32gpr_22_x)
|
||||
lwz 22,-40(11)
|
||||
_GLOBAL(_restgpr_23_x)
|
||||
_GLOBAL(_rest32gpr_23_x)
|
||||
lwz 23,-36(11)
|
||||
_GLOBAL(_restgpr_24_x)
|
||||
_GLOBAL(_rest32gpr_24_x)
|
||||
lwz 24,-32(11)
|
||||
_GLOBAL(_restgpr_25_x)
|
||||
_GLOBAL(_rest32gpr_25_x)
|
||||
lwz 25,-28(11)
|
||||
_GLOBAL(_restgpr_26_x)
|
||||
_GLOBAL(_rest32gpr_26_x)
|
||||
lwz 26,-24(11)
|
||||
_GLOBAL(_restgpr_27_x)
|
||||
_GLOBAL(_rest32gpr_27_x)
|
||||
lwz 27,-20(11)
|
||||
_GLOBAL(_restgpr_28_x)
|
||||
_GLOBAL(_rest32gpr_28_x)
|
||||
lwz 28,-16(11)
|
||||
_GLOBAL(_restgpr_29_x)
|
||||
_GLOBAL(_rest32gpr_29_x)
|
||||
lwz 29,-12(11)
|
||||
_GLOBAL(_restgpr_30_x)
|
||||
_GLOBAL(_rest32gpr_30_x)
|
||||
lwz 30,-8(11)
|
||||
_GLOBAL(_restgpr_31_x)
|
||||
_GLOBAL(_rest32gpr_31_x)
|
||||
lwz 0,4(11)
|
||||
lwz 31,-4(11)
|
||||
mtlr 0
|
||||
mr 1,11
|
||||
blr
|
||||
#endif
|
||||
63
arch/powerpc/boot/cuboot-52xx.c
Normal file
63
arch/powerpc/boot/cuboot-52xx.c
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Old U-boot compatibility for MPC5200
|
||||
*
|
||||
* Author: Grant Likely <grant.likely@secretlab.ca>
|
||||
*
|
||||
* Copyright (c) 2007 Secret Lab Technologies Ltd.
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_PPC_MPC52xx
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *soc, *reg;
|
||||
int div;
|
||||
u32 sysfreq;
|
||||
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
|
||||
/* Unfortunately, the specific model number is encoded in the
|
||||
* soc node name in existing dts files -- once that is fixed,
|
||||
* this can do a simple path lookup.
|
||||
*/
|
||||
soc = find_node_by_devtype(NULL, "soc");
|
||||
if (!soc)
|
||||
soc = find_node_by_compatible(NULL, "fsl,mpc5200-immr");
|
||||
if (!soc)
|
||||
soc = find_node_by_compatible(NULL, "fsl,mpc5200b-immr");
|
||||
if (soc) {
|
||||
setprop(soc, "bus-frequency", &bd.bi_ipbfreq,
|
||||
sizeof(bd.bi_ipbfreq));
|
||||
|
||||
if (!dt_xlate_reg(soc, 0, (void*)®, NULL))
|
||||
return;
|
||||
div = in_8(reg + 0x204) & 0x0020 ? 8 : 4;
|
||||
sysfreq = bd.bi_busfreq * div;
|
||||
setprop(soc, "system-frequency", &sysfreq, sizeof(sysfreq));
|
||||
}
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
53
arch/powerpc/boot/cuboot-824x.c
Normal file
53
arch/powerpc/boot/cuboot-824x.c
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Old U-boot compatibility for 824x
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_824x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *soc;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
|
||||
soc = find_node_by_devtype(NULL, "soc");
|
||||
if (soc) {
|
||||
void *serial = NULL;
|
||||
|
||||
setprop(soc, "bus-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
|
||||
while ((serial = find_node_by_devtype(serial, "serial"))) {
|
||||
if (get_parent(serial) != soc)
|
||||
continue;
|
||||
|
||||
setprop(serial, "clock-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
59
arch/powerpc/boot/cuboot-83xx.c
Normal file
59
arch/powerpc/boot/cuboot-83xx.c
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Old U-boot compatibility for 83xx
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_83xx
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *soc;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
|
||||
/* Unfortunately, the specific model number is encoded in the
|
||||
* soc node name in existing dts files -- once that is fixed,
|
||||
* this can do a simple path lookup.
|
||||
*/
|
||||
soc = find_node_by_devtype(NULL, "soc");
|
||||
if (soc) {
|
||||
void *serial = NULL;
|
||||
|
||||
setprop(soc, "bus-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
|
||||
while ((serial = find_node_by_devtype(serial, "serial"))) {
|
||||
if (get_parent(serial) != soc)
|
||||
continue;
|
||||
|
||||
setprop(serial, "clock-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
66
arch/powerpc/boot/cuboot-85xx-cpm2.c
Normal file
66
arch/powerpc/boot/cuboot-85xx-cpm2.c
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Old U-boot compatibility for 85xx
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_85xx
|
||||
#define TARGET_CPM2
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *devp;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq);
|
||||
|
||||
/* Unfortunately, the specific model number is encoded in the
|
||||
* soc node name in existing dts files -- once that is fixed,
|
||||
* this can do a simple path lookup.
|
||||
*/
|
||||
devp = find_node_by_devtype(NULL, "soc");
|
||||
if (devp) {
|
||||
void *serial = NULL;
|
||||
|
||||
setprop(devp, "bus-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
|
||||
while ((serial = find_node_by_devtype(serial, "serial"))) {
|
||||
if (get_parent(serial) != devp)
|
||||
continue;
|
||||
|
||||
setprop(serial, "clock-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
}
|
||||
}
|
||||
|
||||
devp = find_node_by_compatible(NULL, "fsl,cpm2-brg");
|
||||
if (devp)
|
||||
setprop(devp, "clock-frequency", &bd.bi_brgfreq,
|
||||
sizeof(bd.bi_brgfreq));
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
62
arch/powerpc/boot/cuboot-85xx.c
Normal file
62
arch/powerpc/boot/cuboot-85xx.c
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Old U-boot compatibility for 85xx
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_85xx
|
||||
#define TARGET_HAS_ETH3
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *soc;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr);
|
||||
dt_fixup_mac_address_by_alias("ethernet3", bd.bi_enet3addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq);
|
||||
|
||||
/* Unfortunately, the specific model number is encoded in the
|
||||
* soc node name in existing dts files -- once that is fixed,
|
||||
* this can do a simple path lookup.
|
||||
*/
|
||||
soc = find_node_by_devtype(NULL, "soc");
|
||||
if (soc) {
|
||||
void *serial = NULL;
|
||||
|
||||
setprop(soc, "bus-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
|
||||
while ((serial = find_node_by_devtype(serial, "serial"))) {
|
||||
if (get_parent(serial) != soc)
|
||||
continue;
|
||||
|
||||
setprop(serial, "clock-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
47
arch/powerpc/boot/cuboot-8xx.c
Normal file
47
arch/powerpc/boot/cuboot-8xx.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Old U-boot compatibility for 8xx
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_8xx
|
||||
#define TARGET_HAS_ETH1
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *node;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 16, bd.bi_busfreq);
|
||||
|
||||
node = finddevice("/soc/cpm");
|
||||
if (node)
|
||||
setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
|
||||
|
||||
node = finddevice("/soc/cpm/brg");
|
||||
if (node)
|
||||
setprop(node, "clock-frequency", &bd.bi_busfreq, 4);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
174
arch/powerpc/boot/cuboot-acadia.c
Normal file
174
arch/powerpc/boot/cuboot-acadia.c
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Acadia
|
||||
*
|
||||
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Copyright 2008 IBM Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "io.h"
|
||||
#include "dcr.h"
|
||||
#include "stdio.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
|
||||
|
||||
#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
|
||||
|
||||
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
|
||||
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
|
||||
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
|
||||
|
||||
#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
|
||||
#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
|
||||
#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
|
||||
#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
|
||||
|
||||
#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
|
||||
#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
|
||||
#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
|
||||
#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
|
||||
|
||||
static void get_clocks(void)
|
||||
{
|
||||
unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;
|
||||
unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;
|
||||
unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;
|
||||
unsigned long div; /* total divisor udiv * bdiv */
|
||||
unsigned long umin; /* minimum udiv */
|
||||
unsigned short diff; /* smallest diff */
|
||||
unsigned long udiv; /* best udiv */
|
||||
unsigned short idiff; /* current diff */
|
||||
unsigned short ibdiv; /* current bdiv */
|
||||
unsigned long est; /* current estimate */
|
||||
unsigned long baud;
|
||||
void *np;
|
||||
|
||||
/* read the sysclk value from the CPLD */
|
||||
sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;
|
||||
|
||||
/*
|
||||
* Read PLL Mode registers
|
||||
*/
|
||||
cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);
|
||||
cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);
|
||||
|
||||
/*
|
||||
* Determine forward divider A
|
||||
*/
|
||||
pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
|
||||
|
||||
/*
|
||||
* Determine forward divider B
|
||||
*/
|
||||
pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
|
||||
if (pllFwdDivB == 0)
|
||||
pllFwdDivB = 8;
|
||||
|
||||
/*
|
||||
* Determine FBK_DIV.
|
||||
*/
|
||||
pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
|
||||
if (pllFbkDiv == 0)
|
||||
pllFbkDiv = 256;
|
||||
|
||||
/*
|
||||
* Read CPR_PRIMAD register
|
||||
*/
|
||||
cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);
|
||||
|
||||
/*
|
||||
* Determine PLB_DIV.
|
||||
*/
|
||||
pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
|
||||
if (pllPlbDiv == 0)
|
||||
pllPlbDiv = 16;
|
||||
|
||||
/*
|
||||
* Determine EXTBUS_DIV.
|
||||
*/
|
||||
pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
|
||||
if (pllExtBusDiv == 0)
|
||||
pllExtBusDiv = 16;
|
||||
|
||||
/*
|
||||
* Determine OPB_DIV.
|
||||
*/
|
||||
pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
|
||||
if (pllOpbDiv == 0)
|
||||
pllOpbDiv = 16;
|
||||
|
||||
/* There is a bug in U-Boot that prevents us from using
|
||||
* bd.bi_opbfreq because U-Boot doesn't populate it for
|
||||
* 405EZ. We get to calculate it, yay!
|
||||
*/
|
||||
freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;
|
||||
|
||||
freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;
|
||||
|
||||
plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?
|
||||
pllFwdDivB : pllFwdDiv) *
|
||||
pllFbkDiv) / pllFwdDivB);
|
||||
|
||||
np = find_node_by_alias("serial0");
|
||||
if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))
|
||||
fatal("no current-speed property\n\r");
|
||||
|
||||
udiv = 256; /* Assume lowest possible serial clk */
|
||||
div = plloutb / (16 * baud); /* total divisor */
|
||||
umin = (plloutb / freqOPB) << 1; /* 2 x OPB divisor */
|
||||
diff = 256; /* highest possible */
|
||||
|
||||
/* i is the test udiv value -- start with the largest
|
||||
* possible (256) to minimize serial clock and constrain
|
||||
* search to umin.
|
||||
*/
|
||||
for (i = 256; i > umin; i--) {
|
||||
ibdiv = div / i;
|
||||
est = i * ibdiv;
|
||||
idiff = (est > div) ? (est-div) : (div-est);
|
||||
if (idiff == 0) {
|
||||
udiv = i;
|
||||
break; /* can't do better */
|
||||
} else if (idiff < diff) {
|
||||
udiv = i; /* best so far */
|
||||
diff = idiff; /* update lowest diff*/
|
||||
}
|
||||
}
|
||||
freqUART = plloutb / udiv;
|
||||
|
||||
dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);
|
||||
dt_fixup_clock("/plb/ebc", freqEBC);
|
||||
dt_fixup_clock("/plb/opb", freqOPB);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);
|
||||
}
|
||||
|
||||
static void acadia_fixups(void)
|
||||
{
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
get_clocks();
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = acadia_fixups;
|
||||
platform_ops.exit = ibm40x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
35
arch/powerpc/boot/cuboot-amigaone.c
Normal file
35
arch/powerpc/boot/cuboot-amigaone.c
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Old U-boot compatibility for AmigaOne
|
||||
*
|
||||
* Author: Gerhard Pircher (gerhard_pircher@gmx.net)
|
||||
*
|
||||
* Based on cuboot-83xx.c
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
31
arch/powerpc/boot/cuboot-bamboo.c
Normal file
31
arch/powerpc/boot/cuboot-bamboo.c
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Bamboo
|
||||
*
|
||||
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Copyright 2007 IBM Corporation
|
||||
*
|
||||
* Based on cuboot-ebony.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
bamboo_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
||||
}
|
||||
190
arch/powerpc/boot/cuboot-c2k.c
Normal file
190
arch/powerpc/boot/cuboot-c2k.c
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
/*
|
||||
* GEFanuc C2K platform code.
|
||||
*
|
||||
* Author: Remi Machet <rmachet@slac.stanford.edu>
|
||||
*
|
||||
* Originated from prpmc2800.c
|
||||
*
|
||||
* 2008 (c) Stanford University
|
||||
* 2007 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "types.h"
|
||||
#include "stdio.h"
|
||||
#include "io.h"
|
||||
#include "ops.h"
|
||||
#include "elf.h"
|
||||
#include "gunzip_util.h"
|
||||
#include "mv64x60.h"
|
||||
#include "cuboot.h"
|
||||
#include "ppcboot.h"
|
||||
|
||||
static u8 *bridge_base;
|
||||
|
||||
static void c2k_bridge_setup(u32 mem_size)
|
||||
{
|
||||
u32 i, v[30], enables, acc_bits;
|
||||
u32 pci_base_hi, pci_base_lo, size, buf[2];
|
||||
unsigned long cpu_base;
|
||||
int rc;
|
||||
void *devp, *mv64x60_devp;
|
||||
u8 *bridge_pbase, is_coherent;
|
||||
struct mv64x60_cpu2pci_win *tbl;
|
||||
int bus;
|
||||
|
||||
bridge_pbase = mv64x60_get_bridge_pbase();
|
||||
is_coherent = mv64x60_is_coherent();
|
||||
|
||||
if (is_coherent)
|
||||
acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
|
||||
| MV64x60_PCI_ACC_CNTL_SWAP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
|
||||
| MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
|
||||
else
|
||||
acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_SWAP_NONE
|
||||
| MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
|
||||
| MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
|
||||
|
||||
mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
|
||||
mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360");
|
||||
if (mv64x60_devp == NULL)
|
||||
fatal("Error: Missing marvell,mv64360 device tree node\n\r");
|
||||
|
||||
enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
|
||||
enables |= 0x007ffe00; /* Disable all cpu->pci windows */
|
||||
out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
|
||||
|
||||
/* Get the cpu -> pci i/o & mem mappings from the device tree */
|
||||
devp = NULL;
|
||||
for (bus = 0; ; bus++) {
|
||||
char name[] = "pci ";
|
||||
|
||||
name[strlen(name)-1] = bus+'0';
|
||||
|
||||
devp = find_node_by_alias(name);
|
||||
if (devp == NULL)
|
||||
break;
|
||||
|
||||
if (bus >= 2)
|
||||
fatal("Error: Only 2 PCI controllers are supported at" \
|
||||
" this time.\n");
|
||||
|
||||
mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,
|
||||
mem_size, acc_bits);
|
||||
|
||||
rc = getprop(devp, "ranges", v, sizeof(v));
|
||||
if (rc == 0)
|
||||
fatal("Error: Can't find marvell,mv64360-pci ranges"
|
||||
" property\n\r");
|
||||
|
||||
/* Get the cpu -> pci i/o & mem mappings from the device tree */
|
||||
|
||||
for (i = 0; i < rc; i += 6) {
|
||||
switch (v[i] & 0xff000000) {
|
||||
case 0x01000000: /* PCI I/O Space */
|
||||
tbl = mv64x60_cpu2pci_io;
|
||||
break;
|
||||
case 0x02000000: /* PCI MEM Space */
|
||||
tbl = mv64x60_cpu2pci_mem;
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
pci_base_hi = v[i+1];
|
||||
pci_base_lo = v[i+2];
|
||||
cpu_base = v[i+3];
|
||||
size = v[i+5];
|
||||
|
||||
buf[0] = cpu_base;
|
||||
buf[1] = size;
|
||||
|
||||
if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
|
||||
fatal("Error: Can't translate PCI address " \
|
||||
"0x%x\n\r", (u32)cpu_base);
|
||||
|
||||
mv64x60_config_cpu2pci_window(bridge_base, bus,
|
||||
pci_base_hi, pci_base_lo, cpu_base, size, tbl);
|
||||
}
|
||||
|
||||
enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci<bus> i/o,
|
||||
cpu->pci<bus> mem0 */
|
||||
out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),
|
||||
enables);
|
||||
};
|
||||
}
|
||||
|
||||
static void c2k_fixups(void)
|
||||
{
|
||||
u32 mem_size;
|
||||
|
||||
mem_size = mv64x60_get_mem_size(bridge_base);
|
||||
c2k_bridge_setup(mem_size); /* Do necessary bridge setup */
|
||||
}
|
||||
|
||||
#define MV64x60_MPP_CNTL_0 0xf000
|
||||
#define MV64x60_MPP_CNTL_2 0xf008
|
||||
#define MV64x60_GPP_IO_CNTL 0xf100
|
||||
#define MV64x60_GPP_LEVEL_CNTL 0xf110
|
||||
#define MV64x60_GPP_VALUE_SET 0xf118
|
||||
|
||||
static void c2k_reset(void)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
udelay(5000000);
|
||||
|
||||
if (bridge_base != 0) {
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
|
||||
temp &= 0xFFFF0FFF;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
|
||||
temp |= 0x00000004;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
|
||||
temp |= 0x00000004;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
|
||||
temp &= 0xFFFF0FFF;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
|
||||
temp |= 0x00080000;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
|
||||
|
||||
temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
|
||||
temp |= 0x00080000;
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
|
||||
|
||||
out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
|
||||
0x00080004);
|
||||
}
|
||||
|
||||
for (;;);
|
||||
}
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
fdt_init(_dtb_start);
|
||||
|
||||
bridge_base = mv64x60_get_bridge_base();
|
||||
|
||||
platform_ops.fixups = c2k_fixups;
|
||||
platform_ops.exit = c2k_reset;
|
||||
|
||||
if (serial_console_init() < 0)
|
||||
exit();
|
||||
}
|
||||
31
arch/powerpc/boot/cuboot-ebony.c
Normal file
31
arch/powerpc/boot/cuboot-ebony.c
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Ebony
|
||||
*
|
||||
* Author: David Gibson <david@gibson.dropbear.id.au>
|
||||
*
|
||||
* Copyright 2007 David Gibson, IBM Corporatio.
|
||||
* Based on cuboot-83xx.c, which is:
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
ebony_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
||||
}
|
||||
142
arch/powerpc/boot/cuboot-hotfoot.c
Normal file
142
arch/powerpc/boot/cuboot-hotfoot.c
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Esteem 195E Hotfoot CPU Board
|
||||
*
|
||||
* Author: Solomon Peachy <solomon@linux-wlan.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "reg.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_HOTFOOT
|
||||
|
||||
#include "ppcboot-hotfoot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
#define NUM_REGS 3
|
||||
|
||||
static void hotfoot_fixups(void)
|
||||
{
|
||||
u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
|
||||
dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_procfreq, 0);
|
||||
dt_fixup_clock("/plb", bd.bi_plb_busfreq);
|
||||
dt_fixup_clock("/plb/opb", bd.bi_opbfreq);
|
||||
dt_fixup_clock("/plb/ebc", bd.bi_pci_busfreq);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", bd.bi_procfreq / uart);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", bd.bi_procfreq / uart);
|
||||
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
|
||||
/* Is this a single eth/serial board? */
|
||||
if ((bd.bi_enet1addr[0] == 0) &&
|
||||
(bd.bi_enet1addr[1] == 0) &&
|
||||
(bd.bi_enet1addr[2] == 0) &&
|
||||
(bd.bi_enet1addr[3] == 0) &&
|
||||
(bd.bi_enet1addr[4] == 0) &&
|
||||
(bd.bi_enet1addr[5] == 0)) {
|
||||
void *devp;
|
||||
|
||||
printf("Trimming devtree for single serial/eth board\n");
|
||||
|
||||
devp = finddevice("/plb/opb/serial@ef600300");
|
||||
if (!devp)
|
||||
fatal("Can't find node for /plb/opb/serial@ef600300");
|
||||
del_node(devp);
|
||||
|
||||
devp = finddevice("/plb/opb/ethernet@ef600900");
|
||||
if (!devp)
|
||||
fatal("Can't find node for /plb/opb/ethernet@ef600900");
|
||||
del_node(devp);
|
||||
}
|
||||
|
||||
ibm4xx_quiesce_eth((u32 *)0xef600800, (u32 *)0xef600900);
|
||||
|
||||
/* Fix up flash size in fdt for 4M boards. */
|
||||
if (bd.bi_flashsize < 0x800000) {
|
||||
u32 regs[NUM_REGS];
|
||||
void *devp = finddevice("/plb/ebc/nor_flash@0");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for nor_flash!??");
|
||||
|
||||
printf("Fixing devtree for 4M Flash\n");
|
||||
|
||||
/* First fix up the base addresse */
|
||||
getprop(devp, "reg", regs, sizeof(regs));
|
||||
regs[0] = 0;
|
||||
regs[1] = 0xffc00000;
|
||||
regs[2] = 0x00400000;
|
||||
setprop(devp, "reg", regs, sizeof(regs));
|
||||
|
||||
/* Then the offsets */
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@0");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@0");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@1");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@1");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@2");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@2");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@3");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@3");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@4");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@4");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@6");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@6");
|
||||
getprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
regs[0] -= 0x400000;
|
||||
setprop(devp, "reg", regs, 2*sizeof(u32));
|
||||
|
||||
/* Delete the FeatFS node */
|
||||
devp = finddevice("/plb/ebc/nor_flash@0/partition@5");
|
||||
if (!devp)
|
||||
fatal("Can't find FDT node for partition@5");
|
||||
del_node(devp);
|
||||
}
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = hotfoot_fixups;
|
||||
platform_ops.exit = ibm40x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
57
arch/powerpc/boot/cuboot-katmai.c
Normal file
57
arch/powerpc/boot/cuboot-katmai.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Katmai
|
||||
*
|
||||
* Author: Hugh Blemings <hugh@au.ibm.com>
|
||||
*
|
||||
* Copyright 2007 Hugh Blemings, IBM Corporation.
|
||||
* Based on cuboot-ebony.c which is:
|
||||
* Copyright 2007 David Gibson, IBM Corporation.
|
||||
* Based on cuboot-83xx.c, which is:
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "reg.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
BSS_STACK(4096);
|
||||
|
||||
static void katmai_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333000;
|
||||
|
||||
/* 440SP Clock logic is all but identical to 440GX
|
||||
* so we just use that code for now at least
|
||||
*/
|
||||
ibm440spe_fixup_clocks(sysclk, 6 * 1843200, 0);
|
||||
|
||||
ibm440spe_fixup_memsize();
|
||||
|
||||
dt_fixup_mac_address(0, bd.bi_enetaddr);
|
||||
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
platform_ops.fixups = katmai_fixups;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
49
arch/powerpc/boot/cuboot-kilauea.c
Normal file
49
arch/powerpc/boot/cuboot-kilauea.c
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Old U-boot compatibility for PPC405EX. This image is already included
|
||||
* a dtb.
|
||||
*
|
||||
* Author: Tiejun Chen <tiejun.chen@windriver.com>
|
||||
*
|
||||
* Copyright (C) 2009 Wind River Systems, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "io.h"
|
||||
#include "dcr.h"
|
||||
#include "stdio.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
#define KILAUEA_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void kilauea_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm405ex_fixup_clocks(sysclk, KILAUEA_SYS_EXT_SERIAL_CLOCK);
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = kilauea_fixups;
|
||||
platform_ops.exit = ibm40x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
48
arch/powerpc/boot/cuboot-mpc7448hpc2.c
Normal file
48
arch/powerpc/boot/cuboot-mpc7448hpc2.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
|
||||
*
|
||||
* Author: Roy Zang <tie-fei.zang@freescale.com>
|
||||
*
|
||||
* Description:
|
||||
* Old U-boot compatibility for mpc7448hpc2 board
|
||||
* Based on the code of Scott Wood <scottwood@freescale.com>
|
||||
* for 83xx and 85xx.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_HAS_ETH1
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
extern char _dtb_start[], _dtb_end[];
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *tsi;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
tsi = find_node_by_devtype(NULL, "tsi-bridge");
|
||||
if (tsi)
|
||||
setprop(tsi, "bus-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
272
arch/powerpc/boot/cuboot-pq2.c
Normal file
272
arch/powerpc/boot/cuboot-pq2.c
Normal file
|
|
@ -0,0 +1,272 @@
|
|||
/*
|
||||
* Old U-boot compatibility for PowerQUICC II
|
||||
* (a.k.a. 82xx with CPM, not the 8240 family of chips)
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
#include "io.h"
|
||||
#include "fsl-soc.h"
|
||||
|
||||
#define TARGET_CPM2
|
||||
#define TARGET_HAS_ETH1
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
struct cs_range {
|
||||
u32 csnum;
|
||||
u32 base; /* must be zero */
|
||||
u32 addr;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
struct pci_range {
|
||||
u32 flags;
|
||||
u32 pci_addr[2];
|
||||
u32 phys_addr;
|
||||
u32 size[2];
|
||||
};
|
||||
|
||||
struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
|
||||
struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
|
||||
|
||||
/* Different versions of u-boot put the BCSR in different places, and
|
||||
* some don't set up the PCI PIC at all, so we assume the device tree is
|
||||
* sane and update the BRx registers appropriately.
|
||||
*
|
||||
* For any node defined as compatible with fsl,pq2-localbus,
|
||||
* #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus.
|
||||
* Ranges must be for whole chip selects.
|
||||
*/
|
||||
static void update_cs_ranges(void)
|
||||
{
|
||||
void *bus_node, *parent_node;
|
||||
u32 *ctrl_addr;
|
||||
unsigned long ctrl_size;
|
||||
u32 naddr, nsize;
|
||||
int len;
|
||||
int i;
|
||||
|
||||
bus_node = finddevice("/localbus");
|
||||
if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus"))
|
||||
return;
|
||||
|
||||
dt_get_reg_format(bus_node, &naddr, &nsize);
|
||||
if (naddr != 2 || nsize != 1)
|
||||
goto err;
|
||||
|
||||
parent_node = get_parent(bus_node);
|
||||
if (!parent_node)
|
||||
goto err;
|
||||
|
||||
dt_get_reg_format(parent_node, &naddr, &nsize);
|
||||
if (naddr != 1 || nsize != 1)
|
||||
goto err;
|
||||
|
||||
if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr,
|
||||
&ctrl_size))
|
||||
goto err;
|
||||
|
||||
len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
|
||||
|
||||
for (i = 0; i < len / sizeof(struct cs_range); i++) {
|
||||
u32 base, option;
|
||||
int cs = cs_ranges_buf[i].csnum;
|
||||
if (cs >= ctrl_size / 8)
|
||||
goto err;
|
||||
|
||||
if (cs_ranges_buf[i].base != 0)
|
||||
goto err;
|
||||
|
||||
base = in_be32(&ctrl_addr[cs * 2]);
|
||||
|
||||
/* If CS is already valid, use the existing flags.
|
||||
* Otherwise, guess a sane default.
|
||||
*/
|
||||
if (base & 1) {
|
||||
base &= 0x7fff;
|
||||
option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
|
||||
} else {
|
||||
base = 0x1801;
|
||||
option = 0x10;
|
||||
}
|
||||
|
||||
out_be32(&ctrl_addr[cs * 2], 0);
|
||||
out_be32(&ctrl_addr[cs * 2 + 1],
|
||||
option | ~(cs_ranges_buf[i].size - 1));
|
||||
out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
err:
|
||||
printf("Bad /localbus node\r\n");
|
||||
}
|
||||
|
||||
/* Older u-boots don't set PCI up properly. Update the hardware to match
|
||||
* the device tree. The prefetch mem region and non-prefetch mem region
|
||||
* must be contiguous in the host bus. As required by the PCI binding,
|
||||
* PCI #addr/#size must be 3/2. The parent bus must be 1/1. Only
|
||||
* 32-bit PCI is supported. All three region types (prefetchable mem,
|
||||
* non-prefetchable mem, and I/O) must be present.
|
||||
*/
|
||||
static void fixup_pci(void)
|
||||
{
|
||||
struct pci_range *mem = NULL, *mmio = NULL,
|
||||
*io = NULL, *mem_base = NULL;
|
||||
u32 *pci_regs[3];
|
||||
u8 *soc_regs;
|
||||
int i, len;
|
||||
void *node, *parent_node;
|
||||
u32 naddr, nsize, mem_pow2, mem_mask;
|
||||
|
||||
node = finddevice("/pci");
|
||||
if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
|
||||
return;
|
||||
|
||||
for (i = 0; i < 3; i++)
|
||||
if (!dt_xlate_reg(node, i,
|
||||
(unsigned long *)&pci_regs[i], NULL))
|
||||
goto err;
|
||||
|
||||
soc_regs = (u8 *)fsl_get_immr();
|
||||
if (!soc_regs)
|
||||
goto unhandled;
|
||||
|
||||
dt_get_reg_format(node, &naddr, &nsize);
|
||||
if (naddr != 3 || nsize != 2)
|
||||
goto err;
|
||||
|
||||
parent_node = get_parent(node);
|
||||
if (!parent_node)
|
||||
goto err;
|
||||
|
||||
dt_get_reg_format(parent_node, &naddr, &nsize);
|
||||
if (naddr != 1 || nsize != 1)
|
||||
goto unhandled;
|
||||
|
||||
len = getprop(node, "ranges", pci_ranges_buf,
|
||||
sizeof(pci_ranges_buf));
|
||||
|
||||
for (i = 0; i < len / sizeof(struct pci_range); i++) {
|
||||
u32 flags = pci_ranges_buf[i].flags & 0x43000000;
|
||||
|
||||
if (flags == 0x42000000)
|
||||
mem = &pci_ranges_buf[i];
|
||||
else if (flags == 0x02000000)
|
||||
mmio = &pci_ranges_buf[i];
|
||||
else if (flags == 0x01000000)
|
||||
io = &pci_ranges_buf[i];
|
||||
}
|
||||
|
||||
if (!mem || !mmio || !io)
|
||||
goto unhandled;
|
||||
if (mem->size[1] != mmio->size[1])
|
||||
goto unhandled;
|
||||
if (mem->size[1] & (mem->size[1] - 1))
|
||||
goto unhandled;
|
||||
if (io->size[1] & (io->size[1] - 1))
|
||||
goto unhandled;
|
||||
|
||||
if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
|
||||
mem_base = mem;
|
||||
else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
|
||||
mem_base = mmio;
|
||||
else
|
||||
goto unhandled;
|
||||
|
||||
out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
|
||||
out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
|
||||
|
||||
out_be32(&pci_regs[1][1], io->phys_addr | 1);
|
||||
out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
|
||||
|
||||
out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
|
||||
out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
|
||||
out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
|
||||
|
||||
out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
|
||||
out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
|
||||
out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
|
||||
|
||||
out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
|
||||
out_le32(&pci_regs[0][14], io->phys_addr >> 12);
|
||||
out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
|
||||
|
||||
/* Inbound translation */
|
||||
out_le32(&pci_regs[0][58], 0);
|
||||
out_le32(&pci_regs[0][60], 0);
|
||||
|
||||
mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
|
||||
mem_mask = ~(mem_pow2 - 1) >> 12;
|
||||
out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
|
||||
|
||||
/* If PCI is disabled, drive RST high to enable. */
|
||||
if (!(in_le32(&pci_regs[0][32]) & 1)) {
|
||||
/* Tpvrh (Power valid to RST# high) 100 ms */
|
||||
udelay(100000);
|
||||
|
||||
out_le32(&pci_regs[0][32], 1);
|
||||
|
||||
/* Trhfa (RST# high to first cfg access) 2^25 clocks */
|
||||
udelay(1020000);
|
||||
}
|
||||
|
||||
/* Enable bus master and memory access */
|
||||
out_le32(&pci_regs[0][64], 0x80000004);
|
||||
out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
|
||||
|
||||
/* Park the bus on PCI, and elevate PCI's arbitration priority,
|
||||
* as required by section 9.6 of the user's manual.
|
||||
*/
|
||||
out_8(&soc_regs[0x10028], 3);
|
||||
out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
|
||||
|
||||
return;
|
||||
|
||||
err:
|
||||
printf("Bad PCI node -- using existing firmware setup.\r\n");
|
||||
return;
|
||||
|
||||
unhandled:
|
||||
printf("Unsupported PCI node -- using existing firmware setup.\r\n");
|
||||
}
|
||||
|
||||
static void pq2_platform_fixups(void)
|
||||
{
|
||||
void *node;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
|
||||
node = finddevice("/soc/cpm");
|
||||
if (node)
|
||||
setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
|
||||
|
||||
node = finddevice("/soc/cpm/brg");
|
||||
if (node)
|
||||
setprop(node, "clock-frequency", &bd.bi_brgfreq, 4);
|
||||
|
||||
update_cs_ranges();
|
||||
fixup_pci();
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = pq2_platform_fixups;
|
||||
}
|
||||
57
arch/powerpc/boot/cuboot-rainier.c
Normal file
57
arch/powerpc/boot/cuboot-rainier.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Rainier
|
||||
*
|
||||
* Valentine Barshak <vbarshak@ru.mvista.com>
|
||||
* Copyright 2007 MontaVista Software, Inc
|
||||
*
|
||||
* Based on Ebony code by David Gibson <david@gibson.dropbear.id.au>
|
||||
* Copyright IBM Corporation, 2007
|
||||
*
|
||||
* Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
* Copyright IBM Corporation, 2007
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2 of the License
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "elf.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "page.h"
|
||||
#include "ops.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
|
||||
static void rainier_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
ibm4xx_denali_fixup_memsize();
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = rainier_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
49
arch/powerpc/boot/cuboot-sam440ep.c
Normal file
49
arch/powerpc/boot/cuboot-sam440ep.c
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Sam440ep based off bamboo.c code
|
||||
* original copyrights below
|
||||
*
|
||||
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Copyright 2007 IBM Corporation
|
||||
*
|
||||
* Based on cuboot-ebony.c
|
||||
*
|
||||
* Modified from cuboot-bamboo.c for sam440ep:
|
||||
* Copyright 2008 Giuseppe Coviello <gicoviello@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "44x.h"
|
||||
#include "4xx.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void sam440ep_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 66666666;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
|
||||
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = sam440ep_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
57
arch/powerpc/boot/cuboot-sequoia.c
Normal file
57
arch/powerpc/boot/cuboot-sequoia.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Sequoia
|
||||
*
|
||||
* Valentine Barshak <vbarshak@ru.mvista.com>
|
||||
* Copyright 2007 MontaVista Software, Inc
|
||||
*
|
||||
* Based on Ebony code by David Gibson <david@gibson.dropbear.id.au>
|
||||
* Copyright IBM Corporation, 2007
|
||||
*
|
||||
* Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
* Copyright IBM Corporation, 2007
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2 of the License
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "elf.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "page.h"
|
||||
#include "ops.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
|
||||
static void sequoia_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
ibm4xx_denali_fixup_memsize();
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = sequoia_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
57
arch/powerpc/boot/cuboot-taishan.c
Normal file
57
arch/powerpc/boot/cuboot-taishan.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Taishan
|
||||
*
|
||||
* Author: Hugh Blemings <hugh@au.ibm.com>
|
||||
*
|
||||
* Copyright 2007 Hugh Blemings, IBM Corporation.
|
||||
* Based on cuboot-ebony.c which is:
|
||||
* Copyright 2007 David Gibson, IBM Corporation.
|
||||
* Based on cuboot-83xx.c, which is:
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
#include "reg.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#define TARGET_440GX
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
BSS_STACK(4096);
|
||||
|
||||
static void taishan_fixups(void)
|
||||
{
|
||||
/* FIXME: sysclk should be derived by reading the FPGA
|
||||
registers */
|
||||
unsigned long sysclk = 33000000;
|
||||
|
||||
ibm440gx_fixup_clocks(sysclk, 6 * 1843200, 25000000);
|
||||
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
platform_ops.fixups = taishan_fixups;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
38
arch/powerpc/boot/cuboot-warp.c
Normal file
38
arch/powerpc/boot/cuboot-warp.c
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2008 PIKA Technologies
|
||||
* Sean MacLennan <smaclennan@pikatech.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "4xx.h"
|
||||
#include "cuboot.h"
|
||||
#include "stdio.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void warp_fixups(void)
|
||||
{
|
||||
ibm440ep_fixup_clocks(66000000, 11059200, 50000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
platform_ops.fixups = warp_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
44
arch/powerpc/boot/cuboot-yosemite.c
Normal file
44
arch/powerpc/boot/cuboot-yosemite.c
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Yosemite
|
||||
*
|
||||
* Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* Copyright 2008 IBM Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void yosemite_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 66666666;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = yosemite_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
32
arch/powerpc/boot/cuboot.c
Normal file
32
arch/powerpc/boot/cuboot.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Compatibility for old (not device tree aware) U-Boot versions
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
* Consolidated using macros by David Gibson <david@gibson.dropbear.id.au>
|
||||
*
|
||||
* Copyright 2007 David Gibson, IBM Corporation.
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
|
||||
#include "ppcboot.h"
|
||||
|
||||
void cuboot_init(unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7,
|
||||
unsigned long end_of_ram)
|
||||
{
|
||||
unsigned long avail_ram = end_of_ram - (unsigned long)_end;
|
||||
|
||||
loader_info.initrd_addr = r4;
|
||||
loader_info.initrd_size = r4 ? r5 - r4 : 0;
|
||||
loader_info.cmdline = (char *)r6;
|
||||
loader_info.cmdline_len = r7 - r6;
|
||||
|
||||
simple_alloc_init(_end, avail_ram - 1024*1024, 32, 64);
|
||||
}
|
||||
14
arch/powerpc/boot/cuboot.h
Normal file
14
arch/powerpc/boot/cuboot.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef _PPC_BOOT_CUBOOT_H_
|
||||
#define _PPC_BOOT_CUBOOT_H_
|
||||
|
||||
void cuboot_init(unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7,
|
||||
unsigned long end_of_ram);
|
||||
|
||||
#define CUBOOT_INIT() \
|
||||
do { \
|
||||
memcpy(&bd, (bd_t *)r3, sizeof(bd)); \
|
||||
cuboot_init(r4, r5, r6, r7, bd.bi_memstart + bd.bi_memsize); \
|
||||
} while (0)
|
||||
|
||||
#endif /* _PPC_BOOT_CUBOOT_H_ */
|
||||
207
arch/powerpc/boot/dcr.h
Normal file
207
arch/powerpc/boot/dcr.h
Normal file
|
|
@ -0,0 +1,207 @@
|
|||
#ifndef _PPC_BOOT_DCR_H_
|
||||
#define _PPC_BOOT_DCR_H_
|
||||
|
||||
#define mfdcr(rn) \
|
||||
({ \
|
||||
unsigned long rval; \
|
||||
asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
|
||||
rval; \
|
||||
})
|
||||
#define mtdcr(rn, val) \
|
||||
asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
|
||||
#define mfdcrx(rn) \
|
||||
({ \
|
||||
unsigned long rval; \
|
||||
asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
|
||||
rval; \
|
||||
})
|
||||
#define mtdcrx(rn, val) \
|
||||
({ \
|
||||
asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
|
||||
})
|
||||
|
||||
/* 440GP/440GX SDRAM controller DCRs */
|
||||
#define DCRN_SDRAM0_CFGADDR 0x010
|
||||
#define DCRN_SDRAM0_CFGDATA 0x011
|
||||
|
||||
#define SDRAM0_READ(offset) ({\
|
||||
mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
|
||||
mfdcr(DCRN_SDRAM0_CFGDATA); })
|
||||
#define SDRAM0_WRITE(offset, data) ({\
|
||||
mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
|
||||
mtdcr(DCRN_SDRAM0_CFGDATA, data); })
|
||||
|
||||
#define SDRAM0_B0CR 0x40
|
||||
#define SDRAM0_B1CR 0x44
|
||||
#define SDRAM0_B2CR 0x48
|
||||
#define SDRAM0_B3CR 0x4c
|
||||
|
||||
static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
|
||||
SDRAM0_B2CR, SDRAM0_B3CR };
|
||||
|
||||
#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
|
||||
#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
|
||||
#define SDRAM_CONFIG_BANK_SIZE(reg) \
|
||||
(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
|
||||
|
||||
/* 440GP External Bus Controller (EBC) */
|
||||
#define DCRN_EBC0_CFGADDR 0x012
|
||||
#define DCRN_EBC0_CFGDATA 0x013
|
||||
#define EBC_NUM_BANKS 8
|
||||
#define EBC_B0CR 0x00
|
||||
#define EBC_B1CR 0x01
|
||||
#define EBC_B2CR 0x02
|
||||
#define EBC_B3CR 0x03
|
||||
#define EBC_B4CR 0x04
|
||||
#define EBC_B5CR 0x05
|
||||
#define EBC_B6CR 0x06
|
||||
#define EBC_B7CR 0x07
|
||||
#define EBC_BXCR(n) (n)
|
||||
#define EBC_BXCR_BAS 0xfff00000
|
||||
#define EBC_BXCR_BS 0x000e0000
|
||||
#define EBC_BXCR_BANK_SIZE(reg) \
|
||||
(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
|
||||
#define EBC_BXCR_BU 0x00018000
|
||||
#define EBC_BXCR_BU_OFF 0x00000000
|
||||
#define EBC_BXCR_BU_RO 0x00008000
|
||||
#define EBC_BXCR_BU_WO 0x00010000
|
||||
#define EBC_BXCR_BU_RW 0x00018000
|
||||
#define EBC_BXCR_BW 0x00006000
|
||||
#define EBC_B0AP 0x10
|
||||
#define EBC_B1AP 0x11
|
||||
#define EBC_B2AP 0x12
|
||||
#define EBC_B3AP 0x13
|
||||
#define EBC_B4AP 0x14
|
||||
#define EBC_B5AP 0x15
|
||||
#define EBC_B6AP 0x16
|
||||
#define EBC_B7AP 0x17
|
||||
#define EBC_BXAP(n) (0x10+(n))
|
||||
#define EBC_BEAR 0x20
|
||||
#define EBC_BESR 0x21
|
||||
#define EBC_CFG 0x23
|
||||
#define EBC_CID 0x24
|
||||
|
||||
/* 440GP Clock, PM, chip control */
|
||||
#define DCRN_CPC0_SR 0x0b0
|
||||
#define DCRN_CPC0_ER 0x0b1
|
||||
#define DCRN_CPC0_FR 0x0b2
|
||||
#define DCRN_CPC0_SYS0 0x0e0
|
||||
#define CPC0_SYS0_TUNE 0xffc00000
|
||||
#define CPC0_SYS0_FBDV_MASK 0x003c0000
|
||||
#define CPC0_SYS0_FWDVA_MASK 0x00038000
|
||||
#define CPC0_SYS0_FWDVB_MASK 0x00007000
|
||||
#define CPC0_SYS0_OPDV_MASK 0x00000c00
|
||||
#define CPC0_SYS0_EPDV_MASK 0x00000300
|
||||
/* Helper macros to compute the actual clock divider values from the
|
||||
* encodings in the CPC0 register */
|
||||
#define CPC0_SYS0_FBDV(reg) \
|
||||
((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
|
||||
#define CPC0_SYS0_FWDVA(reg) \
|
||||
(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
|
||||
#define CPC0_SYS0_FWDVB(reg) \
|
||||
(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
|
||||
#define CPC0_SYS0_OPDV(reg) \
|
||||
((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
|
||||
#define CPC0_SYS0_EPDV(reg) \
|
||||
((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
|
||||
#define CPC0_SYS0_EXTSL 0x00000080
|
||||
#define CPC0_SYS0_RW_MASK 0x00000060
|
||||
#define CPC0_SYS0_RL 0x00000010
|
||||
#define CPC0_SYS0_ZMIISL_MASK 0x0000000c
|
||||
#define CPC0_SYS0_BYPASS 0x00000002
|
||||
#define CPC0_SYS0_NTO1 0x00000001
|
||||
#define DCRN_CPC0_SYS1 0x0e1
|
||||
#define DCRN_CPC0_CUST0 0x0e2
|
||||
#define DCRN_CPC0_CUST1 0x0e3
|
||||
#define DCRN_CPC0_STRP0 0x0e4
|
||||
#define DCRN_CPC0_STRP1 0x0e5
|
||||
#define DCRN_CPC0_STRP2 0x0e6
|
||||
#define DCRN_CPC0_STRP3 0x0e7
|
||||
#define DCRN_CPC0_GPIO 0x0e8
|
||||
#define DCRN_CPC0_PLB 0x0e9
|
||||
#define DCRN_CPC0_CR1 0x0ea
|
||||
#define DCRN_CPC0_CR0 0x0eb
|
||||
#define CPC0_CR0_SWE 0x80000000
|
||||
#define CPC0_CR0_CETE 0x40000000
|
||||
#define CPC0_CR0_U1FCS 0x20000000
|
||||
#define CPC0_CR0_U0DTE 0x10000000
|
||||
#define CPC0_CR0_U0DRE 0x08000000
|
||||
#define CPC0_CR0_U0DC 0x04000000
|
||||
#define CPC0_CR0_U1DTE 0x02000000
|
||||
#define CPC0_CR0_U1DRE 0x01000000
|
||||
#define CPC0_CR0_U1DC 0x00800000
|
||||
#define CPC0_CR0_U0EC 0x00400000
|
||||
#define CPC0_CR0_U1EC 0x00200000
|
||||
#define CPC0_CR0_UDIV_MASK 0x001f0000
|
||||
#define CPC0_CR0_UDIV(reg) \
|
||||
((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
|
||||
#define DCRN_CPC0_MIRQ0 0x0ec
|
||||
#define DCRN_CPC0_MIRQ1 0x0ed
|
||||
#define DCRN_CPC0_JTAGID 0x0ef
|
||||
|
||||
#define DCRN_MAL0_CFG 0x180
|
||||
#define MAL_RESET 0x80000000
|
||||
|
||||
/* 440EP Clock/Power-on Reset regs */
|
||||
#define DCRN_CPR0_ADDR 0xc
|
||||
#define DCRN_CPR0_DATA 0xd
|
||||
#define CPR0_PLLD0 0x60
|
||||
#define CPR0_OPBD0 0xc0
|
||||
#define CPR0_PERD0 0xe0
|
||||
#define CPR0_PRIMBD0 0xa0
|
||||
#define CPR0_SCPID 0x120
|
||||
#define CPR0_PLLC0 0x40
|
||||
|
||||
/* 405GP Clocking/Power Management/Chip Control regs */
|
||||
#define DCRN_CPC0_PLLMR 0xb0
|
||||
#define DCRN_405_CPC0_CR0 0xb1
|
||||
#define DCRN_405_CPC0_CR1 0xb2
|
||||
#define DCRN_405_CPC0_PSR 0xb4
|
||||
|
||||
/* 405EP Clocking/Power Management/Chip Control regs */
|
||||
#define DCRN_CPC0_PLLMR0 0xf0
|
||||
#define DCRN_CPC0_PLLMR1 0xf4
|
||||
#define DCRN_CPC0_UCR 0xf5
|
||||
|
||||
/* 440GX/405EX Clock Control reg */
|
||||
#define DCRN_CPR0_CLKUPD 0x020
|
||||
#define DCRN_CPR0_PLLC 0x040
|
||||
#define DCRN_CPR0_PLLD 0x060
|
||||
#define DCRN_CPR0_PRIMAD 0x080
|
||||
#define DCRN_CPR0_PRIMBD 0x0a0
|
||||
#define DCRN_CPR0_OPBD 0x0c0
|
||||
#define DCRN_CPR0_PERD 0x0e0
|
||||
#define DCRN_CPR0_MALD 0x100
|
||||
|
||||
#define DCRN_SDR0_CONFIG_ADDR 0xe
|
||||
#define DCRN_SDR0_CONFIG_DATA 0xf
|
||||
|
||||
/* SDR read/write helper macros */
|
||||
#define SDR0_READ(offset) ({\
|
||||
mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
|
||||
mfdcr(DCRN_SDR0_CONFIG_DATA); })
|
||||
#define SDR0_WRITE(offset, data) ({\
|
||||
mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
|
||||
mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
|
||||
|
||||
#define DCRN_SDR0_UART0 0x0120
|
||||
#define DCRN_SDR0_UART1 0x0121
|
||||
#define DCRN_SDR0_UART2 0x0122
|
||||
#define DCRN_SDR0_UART3 0x0123
|
||||
|
||||
|
||||
/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
|
||||
|
||||
#define DCRN_CPR0_CFGADDR 0xc
|
||||
#define DCRN_CPR0_CFGDATA 0xd
|
||||
|
||||
#define CPR0_READ(offset) ({\
|
||||
mtdcr(DCRN_CPR0_CFGADDR, offset); \
|
||||
mfdcr(DCRN_CPR0_CFGDATA); })
|
||||
#define CPR0_WRITE(offset, data) ({\
|
||||
mtdcr(DCRN_CPR0_CFGADDR, offset); \
|
||||
mtdcr(DCRN_CPR0_CFGDATA, data); })
|
||||
|
||||
|
||||
|
||||
#endif /* _PPC_BOOT_DCR_H_ */
|
||||
372
arch/powerpc/boot/devtree.c
Normal file
372
arch/powerpc/boot/devtree.c
Normal file
|
|
@ -0,0 +1,372 @@
|
|||
/*
|
||||
* devtree.c - convenience functions for device tree manipulation
|
||||
* Copyright 2007 David Gibson, IBM Corporation.
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Authors: David Gibson <david@gibson.dropbear.id.au>
|
||||
* Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "ops.h"
|
||||
|
||||
void dt_fixup_memory(u64 start, u64 size)
|
||||
{
|
||||
void *root, *memory;
|
||||
int naddr, nsize, i;
|
||||
u32 memreg[4];
|
||||
|
||||
root = finddevice("/");
|
||||
if (getprop(root, "#address-cells", &naddr, sizeof(naddr)) < 0)
|
||||
naddr = 2;
|
||||
if (naddr < 1 || naddr > 2)
|
||||
fatal("Can't cope with #address-cells == %d in /\n\r", naddr);
|
||||
|
||||
if (getprop(root, "#size-cells", &nsize, sizeof(nsize)) < 0)
|
||||
nsize = 1;
|
||||
if (nsize < 1 || nsize > 2)
|
||||
fatal("Can't cope with #size-cells == %d in /\n\r", nsize);
|
||||
|
||||
i = 0;
|
||||
if (naddr == 2)
|
||||
memreg[i++] = start >> 32;
|
||||
memreg[i++] = start & 0xffffffff;
|
||||
if (nsize == 2)
|
||||
memreg[i++] = size >> 32;
|
||||
memreg[i++] = size & 0xffffffff;
|
||||
|
||||
memory = finddevice("/memory");
|
||||
if (! memory) {
|
||||
memory = create_node(NULL, "memory");
|
||||
setprop_str(memory, "device_type", "memory");
|
||||
}
|
||||
|
||||
printf("Memory <- <0x%x", memreg[0]);
|
||||
for (i = 1; i < (naddr + nsize); i++)
|
||||
printf(" 0x%x", memreg[i]);
|
||||
printf("> (%ldMB)\n\r", (unsigned long)(size >> 20));
|
||||
|
||||
setprop(memory, "reg", memreg, (naddr + nsize)*sizeof(u32));
|
||||
}
|
||||
|
||||
#define MHZ(x) ((x + 500000) / 1000000)
|
||||
|
||||
void dt_fixup_cpu_clocks(u32 cpu, u32 tb, u32 bus)
|
||||
{
|
||||
void *devp = NULL;
|
||||
|
||||
printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu));
|
||||
printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb));
|
||||
if (bus > 0)
|
||||
printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus));
|
||||
|
||||
while ((devp = find_node_by_devtype(devp, "cpu"))) {
|
||||
setprop_val(devp, "clock-frequency", cpu);
|
||||
setprop_val(devp, "timebase-frequency", tb);
|
||||
if (bus > 0)
|
||||
setprop_val(devp, "bus-frequency", bus);
|
||||
}
|
||||
|
||||
timebase_period_ns = 1000000000 / tb;
|
||||
}
|
||||
|
||||
void dt_fixup_clock(const char *path, u32 freq)
|
||||
{
|
||||
void *devp = finddevice(path);
|
||||
|
||||
if (devp) {
|
||||
printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq));
|
||||
setprop_val(devp, "clock-frequency", freq);
|
||||
}
|
||||
}
|
||||
|
||||
void dt_fixup_mac_address_by_alias(const char *alias, const u8 *addr)
|
||||
{
|
||||
void *devp = find_node_by_alias(alias);
|
||||
|
||||
if (devp) {
|
||||
printf("%s: local-mac-address <-"
|
||||
" %02x:%02x:%02x:%02x:%02x:%02x\n\r", alias,
|
||||
addr[0], addr[1], addr[2],
|
||||
addr[3], addr[4], addr[5]);
|
||||
|
||||
setprop(devp, "local-mac-address", addr, 6);
|
||||
}
|
||||
}
|
||||
|
||||
void dt_fixup_mac_address(u32 index, const u8 *addr)
|
||||
{
|
||||
void *devp = find_node_by_prop_value(NULL, "linux,network-index",
|
||||
(void*)&index, sizeof(index));
|
||||
|
||||
if (devp) {
|
||||
printf("ENET%d: local-mac-address <-"
|
||||
" %02x:%02x:%02x:%02x:%02x:%02x\n\r", index,
|
||||
addr[0], addr[1], addr[2],
|
||||
addr[3], addr[4], addr[5]);
|
||||
|
||||
setprop(devp, "local-mac-address", addr, 6);
|
||||
}
|
||||
}
|
||||
|
||||
void __dt_fixup_mac_addresses(u32 startindex, ...)
|
||||
{
|
||||
va_list ap;
|
||||
u32 index = startindex;
|
||||
const u8 *addr;
|
||||
|
||||
va_start(ap, startindex);
|
||||
|
||||
while ((addr = va_arg(ap, const u8 *)))
|
||||
dt_fixup_mac_address(index++, addr);
|
||||
|
||||
va_end(ap);
|
||||
}
|
||||
|
||||
#define MAX_ADDR_CELLS 4
|
||||
|
||||
void dt_get_reg_format(void *node, u32 *naddr, u32 *nsize)
|
||||
{
|
||||
if (getprop(node, "#address-cells", naddr, 4) != 4)
|
||||
*naddr = 2;
|
||||
if (getprop(node, "#size-cells", nsize, 4) != 4)
|
||||
*nsize = 1;
|
||||
}
|
||||
|
||||
static void copy_val(u32 *dest, u32 *src, int naddr)
|
||||
{
|
||||
int pad = MAX_ADDR_CELLS - naddr;
|
||||
|
||||
memset(dest, 0, pad * 4);
|
||||
memcpy(dest + pad, src, naddr * 4);
|
||||
}
|
||||
|
||||
static int sub_reg(u32 *reg, u32 *sub)
|
||||
{
|
||||
int i, borrow = 0;
|
||||
|
||||
for (i = MAX_ADDR_CELLS - 1; i >= 0; i--) {
|
||||
int prev_borrow = borrow;
|
||||
borrow = reg[i] < sub[i] + prev_borrow;
|
||||
reg[i] -= sub[i] + prev_borrow;
|
||||
}
|
||||
|
||||
return !borrow;
|
||||
}
|
||||
|
||||
static int add_reg(u32 *reg, u32 *add, int naddr)
|
||||
{
|
||||
int i, carry = 0;
|
||||
|
||||
for (i = MAX_ADDR_CELLS - 1; i >= MAX_ADDR_CELLS - naddr; i--) {
|
||||
u64 tmp = (u64)reg[i] + add[i] + carry;
|
||||
carry = tmp >> 32;
|
||||
reg[i] = (u32)tmp;
|
||||
}
|
||||
|
||||
return !carry;
|
||||
}
|
||||
|
||||
/* It is assumed that if the first byte of reg fits in a
|
||||
* range, then the whole reg block fits.
|
||||
*/
|
||||
static int compare_reg(u32 *reg, u32 *range, u32 *rangesize)
|
||||
{
|
||||
int i;
|
||||
u32 end;
|
||||
|
||||
for (i = 0; i < MAX_ADDR_CELLS; i++) {
|
||||
if (reg[i] < range[i])
|
||||
return 0;
|
||||
if (reg[i] > range[i])
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < MAX_ADDR_CELLS; i++) {
|
||||
end = range[i] + rangesize[i];
|
||||
|
||||
if (reg[i] < end)
|
||||
break;
|
||||
if (reg[i] > end)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return reg[i] != end;
|
||||
}
|
||||
|
||||
/* reg must be MAX_ADDR_CELLS */
|
||||
static int find_range(u32 *reg, u32 *ranges, int nregaddr,
|
||||
int naddr, int nsize, int buflen)
|
||||
{
|
||||
int nrange = nregaddr + naddr + nsize;
|
||||
int i;
|
||||
|
||||
for (i = 0; i + nrange <= buflen; i += nrange) {
|
||||
u32 range_addr[MAX_ADDR_CELLS];
|
||||
u32 range_size[MAX_ADDR_CELLS];
|
||||
|
||||
copy_val(range_addr, ranges + i, nregaddr);
|
||||
copy_val(range_size, ranges + i + nregaddr + naddr, nsize);
|
||||
|
||||
if (compare_reg(reg, range_addr, range_size))
|
||||
return i;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Currently only generic buses without special encodings are supported.
|
||||
* In particular, PCI is not supported. Also, only the beginning of the
|
||||
* reg block is tracked; size is ignored except in ranges.
|
||||
*/
|
||||
static u32 prop_buf[MAX_PROP_LEN / 4];
|
||||
|
||||
static int dt_xlate(void *node, int res, int reglen, unsigned long *addr,
|
||||
unsigned long *size)
|
||||
{
|
||||
u32 last_addr[MAX_ADDR_CELLS];
|
||||
u32 this_addr[MAX_ADDR_CELLS];
|
||||
void *parent;
|
||||
u64 ret_addr, ret_size;
|
||||
u32 naddr, nsize, prev_naddr, prev_nsize;
|
||||
int buflen, offset;
|
||||
|
||||
parent = get_parent(node);
|
||||
if (!parent)
|
||||
return 0;
|
||||
|
||||
dt_get_reg_format(parent, &naddr, &nsize);
|
||||
|
||||
if (nsize > 2)
|
||||
return 0;
|
||||
|
||||
offset = (naddr + nsize) * res;
|
||||
|
||||
if (reglen < offset + naddr + nsize ||
|
||||
MAX_PROP_LEN < (offset + naddr + nsize) * 4)
|
||||
return 0;
|
||||
|
||||
copy_val(last_addr, prop_buf + offset, naddr);
|
||||
|
||||
ret_size = prop_buf[offset + naddr];
|
||||
if (nsize == 2) {
|
||||
ret_size <<= 32;
|
||||
ret_size |= prop_buf[offset + naddr + 1];
|
||||
}
|
||||
|
||||
for (;;) {
|
||||
prev_naddr = naddr;
|
||||
prev_nsize = nsize;
|
||||
node = parent;
|
||||
|
||||
parent = get_parent(node);
|
||||
if (!parent)
|
||||
break;
|
||||
|
||||
dt_get_reg_format(parent, &naddr, &nsize);
|
||||
|
||||
buflen = getprop(node, "ranges", prop_buf,
|
||||
sizeof(prop_buf));
|
||||
if (buflen == 0)
|
||||
continue;
|
||||
if (buflen < 0 || buflen > sizeof(prop_buf))
|
||||
return 0;
|
||||
|
||||
offset = find_range(last_addr, prop_buf, prev_naddr,
|
||||
naddr, prev_nsize, buflen / 4);
|
||||
|
||||
if (offset < 0)
|
||||
return 0;
|
||||
|
||||
copy_val(this_addr, prop_buf + offset, prev_naddr);
|
||||
|
||||
if (!sub_reg(last_addr, this_addr))
|
||||
return 0;
|
||||
|
||||
copy_val(this_addr, prop_buf + offset + prev_naddr, naddr);
|
||||
|
||||
if (!add_reg(last_addr, this_addr, naddr))
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (naddr > 2)
|
||||
return 0;
|
||||
|
||||
ret_addr = ((u64)last_addr[2] << 32) | last_addr[3];
|
||||
|
||||
if (sizeof(void *) == 4 &&
|
||||
(ret_addr >= 0x100000000ULL || ret_size > 0x100000000ULL ||
|
||||
ret_addr + ret_size > 0x100000000ULL))
|
||||
return 0;
|
||||
|
||||
*addr = ret_addr;
|
||||
if (size)
|
||||
*size = ret_size;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int dt_xlate_reg(void *node, int res, unsigned long *addr, unsigned long *size)
|
||||
{
|
||||
int reglen;
|
||||
|
||||
reglen = getprop(node, "reg", prop_buf, sizeof(prop_buf)) / 4;
|
||||
return dt_xlate(node, res, reglen, addr, size);
|
||||
}
|
||||
|
||||
int dt_xlate_addr(void *node, u32 *buf, int buflen, unsigned long *xlated_addr)
|
||||
{
|
||||
|
||||
if (buflen > sizeof(prop_buf))
|
||||
return 0;
|
||||
|
||||
memcpy(prop_buf, buf, buflen);
|
||||
return dt_xlate(node, 0, buflen / 4, xlated_addr, NULL);
|
||||
}
|
||||
|
||||
int dt_is_compatible(void *node, const char *compat)
|
||||
{
|
||||
char *buf = (char *)prop_buf;
|
||||
int len, pos;
|
||||
|
||||
len = getprop(node, "compatible", buf, MAX_PROP_LEN);
|
||||
if (len < 0)
|
||||
return 0;
|
||||
|
||||
for (pos = 0; pos < len; pos++) {
|
||||
if (!strcmp(buf + pos, compat))
|
||||
return 1;
|
||||
|
||||
pos += strnlen(&buf[pos], len - pos);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dt_get_virtual_reg(void *node, void **addr, int nres)
|
||||
{
|
||||
unsigned long xaddr;
|
||||
int n;
|
||||
|
||||
n = getprop(node, "virtual-reg", addr, nres * 4);
|
||||
if (n > 0)
|
||||
return n / 4;
|
||||
|
||||
for (n = 0; n < nres; n++) {
|
||||
if (!dt_xlate_reg(node, n, &xaddr, NULL))
|
||||
break;
|
||||
|
||||
addr[n] = (void *)xaddr;
|
||||
}
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
111
arch/powerpc/boot/div64.S
Normal file
111
arch/powerpc/boot/div64.S
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* Divide a 64-bit unsigned number by a 32-bit unsigned number.
|
||||
* This routine assumes that the top 32 bits of the dividend are
|
||||
* non-zero to start with.
|
||||
* On entry, r3 points to the dividend, which get overwritten with
|
||||
* the 64-bit quotient, and r4 contains the divisor.
|
||||
* On exit, r3 contains the remainder.
|
||||
*
|
||||
* Copyright (C) 2002 Paul Mackerras, IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
#include "ppc_asm.h"
|
||||
|
||||
.globl __div64_32
|
||||
__div64_32:
|
||||
lwz r5,0(r3) # get the dividend into r5/r6
|
||||
lwz r6,4(r3)
|
||||
cmplw r5,r4
|
||||
li r7,0
|
||||
li r8,0
|
||||
blt 1f
|
||||
divwu r7,r5,r4 # if dividend.hi >= divisor,
|
||||
mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor
|
||||
subf. r5,r0,r5 # dividend.hi %= divisor
|
||||
beq 3f
|
||||
1: mr r11,r5 # here dividend.hi != 0
|
||||
andis. r0,r5,0xc000
|
||||
bne 2f
|
||||
cntlzw r0,r5 # we are shifting the dividend right
|
||||
li r10,-1 # to make it < 2^32, and shifting
|
||||
srw r10,r10,r0 # the divisor right the same amount,
|
||||
addc r9,r4,r10 # rounding up (so the estimate cannot
|
||||
andc r11,r6,r10 # ever be too large, only too small)
|
||||
andc r9,r9,r10
|
||||
addze r9,r9
|
||||
or r11,r5,r11
|
||||
rotlw r9,r9,r0
|
||||
rotlw r11,r11,r0
|
||||
divwu r11,r11,r9 # then we divide the shifted quantities
|
||||
2: mullw r10,r11,r4 # to get an estimate of the quotient,
|
||||
mulhwu r9,r11,r4 # multiply the estimate by the divisor,
|
||||
subfc r6,r10,r6 # take the product from the divisor,
|
||||
add r8,r8,r11 # and add the estimate to the accumulated
|
||||
subfe. r5,r9,r5 # quotient
|
||||
bne 1b
|
||||
3: cmplw r6,r4
|
||||
blt 4f
|
||||
divwu r0,r6,r4 # perform the remaining 32-bit division
|
||||
mullw r10,r0,r4 # and get the remainder
|
||||
add r8,r8,r0
|
||||
subf r6,r10,r6
|
||||
4: stw r7,0(r3) # return the quotient in *r3
|
||||
stw r8,4(r3)
|
||||
mr r3,r6 # return the remainder in r3
|
||||
blr
|
||||
|
||||
/*
|
||||
* Extended precision shifts.
|
||||
*
|
||||
* Updated to be valid for shift counts from 0 to 63 inclusive.
|
||||
* -- Gabriel
|
||||
*
|
||||
* R3/R4 has 64 bit value
|
||||
* R5 has shift count
|
||||
* result in R3/R4
|
||||
*
|
||||
* ashrdi3: arithmetic right shift (sign propagation)
|
||||
* lshrdi3: logical right shift
|
||||
* ashldi3: left shift
|
||||
*/
|
||||
.globl __ashrdi3
|
||||
__ashrdi3:
|
||||
subfic r6,r5,32
|
||||
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
||||
addi r7,r5,32 # could be xori, or addi with -32
|
||||
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
||||
rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
|
||||
sraw r7,r3,r7 # t2 = MSW >> (count-32)
|
||||
or r4,r4,r6 # LSW |= t1
|
||||
slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
|
||||
sraw r3,r3,r5 # MSW = MSW >> count
|
||||
or r4,r4,r7 # LSW |= t2
|
||||
blr
|
||||
|
||||
.globl __ashldi3
|
||||
__ashldi3:
|
||||
subfic r6,r5,32
|
||||
slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
|
||||
addi r7,r5,32 # could be xori, or addi with -32
|
||||
srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
|
||||
slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
|
||||
or r3,r3,r6 # MSW |= t1
|
||||
slw r4,r4,r5 # LSW = LSW << count
|
||||
or r3,r3,r7 # MSW |= t2
|
||||
blr
|
||||
|
||||
.globl __lshrdi3
|
||||
__lshrdi3:
|
||||
subfic r6,r5,32
|
||||
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
||||
addi r7,r5,32 # could be xori, or addi with -32
|
||||
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
||||
srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
|
||||
or r4,r4,r6 # LSW |= t1
|
||||
srw r3,r3,r5 # MSW = MSW >> count
|
||||
or r4,r4,r7 # LSW |= t2
|
||||
blr
|
||||
142
arch/powerpc/boot/dts/a3m071.dts
Normal file
142
arch/powerpc/boot/dts/a3m071.dts
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* a3m071 board Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* Copyright (C) 2011 DENX Software Engineering GmbH
|
||||
* Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "mpc5200b.dtsi"
|
||||
|
||||
&gpt0 { fsl,has-wdt; };
|
||||
|
||||
/ {
|
||||
model = "anonymous,a3m071";
|
||||
compatible = "anonymous,a3m071";
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <0>; /* From boot loader */
|
||||
system-frequency = <0>; /* From boot loader */
|
||||
|
||||
spi@f00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb: usb@1000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2000 {
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
};
|
||||
|
||||
psc@2200 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2400 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2600 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2800 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2c00 { // PSC6
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2c00 0x100>;
|
||||
interrupts = <2 4 0>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
phy0: ethernet-phy@3 {
|
||||
reg = <0x03>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
localbus {
|
||||
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xfc000000 0x02000000
|
||||
3 0 0xe9000000 0x00080000
|
||||
5 0 0xe8000000 0x00010000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0 0x0 0x02000000>;
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <2>;
|
||||
partition@0x0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@0x00040000 {
|
||||
label = "env";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
};
|
||||
partition@0x00060000 {
|
||||
label = "dtb";
|
||||
reg = <0x00060000 0x00020000>;
|
||||
};
|
||||
partition@0x00080000 {
|
||||
label = "kernel";
|
||||
reg = <0x00080000 0x00500000>;
|
||||
};
|
||||
partition@0x00580000 {
|
||||
label = "root";
|
||||
reg = <0x00580000 0x00A80000>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga@3,0 {
|
||||
compatible = "anonymous,a3m071-fpga";
|
||||
reg = <3 0x0 0x00080000
|
||||
5 0x0 0x00010000>;
|
||||
interrupts = <0 0 3>; /* level low */
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
151
arch/powerpc/boot/dts/a4m072.dts
Normal file
151
arch/powerpc/boot/dts/a4m072.dts
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* a4m072 board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2011 DENX Software Engineering GmbH
|
||||
* Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "mpc5200b.dtsi"
|
||||
|
||||
&gpt0 { fsl,has-wdt; };
|
||||
&gpt3 { gpio-controller; };
|
||||
&gpt4 { gpio-controller; };
|
||||
&gpt5 { gpio-controller; };
|
||||
|
||||
/ {
|
||||
model = "anonymous,a4m072";
|
||||
compatible = "anonymous,a4m072";
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <0>; /* From boot loader */
|
||||
system-frequency = <0>; /* From boot loader */
|
||||
|
||||
cdm@200 {
|
||||
fsl,init-ext-48mhz-en = <0x0>;
|
||||
fsl,init-fd-enable = <0x01>;
|
||||
fsl,init-fd-counters = <0x3333>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2000 {
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
};
|
||||
|
||||
psc@2200 {
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2200 0x100>;
|
||||
interrupts = <2 2 0>;
|
||||
};
|
||||
|
||||
psc@2400 {
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <2 3 0>;
|
||||
};
|
||||
|
||||
psc@2600 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2800 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2c00 {
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2c00 0x100>;
|
||||
interrupts = <2 4 0>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
phy0: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
interrupts = <1 2 0>; /* IRQ 2 active low */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
hwmon@2e {
|
||||
compatible = "nsc,lm87";
|
||||
reg = <0x2e>;
|
||||
};
|
||||
rtc@51 {
|
||||
compatible = "nxp,rtc8564";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
localbus {
|
||||
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xfe000000 0x02000000
|
||||
1 0 0x62000000 0x00400000
|
||||
2 0 0x64000000 0x00200000
|
||||
3 0 0x66000000 0x01000000
|
||||
6 0 0x68000000 0x01000000
|
||||
7 0 0x6a000000 0x00000004>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
};
|
||||
sram0@1,0 {
|
||||
compatible = "mtd-ram";
|
||||
reg = <1 0x00000 0x00400000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200-pci";
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x16 */
|
||||
0xc000 0 0 1 &mpc5200_pic 1 3 3
|
||||
0xc000 0 0 2 &mpc5200_pic 1 3 3
|
||||
0xc000 0 0 3 &mpc5200_pic 1 3 3
|
||||
0xc000 0 0 4 &mpc5200_pic 1 3 3>;
|
||||
clock-frequency = <0>; /* From boot loader */
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
399
arch/powerpc/boot/dts/ac14xx.dts
Normal file
399
arch/powerpc/boot/dts/ac14xx.dts
Normal file
|
|
@ -0,0 +1,399 @@
|
|||
/*
|
||||
* Device Tree Source for the MPC5121e based ac14xx board
|
||||
*
|
||||
* Copyright 2012 Anatolij Gustschin <agust@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
|
||||
#include <mpc5121.dtsi>
|
||||
|
||||
/ {
|
||||
model = "ac14xx";
|
||||
compatible = "ifm,ac14xx", "fsl,mpc5121";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial7;
|
||||
spi4 = &spi4;
|
||||
spi5 = &spi5;
|
||||
};
|
||||
|
||||
cpus {
|
||||
PowerPC,5121@0 {
|
||||
timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
|
||||
bus-frequency = <160000000>; /* 160 MHz csb bus */
|
||||
clock-frequency = <400000000>; /* 400 MHz ppc core */
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x10000000>; /* 256MB at 0 */
|
||||
};
|
||||
|
||||
nfc@40000000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
localbus@80000020 {
|
||||
ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
|
||||
0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
|
||||
0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
|
||||
0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
|
||||
0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
|
||||
0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "dtb-kernel-production";
|
||||
reg = <0x00000000 0x00400000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "filesystem-production";
|
||||
reg = <0x00400000 0x03400000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "recovery";
|
||||
reg = <0x03800000 0x00700000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "uboot-code";
|
||||
reg = <0x03f00000 0x00040000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "uboot-env1";
|
||||
reg = <0x03f40000 0x00020000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "uboot-env2";
|
||||
reg = <0x03f60000 0x00020000>;
|
||||
};
|
||||
};
|
||||
|
||||
fram@1,0 {
|
||||
compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
|
||||
reg = <1 0x00000000 0x00010000>;
|
||||
};
|
||||
|
||||
asi@2,0 {
|
||||
/* masters mapping: CS, CS offset, size */
|
||||
reg = <2 0x00000000 0x00080000
|
||||
6 0x00000000 0x00080000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ifm,ac14xx-asi-fpga";
|
||||
gpios = <
|
||||
&gpio_pic 26 0 /* prog */
|
||||
&gpio_pic 27 0 /* done */
|
||||
&gpio_pic 10 0 /* reset */
|
||||
>;
|
||||
|
||||
master@1 {
|
||||
interrupts = <20 0x2>;
|
||||
interrupt-parent = <&gpio_pic>;
|
||||
chipselect = <2 0x00009000 0x00009100>;
|
||||
label = "AS-i master 1";
|
||||
};
|
||||
|
||||
master@2 {
|
||||
interrupts = <21 0x2>;
|
||||
interrupt-parent = <&gpio_pic>;
|
||||
chipselect = <6 0x00009000 0x00009100>;
|
||||
label = "AS-i master 2";
|
||||
};
|
||||
};
|
||||
|
||||
netx@3,0 {
|
||||
compatible = "ifm,netx";
|
||||
reg = <0x3 0x00000000 0x00020000>;
|
||||
chipselect = <3 0x00101140 0x00203100>;
|
||||
interrupts = <17 0x8>;
|
||||
gpios = <&gpio_pic 15 0>;
|
||||
};
|
||||
|
||||
safety@5,0 {
|
||||
compatible = "ifm,safety";
|
||||
reg = <0x5 0x00000000 0x00010000>;
|
||||
chipselect = <5 0x00009000 0x00009100>;
|
||||
interrupts = <22 0x2>;
|
||||
interrupt-parent = <&gpio_pic>;
|
||||
gpios = <
|
||||
&gpio_pic 12 0 /* prog */
|
||||
&gpio_pic 11 0 /* done */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
osc {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@80000000 {
|
||||
bus-frequency = <80000000>; /* 80 MHz ips bus */
|
||||
|
||||
clock@f00 {
|
||||
compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO PIC:
|
||||
* interrupts cell = <pin nr, sense>
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
gpio_pic: gpio@1100 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sdhc@1500 {
|
||||
cd-gpios = <&gpio_pic 23 0>; /* card detect */
|
||||
wp-gpios = <&gpio_pic 24 0>; /* write protect */
|
||||
wp-inverted; /* WP active high */
|
||||
};
|
||||
|
||||
i2c@1700 {
|
||||
/* use Fast-mode */
|
||||
clock-frequency = <400000>;
|
||||
|
||||
at24@30 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x30>;
|
||||
};
|
||||
|
||||
at24@31 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x31>;
|
||||
};
|
||||
|
||||
temp@48 {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
at24@51 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
at24@52 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
at24@53 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x53>;
|
||||
};
|
||||
|
||||
at24@54 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
at24@55 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x55>;
|
||||
};
|
||||
|
||||
at24@56 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x56>;
|
||||
};
|
||||
|
||||
at24@57 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x57>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
axe_pic: axe-base@2000 {
|
||||
compatible = "fsl,mpc5121-axe-base";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
axe-app {
|
||||
compatible = "fsl,mpc5121-axe-app";
|
||||
interrupt-parent = <&axe_pic>;
|
||||
interrupts = <
|
||||
/* soft interrupts */
|
||||
0 0x0 1 0x0 2 0x0 3 0x0
|
||||
4 0x0 5 0x0 6 0x0 7 0x0
|
||||
/* fifo interrupts */
|
||||
8 0x0 9 0x0 10 0x0 11 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
display@2100 {
|
||||
edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
|
||||
0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
|
||||
1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
|
||||
01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
|
||||
21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
|
||||
3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
|
||||
54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
|
||||
00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
|
||||
};
|
||||
|
||||
can@2300 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can@2380 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
viu@2400 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@2800 {
|
||||
phy0: ethernet-phy@1f {
|
||||
compatible = "smsc,lan8700";
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
enet: ethernet@2800 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
usb@3000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@4000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* PSC3 serial port A, aka ttyPSC0 */
|
||||
serial0: psc@11300 {
|
||||
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
|
||||
fsl,rx-fifo-size = <512>;
|
||||
fsl,tx-fifo-size = <512>;
|
||||
};
|
||||
|
||||
/* PSC4 in SPI mode */
|
||||
spi4: psc@11400 {
|
||||
compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
|
||||
fsl,rx-fifo-size = <768>;
|
||||
fsl,tx-fifo-size = <768>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
num-cs = <1>;
|
||||
cs-gpios = <&gpio_pic 25 0>;
|
||||
|
||||
flash: m25p128@0 {
|
||||
compatible = "st,m25p128";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "spi-flash0";
|
||||
reg = <0x00000000 0x01000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* PSC5 in SPI mode */
|
||||
spi5: psc@11500 {
|
||||
compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
|
||||
fsl,mode = "spi-master";
|
||||
fsl,rx-fifo-size = <128>;
|
||||
fsl,tx-fifo-size = <128>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
lcd@0 {
|
||||
compatible = "ilitek,ili922x";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
/* PSC7 serial port C, aka ttyPSC2 */
|
||||
serial7: psc@11700 {
|
||||
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
|
||||
fsl,rx-fifo-size = <512>;
|
||||
fsl,tx-fifo-size = <512>;
|
||||
};
|
||||
|
||||
matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <1>;
|
||||
gpio-activelow;
|
||||
col-gpios-binary;
|
||||
col-switch-delay-ms = <200>;
|
||||
|
||||
col-gpios = <&gpio_pic 1 0>; /* pin1 */
|
||||
|
||||
row-gpios = <&gpio_pic 2 0 /* pin2 */
|
||||
&gpio_pic 3 0 /* pin3 */
|
||||
&gpio_pic 4 0>; /* pin4 */
|
||||
|
||||
linux,keymap = <0x0000006e /* FN LEFT */
|
||||
0x01000067 /* UP */
|
||||
0x02000066 /* FN RIGHT */
|
||||
0x00010069 /* LEFT */
|
||||
0x0101006a /* DOWN */
|
||||
0x0201006c>; /* RIGHT */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
backlight {
|
||||
label = "backlight";
|
||||
gpios = <&gpio_pic 0 0>;
|
||||
default-state = "keep";
|
||||
};
|
||||
green {
|
||||
label = "green";
|
||||
gpios = <&gpio_pic 18 0>;
|
||||
default-state = "keep";
|
||||
};
|
||||
red {
|
||||
label = "red";
|
||||
gpios = <&gpio_pic 19 0>;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
224
arch/powerpc/boot/dts/acadia.dts
Normal file
224
arch/powerpc/boot/dts/acadia.dts
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Acadia (405EZ)
|
||||
*
|
||||
* Copyright IBM Corp. 2008
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,acadia";
|
||||
compatible = "amcc,acadia";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EZ";
|
||||
reg = <0x0>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
timebase-frequency = <0>; /* Filled in by wrapper */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>;
|
||||
d-cache-size = <16384>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>; /* Filled in by wrapper */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405ez", "ibm,uic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
cell-index = <0>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-405ez", "ibm,plb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405ez", "ibm,mcmal";
|
||||
dcr-reg = <0x380 0x62>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
/* 405EZ has only 3 interrupts to the UIC, as
|
||||
* SERR, TXDE, and RXDE are or'd together into
|
||||
* one UIC bit
|
||||
*/
|
||||
interrupts = <
|
||||
0x13 0x4 /* TXEOB */
|
||||
0x15 0x4 /* RXEOB */
|
||||
0x12 0x4 /* SERR, TXDE, RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ez", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dcr-reg = <0x0a 0x05>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x8>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x5 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x8>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x6 0x4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405ez", "ibm,iic";
|
||||
reg = <0xef600500 0x11>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0xa 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@ef600700 {
|
||||
compatible = "ibm,gpio-405ez";
|
||||
reg = <0xef600700 0x20>;
|
||||
};
|
||||
|
||||
GPIO1: gpio@ef600800 {
|
||||
compatible = "ibm,gpio-405ez";
|
||||
reg = <0xef600800 0x20>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ez", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0x10 0x4 /* Ethernet */
|
||||
0x11 0x4 /* Ethernet Wake up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by wrapper */
|
||||
reg = <0xef600900 0x70>;
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "mii";
|
||||
phy-map = <0x0>;
|
||||
};
|
||||
|
||||
CAN0: can@ef601000 {
|
||||
compatible = "amcc,can-405ez";
|
||||
reg = <0xef601000 0x620>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
CAN1: can@ef601800 {
|
||||
compatible = "amcc,can-405ez";
|
||||
reg = <0xef601800 0x620>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x8 0x4>;
|
||||
};
|
||||
|
||||
cameleon@ef602000 {
|
||||
compatible = "amcc,cameleon-405ez";
|
||||
reg = <0xef602000 0x800>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0xb 0x4 0xc 0x4>;
|
||||
};
|
||||
|
||||
ieee1588@ef602800 {
|
||||
compatible = "amcc,ieee1588-405ez";
|
||||
reg = <0xef602800 0x60>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x4 0x4>;
|
||||
/* This thing is a bit weird. It has it's own UIC
|
||||
* that it uses to generate snapshot triggers. We
|
||||
* don't really support this device yet, and it needs
|
||||
* work to figure this out.
|
||||
*/
|
||||
dcr-reg = <0xe0 0x9>;
|
||||
};
|
||||
|
||||
usb@ef603000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0xef603000 0x80>;
|
||||
interrupts-parent = <&UIC0>;
|
||||
interrupts = <0xd 0x4 0xe 0x4>;
|
||||
};
|
||||
|
||||
dac@ef603300 {
|
||||
compatible = "amcc,dac-405ez";
|
||||
reg = <0xef603300 0x40>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x18 0x4>;
|
||||
};
|
||||
|
||||
adc@ef603400 {
|
||||
compatible = "amcc,adc-405ez";
|
||||
reg = <0xef603400 0x40>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x17 0x4>;
|
||||
};
|
||||
|
||||
spi@ef603500 {
|
||||
compatible = "amcc,spi-405ez";
|
||||
reg = <0xef603500 0x100>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x9 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ez", "ibm,ebc";
|
||||
dcr-reg = <0x12 0x2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
183
arch/powerpc/boot/dts/adder875-redboot.dts
Normal file
183
arch/powerpc/boot/dts/adder875-redboot.dts
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* Device Tree Source for MPC885 ADS running RedBoot
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Analogue & Micro Adder MPC875";
|
||||
compatible = "analogue-and-micro,adder875";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
console = &console;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,875@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus@fa200100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xfa200100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xfe000000 0x00800000
|
||||
2 0 0xfa100000 0x00008000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@fa200000 {
|
||||
compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xfa200000 0x00004000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary until get_immrbase() is fixed.
|
||||
reg = <0xfa200000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x24>;
|
||||
compatible = "fsl,mpc875-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus";
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc875-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
clock-frequency = <50000000>;
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc875-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
console: serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc875-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x0090>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &console;
|
||||
};
|
||||
};
|
||||
182
arch/powerpc/boot/dts/adder875-uboot.dts
Normal file
182
arch/powerpc/boot/dts/adder875-uboot.dts
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* Device Tree Source for MPC885 ADS running U-Boot
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Analogue & Micro Adder MPC875";
|
||||
compatible = "analogue-and-micro,adder875";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
console = &console;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,875@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus@ff000100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xff000100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xfe000000 0x01000000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@ff000000 {
|
||||
compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff000000 0x00004000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary until get_immrbase() is fixed.
|
||||
reg = <0xff000000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x24>;
|
||||
compatible = "fsl,mpc875-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus";
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc875-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
clock-frequency = <50000000>;
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc875-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
console: serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc875-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x0090>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &console;
|
||||
};
|
||||
};
|
||||
415
arch/powerpc/boot/dts/akebono.dts
Normal file
415
arch/powerpc/boot/dts/akebono.dts
Normal file
|
|
@ -0,0 +1,415 @@
|
|||
/*
|
||||
* Device Tree Source for IBM Embedded PPC 476 Platform
|
||||
*
|
||||
* Copyright © 2013 Tony Breeds IBM Corporation
|
||||
* Copyright © 2013 Alistair Popple IBM Corporation
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x01f00000 0x00100000; // spin table
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "ibm,akebono";
|
||||
compatible = "ibm,akebono", "ibm,476gtr";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
serial0 = &UART0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <0>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "ok";
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <1>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "disabled";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x01f00000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
|
||||
};
|
||||
|
||||
MPIC: interrupt-controller {
|
||||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0xffc00000 0x00040000>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
single-cpu-affinity;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb6";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
clock-frequency = <200000000>; // 200Mhz
|
||||
|
||||
HSTA0: hsta@310000e0000 {
|
||||
compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
|
||||
reg = <0x310 0x000e0000 0x0 0xf0>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <108 0
|
||||
109 0
|
||||
110 0
|
||||
111 0
|
||||
112 0
|
||||
113 0
|
||||
114 0
|
||||
115 0
|
||||
116 0
|
||||
117 0
|
||||
118 0
|
||||
119 0
|
||||
120 0
|
||||
121 0
|
||||
122 0
|
||||
123 0>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
|
||||
dcr-reg = <0xc0000000 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = < /*TXEOB*/ 77 0x4
|
||||
/*RXEOB*/ 78 0x4
|
||||
/*SERR*/ 76 0x4
|
||||
/*TXDE*/ 79 0x4
|
||||
/*RXDE*/ 80 0x4>;
|
||||
};
|
||||
|
||||
SATA0: sata@30000010000 {
|
||||
compatible = "ibm,476gtr-ahci";
|
||||
reg = <0x300 0x00010000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <93 2>;
|
||||
};
|
||||
|
||||
EHCI0: ehci@30010000000 {
|
||||
compatible = "ibm,476gtr-ehci", "generic-ehci";
|
||||
reg = <0x300 0x10000000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <85 2>;
|
||||
};
|
||||
|
||||
SD0: sd@30000000000 {
|
||||
compatible = "ibm,476gtr-sdhci", "generic-sdhci";
|
||||
reg = <0x300 0x00000000 0x0 0x10000>;
|
||||
interrupts = <91 2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
};
|
||||
|
||||
OHCI0: ohci@30010010000 {
|
||||
compatible = "ibm,476gtr-ohci", "generic-ohci";
|
||||
reg = <0x300 0x10010000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <89 1>;
|
||||
};
|
||||
|
||||
OHCI1: ohci@30010020000 {
|
||||
compatible = "ibm,476gtr-ohci", "generic-ohci";
|
||||
reg = <0x300 0x10020000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <88 1>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-4xx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full
|
||||
* 32-bit range
|
||||
*/
|
||||
ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
|
||||
0x80000000 0x0000033f 0x80000000 0x80000000>;
|
||||
clock-frequency = <100000000>;
|
||||
|
||||
RGMII0: emac-rgmii-wol@50004 {
|
||||
compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
|
||||
reg = <0x50004 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@30000 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-476gtr", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
|
||||
/*Wake*/ 0x1 &MPIC 82 0x4>;
|
||||
reg = <0x30000 0x78>;
|
||||
|
||||
/* local-mac-address will normally be added by
|
||||
* the wrapper. If your device doesn't support
|
||||
* passing data to the wrapper (in the form
|
||||
* local-mac-addr=<hwaddr>) then you will need
|
||||
* to set it manually here. */
|
||||
//local-mac-address = [000000000000];
|
||||
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-wol-device = <&RGMII0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
UART0: serial@10000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16750", "ns16550";
|
||||
reg = <0x10000 0x00000008>;
|
||||
virtual-reg = <0xe8010000>;
|
||||
clock-frequency = <1851851>;
|
||||
current-speed = <38400>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <39 2>;
|
||||
};
|
||||
|
||||
IIC0: i2c@00000000 {
|
||||
compatible = "ibm,iic-476gtr", "ibm,iic";
|
||||
reg = <0x0 0x00000020>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <37 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80", "m41st85";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@00000100 {
|
||||
compatible = "ibm,iic-476gtr", "ibm,iic";
|
||||
reg = <0x100 0x00000020>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <38 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
avr@58 {
|
||||
compatible = "ibm,akebono-avr";
|
||||
reg = <0x58>;
|
||||
};
|
||||
};
|
||||
|
||||
FPGA0: fpga@ebc00000 {
|
||||
compatible = "ibm,akebono-fpga";
|
||||
reg = <0xebc00000 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@10100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xc0 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@20100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x100 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@18100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xe0 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE3: pciex@28100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x3>; /* port number */
|
||||
reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x120 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &UART0;
|
||||
};
|
||||
};
|
||||
173
arch/powerpc/boot/dts/amigaone.dts
Normal file
173
arch/powerpc/boot/dts/amigaone.dts
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* AmigaOne Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "AmigaOne";
|
||||
compatible = "eyetech,amigaone";
|
||||
coherency-off;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#cpus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // 33.3 MHz, from U-boot
|
||||
clock-frequency = <0>; // From U-boot
|
||||
bus-frequency = <0>; // From U-boot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; // From U-boot
|
||||
};
|
||||
|
||||
pci@80000000 {
|
||||
device_type = "pci";
|
||||
compatible = "mai-logic,articia-s";
|
||||
bus-frequency = <33333333>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
|
||||
0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
|
||||
0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA)
|
||||
// Configuration address and data register.
|
||||
reg = <0xfec00cf8 4
|
||||
0xfee00cfc 4>;
|
||||
8259-interrupt-acknowledge = <0xfef00000>;
|
||||
// Do not define a interrupt-parent here, if there is no
|
||||
// interrupt-map property.
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
isa@7 {
|
||||
device_type = "isa";
|
||||
compatible = "pciclass,0601";
|
||||
vendor-id = <0x00001106>;
|
||||
device-id = <0x00000686>;
|
||||
revision-id = <0x00000010>;
|
||||
class-code = <0x00060100>;
|
||||
subsystem-id = <0>;
|
||||
subsystem-vendor-id = <0>;
|
||||
devsel-speed = <0x00000001>;
|
||||
min-grant = <0>;
|
||||
max-latency = <0>;
|
||||
/* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
|
||||
ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>;
|
||||
interrupt-parent = <&i8259>;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
dma-controller@0 {
|
||||
compatible = "pnpPNP,200";
|
||||
reg = <1 0x00000000 0x00000020
|
||||
1 0x00000080 0x00000010
|
||||
1 0x000000c0 0x00000020>;
|
||||
};
|
||||
|
||||
i8259: interrupt-controller@20 {
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "pnpPNP,000";
|
||||
interrupt-controller;
|
||||
reg = <1 0x00000020 0x00000002
|
||||
1 0x000000a0 0x00000002
|
||||
1 0x000004d0 0x00000002>;
|
||||
reserved-interrupts = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
timer@40 {
|
||||
// Also adds pcspkr to platform devices.
|
||||
compatible = "pnpPNP,100";
|
||||
reg = <1 0x00000040 0x00000020>;
|
||||
};
|
||||
|
||||
8042@60 {
|
||||
device_type = "8042";
|
||||
reg = <1 0x00000060 0x00000001
|
||||
1 0x00000064 0x00000001>;
|
||||
interrupts = <1 3 12 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
keyboard@0 {
|
||||
compatible = "pnpPNP,303";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
mouse@1 {
|
||||
compatible = "pnpPNP,f03";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@70 {
|
||||
compatible = "pnpPNP,b00";
|
||||
reg = <1 0x00000070 0x00000002>;
|
||||
interrupts = <8 3>;
|
||||
};
|
||||
|
||||
serial@3f8 {
|
||||
device_type = "serial";
|
||||
compatible = "pnpPNP,501","pnpPNP,500";
|
||||
reg = <1 0x000003f8 0x00000008>;
|
||||
interrupts = <4 3>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
serial@2f8 {
|
||||
device_type = "serial";
|
||||
compatible = "pnpPNP,501","pnpPNP,500";
|
||||
reg = <1 0x000002f8 0x00000008>;
|
||||
interrupts = <3 3>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
parallel@378 {
|
||||
device_type = "parallel";
|
||||
// No ECP support for now, otherwise add "pnpPNP,401".
|
||||
compatible = "pnpPNP,400";
|
||||
reg = <1 0x00000378 0x00000003
|
||||
1 0x00000778 0x00000003>;
|
||||
};
|
||||
|
||||
fdc@3f0 {
|
||||
device_type = "fdc";
|
||||
compatible = "pnpPNP,700";
|
||||
reg = <1 0x000003f0 0x00000008>;
|
||||
interrupts = <6 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
disk@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/pci@80000000/isa@7/serial@3f8";
|
||||
};
|
||||
};
|
||||
355
arch/powerpc/boot/dts/arches.dts
Normal file
355
arch/powerpc/boot/dts/arches.dts
Normal file
|
|
@ -0,0 +1,355 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Arches (dual 460GT board)
|
||||
*
|
||||
* (C) Copyright 2008 Applied Micro Circuits Corporation
|
||||
* Victor Gallardo <vgallardo@amcc.com>
|
||||
* Adam Graham <agraham@amcc.com>
|
||||
*
|
||||
* Based on the glacier.dts file
|
||||
* Stefan Roese <sr@denx.de>
|
||||
* Copyright 2008 DENX Software Engineering
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,arches";
|
||||
compatible = "amcc,arches";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
ethernet2 = &EMAC2;
|
||||
serial0 = &UART0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460GT";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460gt";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460gt";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
|
||||
dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
|
||||
0x030 0x008>; /* L2 cache DCR's */
|
||||
cache-line-size = <32>; /* 32 bytes */
|
||||
cache-size = <262144>; /* L2, 256K */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <11 1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-460gt", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
CRYPTO: crypto@180000 {
|
||||
compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
|
||||
reg = <4 0x00180000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <3>;
|
||||
num-rx-chans = <24>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
desc-base-addr-high = <0x8>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460gt", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460gt", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl256n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x02000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <0x00400000 0x01b60000>;
|
||||
};
|
||||
partition@1f60000 {
|
||||
label = "env";
|
||||
reg = <0x01f60000 0x00040000>;
|
||||
};
|
||||
partition@1fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x01fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460gt", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
sttm@4a {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x4a>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x0 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460gt", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460gt", "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460gt", "ibm,tah";
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "sgmii";
|
||||
phy-map = <0xffffffff>;
|
||||
gpcs-address = <0x0000000a>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "sgmii";
|
||||
phy-map = <0x00000000>;
|
||||
gpcs-address = <0x0000000b>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
|
||||
EMAC2: ethernet@ef601100 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC2>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x16 0x4>;
|
||||
reg = <0xef601100 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <16>;
|
||||
cell-index = <2>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
||||
phy-mode = "sgmii";
|
||||
phy-map = <0x00000001>;
|
||||
gpcs-address = <0x0000000C>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
310
arch/powerpc/boot/dts/asp834x-redboot.dts
Normal file
310
arch/powerpc/boot/dts/asp834x-redboot.dts
Normal file
|
|
@ -0,0 +1,310 @@
|
|||
/*
|
||||
* Analogue & Micro ASP8347 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Codehermit
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "Analogue & Micro ASP8347E";
|
||||
compatible = "analogue-and-micro,asp8347e";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8347@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x8000000>; // 128MB at 0
|
||||
};
|
||||
|
||||
localbus@ff005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8347e-localbus",
|
||||
"fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xff005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xf0000000 0x02000000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc8349@ff000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xff000000 0x00100000>;
|
||||
reg = <0xff000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port0;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 08 e5 11 32 33 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
linux,network-index = <0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 08 e5 11 32 34 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
linux,network-index = <1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <400000000>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <400000000>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
|
||||
linux,stdout-path = &serial0;
|
||||
};
|
||||
|
||||
};
|
||||
50
arch/powerpc/boot/dts/b4420qds.dts
Normal file
50
arch/powerpc/boot/dts/b4420qds.dts
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* B4420DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/include/ "fsl/b4420si-pre.dtsi"
|
||||
/include/ "b4qds.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,B4420QDS";
|
||||
compatible = "fsl,B4420QDS";
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4420si-post.dtsi"
|
||||
223
arch/powerpc/boot/dts/b4860emu.dts
Normal file
223
arch/powerpc/boot/dts/b4860emu.dts
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* B4860 emulator Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl/e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4860";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "fsl,B4860QDS";
|
||||
compatible = "fsl,B4860EMU", "fsl,B4860QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 2>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 9>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 4>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 0>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
fsl,portid-mapping = <0x8000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 1>;
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <8 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4-device-config";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-i2c-0.dtsi"
|
||||
/include/ "fsl/qoriq-i2c-1.dtsi"
|
||||
/include/ "fsl/qoriq-duart-0.dtsi"
|
||||
/include/ "fsl/qoriq-duart-1.dtsi"
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4-l2-cache-controller";
|
||||
reg = <0xc20000 0x1000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
61
arch/powerpc/boot/dts/b4860qds.dts
Normal file
61
arch/powerpc/boot/dts/b4860qds.dts
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* B4860DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/b4860si-pre.dtsi"
|
||||
/include/ "b4qds.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,B4860QDS";
|
||||
compatible = "fsl,B4860QDS";
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
reg = <0xf 0xfe0c0000 0 0x11000>;
|
||||
|
||||
port1 {
|
||||
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
|
||||
};
|
||||
port2 {
|
||||
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4860si-post.dtsi"
|
||||
182
arch/powerpc/boot/dts/b4qds.dtsi
Normal file
182
arch/powerpc/boot/dts/b4qds.dtsi
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* B4420DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "fsl,B4QDS";
|
||||
compatible = "fsl,B4QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x2 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 10MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x00A00000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
/* 500MB for Root file System Image */
|
||||
reg = <0x00c00000 0x1F400000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
|
||||
reg = <3 0 0x300>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01052000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
};
|
||||
|
||||
sdhc@114000 {
|
||||
/*Disabled as there is no sdhc connector on B4420QDS board*/
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "at24,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@57 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x57>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb@210000 {
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
reg = <0xf 0xfe200000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4si-post.dtsi"
|
||||
300
arch/powerpc/boot/dts/bamboo.dts
Normal file
300
arch/powerpc/boot/dts/bamboo.dts
Normal file
|
|
@ -0,0 +1,300 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Bamboo
|
||||
*
|
||||
* Copyright (c) 2006, 2007 IBM Corp.
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* FIXME: Draft only!
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,bamboo";
|
||||
compatible = "amcc,bamboo";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
serial3 = &UART3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440EP";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440ep";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440ep";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440ep", "ibm,dma-440gp";
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Bamboo is oddball in the 44x world and doesn't use the ERPN
|
||||
* bits.
|
||||
*/
|
||||
ranges = <0x00000000 0x00000000 0x00000000 0x80000000
|
||||
0x80000000 0x00000000 0x80000000 0x80000000>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600500 0x00000008>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600600 0x00000008>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x4 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0xef600e00 0x00000070>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>;
|
||||
reg = <0xef600f00 0x00000070>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2 3>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
||||
usb@ef601000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0xef601000 0x00000080>;
|
||||
interrupts = <0x8 0x1 0x9 0x1>;
|
||||
interrupt-parent = < &UIC1 >;
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0xeed00000 0x00000004 /* IACK */
|
||||
0x00000000 0xeed00000 0x00000004 /* Special cycle */
|
||||
0x00000000 0xef400000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x40000000
|
||||
0x02000000 0x00000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* Bamboo has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
|
||||
|
||||
/* IDSEL 2 */
|
||||
0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
|
||||
|
||||
/* IDSEL 3 */
|
||||
0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
|
||||
|
||||
/* IDSEL 4 */
|
||||
0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
410
arch/powerpc/boot/dts/bluestone.dts
Normal file
410
arch/powerpc/boot/dts/bluestone.dts
Normal file
|
|
@ -0,0 +1,410 @@
|
|||
/*
|
||||
* Device Tree for Bluestone (APM821xx) board.
|
||||
*
|
||||
* Copyright (c) 2010, Applied Micro Circuits Corporation
|
||||
* Author: Tirumala R Marri <tmarri@apm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "apm,bluestone";
|
||||
compatible = "apm,bluestone";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,apm821xx";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
OCM: ocm@400040000 {
|
||||
compatible = "ibm,ocm";
|
||||
status = "ok";
|
||||
cell-index = <1>;
|
||||
/* configured in U-Boot */
|
||||
reg = <4 0x00040000 0x8000>; /* 32K */
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-apm821xx";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-apm821xx";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
|
||||
dcr-reg = <0x020 0x008
|
||||
0x030 0x008>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <262144>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <11 1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-apm821xx";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal2";
|
||||
descriptor-memory = "ocm";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x00400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "env";
|
||||
reg = <0x00180000 0x00020000>;
|
||||
};
|
||||
partition@1a0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x001a0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
ndfc@1,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000003 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* 2Gb Nand Flash */
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x00000000 0x00C00000>;
|
||||
};
|
||||
partition@c00000 {
|
||||
label = "environment";
|
||||
reg = <0x00C00000 0x00B00000>;
|
||||
};
|
||||
partition@1700000 {
|
||||
label = "kernel";
|
||||
reg = <0x01700000 0x00E00000>;
|
||||
};
|
||||
partition@2500000 {
|
||||
label = "root";
|
||||
reg = <0x02500000 0x08200000>;
|
||||
};
|
||||
partition@a700000 {
|
||||
label = "device-tree";
|
||||
reg = <0x0A700000 0x00B00000>;
|
||||
};
|
||||
partition@b200000 {
|
||||
label = "config";
|
||||
reg = <0x0B200000 0x00D00000>;
|
||||
};
|
||||
partition@bf00000 {
|
||||
label = "diag";
|
||||
reg = <0x0BF00000 0x00C00000>;
|
||||
};
|
||||
partition@cb00000 {
|
||||
label = "vendor";
|
||||
reg = <0x0CB00000 0x3500000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x9 0x8>;
|
||||
};
|
||||
sttm@4C {
|
||||
compatible = "adm,adm1032";
|
||||
reg = <0x4C>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii";
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600c00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600c00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <16384>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
MSI: ppc4xx-msi@C10000000 {
|
||||
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
|
||||
reg = < 0xC 0x10000000 0x100
|
||||
0xC 0x10000000 0x100>;
|
||||
sdr-base = <0x36C>;
|
||||
msi-data = <0x00004440>;
|
||||
msi-mask = <0x0000ffe0>;
|
||||
interrupts =<0 1 2 3 4 5 6 7>;
|
||||
interrupt-parent = <&MSI>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
msi-available-ranges = <0x0 0x100>;
|
||||
interrupt-map = <
|
||||
0 &UIC3 0x18 1
|
||||
1 &UIC3 0x19 1
|
||||
2 &UIC3 0x1A 1
|
||||
3 &UIC3 0x1B 1
|
||||
4 &UIC3 0x1C 1
|
||||
5 &UIC3 0x1D 1
|
||||
6 &UIC3 0x1E 1
|
||||
7 &UIC3 0x1F 1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
34
arch/powerpc/boot/dts/bsc9131rdb.dts
Normal file
34
arch/powerpc/boot/dts/bsc9131rdb.dts
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* BSC9131 RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "fsl/bsc9131si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,bsc9131rdb";
|
||||
compatible = "fsl,bsc9131rdb";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
board_ifc: ifc: ifc@ff71e000 {
|
||||
/* NAND Flash on board */
|
||||
ranges = <0x0 0x0 0x0 0xff800000 0x00004000>;
|
||||
reg = <0x0 0xff71e000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
board_soc: soc: soc@ff700000 {
|
||||
ranges = <0x0 0x0 0xff700000 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "bsc9131rdb.dtsi"
|
||||
/include/ "fsl/bsc9131si-post.dtsi"
|
||||
142
arch/powerpc/boot/dts/bsc9131rdb.dtsi
Normal file
142
arch/powerpc/boot/dts/bsc9131rdb.dtsi
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* BSC9131 RDB Device Tree Source stub (no addresses or top-level ranges)
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&board_ifc {
|
||||
|
||||
nand@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x0 0x0 0x4000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 3MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00300000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00300000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
/* 8MB for Linux Kernel Image */
|
||||
reg = <0x00400000 0x00800000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
/* Rest space for Root file System Image */
|
||||
reg = <0x00c00000 0x07400000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&board_soc {
|
||||
/* BSC9131RDB does not have any device on i2c@3100 */
|
||||
i2c@3100 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
partition@0 {
|
||||
reg = <0x0 0x00080000>;
|
||||
label = "SPI Flash U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
/* 512KB for DTB Image */
|
||||
partition@80000 {
|
||||
reg = <0x00080000 0x00080000>;
|
||||
label = "SPI Flash DTB Image";
|
||||
};
|
||||
|
||||
/* 4MB for Linux Kernel Image */
|
||||
partition@100000 {
|
||||
reg = <0x00100000 0x00400000>;
|
||||
label = "SPI Flash Kernel Image";
|
||||
};
|
||||
|
||||
/*11MB for RFS Image */
|
||||
partition@500000 {
|
||||
reg = <0x00500000 0x00B00000>;
|
||||
label = "SPI Flash RFS Image";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupts = <3 1 0 0>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupts = <2 1 0 0>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
};
|
||||
35
arch/powerpc/boot/dts/bsc9132qds.dts
Normal file
35
arch/powerpc/boot/dts/bsc9132qds.dts
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* BSC9132 QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "fsl/bsc9132si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,bsc9132qds";
|
||||
compatible = "fsl,bsc9132qds";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
ifc: ifc@ff71e000 {
|
||||
/* NOR, NAND Flash on board */
|
||||
ranges = <0x0 0x0 0x0 0x88000000 0x08000000
|
||||
0x1 0x0 0x0 0xff800000 0x00010000>;
|
||||
reg = <0x0 0xff71e000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
soc: soc@ff700000 {
|
||||
ranges = <0x0 0x0 0xff700000 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "bsc9132qds.dtsi"
|
||||
/include/ "fsl/bsc9132si-post.dtsi"
|
||||
101
arch/powerpc/boot/dts/bsc9132qds.dtsi
Normal file
101
arch/powerpc/boot/dts/bsc9132qds.dtsi
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
fpga: fpga@66 {
|
||||
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
|
||||
reg = <0x66>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x1f>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
phy-handle = <&phy0>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy1>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
};
|
||||
224
arch/powerpc/boot/dts/c293pcie.dts
Normal file
224
arch/powerpc/boot/dts/c293pcie.dts
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* C293 PCIE Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/c293si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,C293PCIE";
|
||||
compatible = "fsl,C293PCIE";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
ifc: ifc@fffe1e000 {
|
||||
reg = <0xf 0xffe1e000 0 0x2000>;
|
||||
ranges = <0x0 0x0 0xf 0xec000000 0x04000000
|
||||
0x1 0x0 0xf 0xff800000 0x00010000
|
||||
0x2 0x0 0xf 0xffdf0000 0x00010000>;
|
||||
|
||||
};
|
||||
|
||||
soc: soc@fffe00000 {
|
||||
ranges = <0x0 0xf 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci0: pcie@fffe0a000 {
|
||||
reg = <0xf 0xffe0a000 0 0x1000>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
|
||||
pcie@0 {
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NOR DTB Image";
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 8 MB for Linux Kernel Image */
|
||||
reg = <0x00100000 0x00800000>;
|
||||
label = "NOR Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@900000 {
|
||||
/* 53MB for rootfs */
|
||||
reg = <0x00900000 0x03500000>;
|
||||
label = "NOR Rootfs Image";
|
||||
};
|
||||
|
||||
partition@3e00000 {
|
||||
/* 1MB for blob encrypted key */
|
||||
reg = <0x03e00000 0x00100000>;
|
||||
label = "NOR blob encrypted key";
|
||||
};
|
||||
|
||||
partition@3f00000 {
|
||||
/* 512KB for u-boot Bootloader Image and evn */
|
||||
reg = <0x03f00000 0x00100000>;
|
||||
label = "NOR U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 16MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x01000000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@1200000 {
|
||||
/* 4078MB for Root file System Image */
|
||||
reg = <0x00600000 0xfee00000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
|
||||
cpld@2,0 {
|
||||
compatible = "fsl,c293pcie-cpld";
|
||||
reg = <0x2 0x0 0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
i2c@3000 {
|
||||
eeprom@50 {
|
||||
compatible = "st,24c1024";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
adt7461@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partition@0 {
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
/* 1MB for Environment */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "SPI Flash U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 512KB for DTB Image */
|
||||
reg = <0x00100000 0x00080000>;
|
||||
label = "SPI Flash DTB Image";
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00180000 0x00400000>;
|
||||
label = "SPI Flash Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
/* 10.5MB for RFS Image */
|
||||
reg = <0x00580000 0x00a80000>;
|
||||
label = "SPI Flash RFS Image";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupts = <2 1 0 0>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupts = <2 1 0 0>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
};
|
||||
/include/ "fsl/c293si-post.dtsi"
|
||||
366
arch/powerpc/boot/dts/c2k.dts
Normal file
366
arch/powerpc/boot/dts/c2k.dts
Normal file
|
|
@ -0,0 +1,366 @@
|
|||
/* Device Tree Source for GEFanuc C2K
|
||||
*
|
||||
* Author: Remi Machet <rmachet@slac.stanford.edu>
|
||||
*
|
||||
* Originated from prpmc2800.dts
|
||||
*
|
||||
* 2008 (c) Stanford University
|
||||
* 2007 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "C2K";
|
||||
compatible = "GEFanuc,C2K";
|
||||
coherency-off;
|
||||
|
||||
aliases {
|
||||
pci0 = &PCI0;
|
||||
pci1 = &PCI1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "PowerPC,7447";
|
||||
reg = <0>;
|
||||
clock-frequency = <996000000>; /* 996 MHz */
|
||||
bus-frequency = <166666667>; /* 166.6666 MHz */
|
||||
timebase-frequency = <41666667>; /* 166.6666/4 MHz */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
system-controller@d8000000 { /* Marvell Discovery */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "mv64460";
|
||||
compatible = "marvell,mv64360";
|
||||
clock-frequency = <166666667>; /* 166.66... MHz */
|
||||
reg = <0xd8000000 0x00010000>;
|
||||
virtual-reg = <0xd8000000>;
|
||||
ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
|
||||
0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
|
||||
0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
|
||||
0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
|
||||
0xd8100000 0xd8100000 0x00010000 /* FPGA */
|
||||
0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
|
||||
0xf8000000 0xf8000000 0x08000000 /* User FLASH */
|
||||
0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
|
||||
0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
|
||||
|
||||
mdio@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-mdio";
|
||||
reg = <0x2000 4>;
|
||||
PHY0: ethernet-phy@0 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0>;
|
||||
};
|
||||
PHY1: ethernet-phy@1 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <1>;
|
||||
};
|
||||
PHY2: ethernet-phy@2 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-group@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-eth-group";
|
||||
reg = <0x2000 0x2000>;
|
||||
ethernet@0 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <0>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY0>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@1 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <1>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@2 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <2>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY2>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
};
|
||||
|
||||
SDMA0: sdma@4000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x4000 0xc18>;
|
||||
virtual-reg = <0xd8004000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <36>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
SDMA1: sdma@6000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x6000 0xc18>;
|
||||
virtual-reg = <0xd8006000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <38>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
BRG0: brg@b200 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb200 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
BRG1: brg@b208 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb208 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
CUNIT: cunit@f200 {
|
||||
reg = <0xf200 0x200>;
|
||||
};
|
||||
|
||||
MPSCROUTING: mpscrouting@b400 {
|
||||
reg = <0xb400 0xc>;
|
||||
};
|
||||
|
||||
MPSCINTR: mpscintr@b800 {
|
||||
reg = <0xb800 0x100>;
|
||||
virtual-reg = <0xd800b800>;
|
||||
};
|
||||
|
||||
MPSC0: mpsc@8000 {
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x8000 0x38>;
|
||||
virtual-reg = <0xd8008000>;
|
||||
sdma = <&SDMA0>;
|
||||
brg = <&BRG0>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <0>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
MPSC1: mpsc@9000 {
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x9000 0x38>;
|
||||
virtual-reg = <0xd8009000>;
|
||||
sdma = <&SDMA1>;
|
||||
brg = <&BRG1>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <1>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
wdt@b410 { /* watchdog timer */
|
||||
compatible = "marvell,mv64360-wdt";
|
||||
reg = <0xb410 0x8>;
|
||||
};
|
||||
|
||||
i2c@c000 {
|
||||
compatible = "marvell,mv64360-i2c";
|
||||
reg = <0xc000 0x20>;
|
||||
virtual-reg = <0xd800c000>;
|
||||
interrupts = <37>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
PIC: pic {
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
compatible = "marvell,mv64360-pic";
|
||||
reg = <0x0000 0x88>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
mpp@f000 {
|
||||
compatible = "marvell,mv64360-mpp";
|
||||
reg = <0xf000 0x10>;
|
||||
};
|
||||
|
||||
gpp@f100 {
|
||||
compatible = "marvell,mv64360-gpp";
|
||||
reg = <0xf100 0x20>;
|
||||
};
|
||||
|
||||
PCI0: pci@80000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0cf8 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0c34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* Only one interrupt line for PMC0 slot (INTA) */
|
||||
0x0000 0 0 1 &PIC 88
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
PCI1: pci@a0000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0c78 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0cb4>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x01: PMC1 ? */
|
||||
0x0800 0 0 1 &PIC 88
|
||||
/* IDSEL 0x02: cPCI bridge */
|
||||
0x1000 0 0 1 &PIC 88
|
||||
/* IDSEL 0x03: USB controller */
|
||||
0x1800 0 0 1 &PIC 91
|
||||
/* IDSEL 0x04: SATA controller */
|
||||
0x2000 0 0 1 &PIC 95
|
||||
>;
|
||||
};
|
||||
|
||||
cpu-error@0070 {
|
||||
compatible = "marvell,mv64360-cpu-error";
|
||||
reg = <0x0070 0x10 0x0128 0x28>;
|
||||
interrupts = <3>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
sram-ctrl@0380 {
|
||||
compatible = "marvell,mv64360-sram-ctrl";
|
||||
reg = <0x0380 0x80>;
|
||||
interrupts = <13>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1d40 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1d40 0x40 0x0c28 0x4>;
|
||||
interrupts = <12>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1dc0 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1dc0 0x40 0x0ca8 0x4>;
|
||||
interrupts = <16>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
mem-ctrl@1400 {
|
||||
compatible = "marvell,mv64360-mem-ctrl";
|
||||
reg = <0x1400 0x60>;
|
||||
interrupts = <17>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
/* Devices attached to the device controller */
|
||||
devicebus@045c {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "marvell,mv64306-devctrl";
|
||||
reg = <0x45C 0x88>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
ranges = <0 0 0xd8100000 0x10000
|
||||
2 0 0xd8110000 0x10000
|
||||
4 0 0xf8000000 0x8000000>;
|
||||
fpga@0,0 {
|
||||
compatible = "sbs,fpga-c2k";
|
||||
reg = <0 0 0x10000>;
|
||||
};
|
||||
fpga_usart@2,0 {
|
||||
compatible = "sbs,fpga_usart-c2k";
|
||||
reg = <2 0 0x10000>;
|
||||
};
|
||||
nor_flash@4,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <4 0 0x8000000>; /* 128MB */
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "boot";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "kernel";
|
||||
reg = <0x00080000 0x00400000>;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "initrd";
|
||||
reg = <0x00480000 0x00B80000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "rootfs";
|
||||
reg = <0x01000000 0x06800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "recovery";
|
||||
reg = <0x07800000 0x00800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
chosen {
|
||||
linux,stdout-path = &MPSC0;
|
||||
};
|
||||
};
|
||||
557
arch/powerpc/boot/dts/canyonlands.dts
Normal file
557
arch/powerpc/boot/dts/canyonlands.dts
Normal file
|
|
@ -0,0 +1,557 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Canyonlands (460EX)
|
||||
*
|
||||
* Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,canyonlands";
|
||||
compatible = "amcc,canyonlands";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460EX";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460ex";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460ex";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
CPM0: cpm {
|
||||
compatible = "ibm,cpm";
|
||||
dcr-access-method = "native";
|
||||
dcr-reg = <0x160 0x003>;
|
||||
unused-units = <0x00000100>;
|
||||
idle-doze = <0x02000000>;
|
||||
standby = <0xfeff791d>;
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
|
||||
dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
|
||||
0x030 0x008>; /* L2 cache DCR's */
|
||||
cache-line-size = <32>; /* 32 bytes */
|
||||
cache-size = <262144>; /* L2, 256K */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <11 1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-460ex", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
CRYPTO: crypto@180000 {
|
||||
compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
|
||||
reg = <4 0x00180000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
HWRNG: hwrng@110000 {
|
||||
compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
|
||||
reg = <4 0x00110000 0x50>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <16>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
};
|
||||
|
||||
USB0: ehci@bffd0400 {
|
||||
compatible = "ibm,usb-ehci-460ex", "usb-ehci";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x1d 4>;
|
||||
reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
|
||||
};
|
||||
|
||||
USB1: usb@bffd0000 {
|
||||
compatible = "ohci-le";
|
||||
reg = <4 0xbffd0000 0x60>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x1e 4>;
|
||||
};
|
||||
|
||||
USBOTG0: usbotg@bff80000 {
|
||||
compatible = "amcc,dwc-otg";
|
||||
reg = <0x4 0xbff80000 0x10000>;
|
||||
interrupt-parent = <&USBOTG0>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0x0 0x1 0x2>;
|
||||
interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
|
||||
/* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
|
||||
/* DMA */ 0x2 &UIC0 0xc 0x4>;
|
||||
};
|
||||
|
||||
SATA0: sata@bffd1000 {
|
||||
compatible = "amcc,sata-460ex";
|
||||
reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
interrupts = <0x0 0x4 /* SATA */
|
||||
0x5 0x4>; /* AHBDMA */
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460ex", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpld@2,0 {
|
||||
compatible = "amcc,ppc460ex-bcsr";
|
||||
reg = <2 0x0 0x9>;
|
||||
};
|
||||
|
||||
ndfc@3,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000003 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "user";
|
||||
reg = <0x00000000 0x03f00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x19 0x8>;
|
||||
};
|
||||
sttm@48 {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x14 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@ef600b00 {
|
||||
compatible = "ibm,ppc4xx-gpio";
|
||||
reg = <0xef600b00 0x00000048>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-460ex", "ibm,zmii";
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii-460ex", "ibm,rgmii";
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
|
||||
PCIX0: pci@c0ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
|
||||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0 to 0x3f */
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08011000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 80 to 0xbf */
|
||||
bus-range = <0x80 0xbf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
MSI: ppc4xx-msi@C10000000 {
|
||||
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
|
||||
reg = < 0xC 0x10000000 0x100>;
|
||||
sdr-base = <0x36C>;
|
||||
msi-data = <0x00000000>;
|
||||
msi-mask = <0x44440000>;
|
||||
interrupt-count = <3>;
|
||||
interrupts = <0 1 2 3>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0 &UIC3 0x18 1
|
||||
1 &UIC3 0x19 1
|
||||
2 &UIC3 0x1A 1
|
||||
3 &UIC3 0x1B 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
236
arch/powerpc/boot/dts/charon.dts
Normal file
236
arch/powerpc/boot/dts/charon.dts
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* charon board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* Copyright (C) 2010 DENX Software Engineering GmbH
|
||||
* Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "anon,charon";
|
||||
compatible = "anon,charon";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>; // 128MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200-immr";
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200-cdm";
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200-pic";
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 17 0>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 18 0>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200-xlb";
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
};
|
||||
|
||||
serial@2400 { // PSC3
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <2 3 0>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
fixed-link = <1 1 100 0 0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
};
|
||||
|
||||
|
||||
i2c@3d40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
|
||||
dtt@28 {
|
||||
compatible = "national,lm80";
|
||||
reg = <0x28>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus {
|
||||
compatible = "fsl,mpc5200-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = < 0 0 0xfc000000 0x02000000
|
||||
1 0 0xe0000000 0x04000000 // CS1 range, SM501
|
||||
3 0 0xe8000000 0x00080000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
};
|
||||
|
||||
display@1,0 {
|
||||
compatible = "smi,sm501";
|
||||
reg = <1 0x00000000 0x00800000
|
||||
1 0x03e00000 0x00200000>;
|
||||
mode = "640x480-32@60";
|
||||
interrupts = <1 1 3>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
mram0@3,0 {
|
||||
compatible = "mtd-ram";
|
||||
reg = <3 0x00000 0x80000>;
|
||||
bank-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200-pci";
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 2 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 3 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
89
arch/powerpc/boot/dts/cm5200.dts
Normal file
89
arch/powerpc/boot/dts/cm5200.dts
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* CM5200 board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "mpc5200b.dtsi"
|
||||
|
||||
&gpt0 { fsl,has-wdt; };
|
||||
|
||||
/ {
|
||||
model = "schindler,cm5200";
|
||||
compatible = "schindler,cm5200";
|
||||
|
||||
soc5200@f0000000 {
|
||||
can@900 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can@980 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2000 { // PSC1
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2200 { // PSC2
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2400 { // PSC3
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2600 { // PSC4
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2800 { // PSC5
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2c00 { // PSC6
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
localbus {
|
||||
// 16-bit flash device at LocalPlus Bus CS0
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x2000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
242
arch/powerpc/boot/dts/currituck.dts
Normal file
242
arch/powerpc/boot/dts/currituck.dts
Normal file
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Device Tree Source for IBM Embedded PPC 476 Platform
|
||||
*
|
||||
* Copyright © 2011 Tony Breeds IBM Corporation
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x01f00000 0x00100000; // spin table
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "ibm,currituck";
|
||||
compatible = "ibm,currituck";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
serial0 = &UART0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <0>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "ok";
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <1>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "disabled";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x01f00000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
|
||||
};
|
||||
|
||||
MPIC: interrupt-controller {
|
||||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0xffc00000 0x00040000>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb6";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
clock-frequency = <200000000>; // 200Mhz
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-4xx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full
|
||||
* 32-bit range
|
||||
*/
|
||||
ranges = <0x00000000 0x00000200 0x00000000 0x80000000
|
||||
0x80000000 0x00000200 0x80000000 0x80000000>;
|
||||
clock-frequency = <100000000>;
|
||||
|
||||
UART0: serial@10000000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16750", "ns16550";
|
||||
reg = <0x10000000 0x00000008>;
|
||||
virtual-reg = <0xe1000000>;
|
||||
clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <34 2>;
|
||||
};
|
||||
|
||||
FPGA0: fpga@50000000 {
|
||||
compatible = "ibm,currituck-fpga";
|
||||
reg = <0x50000000 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@00000000 {
|
||||
compatible = "ibm,iic-currituck", "ibm,iic";
|
||||
reg = <0x0 0x00000014>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <79 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80", "m41st85";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@10100000000 { // 4xGBIF1
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x80 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0 to memsize filled in by zImage */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@30100000000 { // 4xGBIF0
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x60 0x20>;
|
||||
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0 to memsize filled in by zImage */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@38100000000 { // 2xGBIF0
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xA0 0x20>;
|
||||
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0 to memsize filled in by zImage */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &UART0;
|
||||
};
|
||||
};
|
||||
161
arch/powerpc/boot/dts/digsy_mtc.dts
Normal file
161
arch/powerpc/boot/dts/digsy_mtc.dts
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* Digsy MTC board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2009 Semihalf
|
||||
*
|
||||
* Based on the CM5200 by M. Balakowicz
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "mpc5200b.dtsi"
|
||||
|
||||
&gpt0 { gpio-controller; fsl,has-wdt; };
|
||||
&gpt1 { gpio-controller; };
|
||||
|
||||
/ {
|
||||
model = "intercontrol,digsy-mtc";
|
||||
compatible = "intercontrol,digsy-mtc";
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x02000000>; // 32MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
rtc@800 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
msp430@0 {
|
||||
compatible = "spidev";
|
||||
spi-max-frequency = <32000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
psc@2000 { // PSC1
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2200 { // PSC2
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2400 { // PSC3
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2600 { // PSC4
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2800 { // PSC5
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2c00 { // PSC6
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
eeprom@50 {
|
||||
compatible = "at,24c08";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@56 {
|
||||
compatible = "mc,rv3029c2";
|
||||
reg = <0x56>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 2 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 3 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus {
|
||||
ranges = <0 0 0xff000000 0x1000000
|
||||
4 0 0x60000000 0x0001000>;
|
||||
|
||||
// 16-bit flash device at LocalPlus Bus CS0
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x0 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00300000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "user";
|
||||
reg = <0x00500000 0x00a00000>;
|
||||
};
|
||||
partition@f00000 {
|
||||
label = "u-boot";
|
||||
reg = <0x00f00000 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
can@4,0 {
|
||||
compatible = "nxp,sja1000";
|
||||
reg = <4 0x000 0x80>;
|
||||
nxp,external-clock-frequency = <24000000>;
|
||||
interrupts = <1 2 3>; // Level-low
|
||||
};
|
||||
|
||||
can@4,100 {
|
||||
compatible = "nxp,sja1000";
|
||||
reg = <4 0x100 0x80>;
|
||||
nxp,external-clock-frequency = <24000000>;
|
||||
interrupts = <1 2 3>; // Level-low
|
||||
};
|
||||
|
||||
serial@4,200 {
|
||||
compatible = "nxp,sc28l92";
|
||||
reg = <4 0x200 0x10>;
|
||||
interrupts = <1 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
337
arch/powerpc/boot/dts/ebony.dts
Normal file
337
arch/powerpc/boot/dts/ebony.dts
Normal file
|
|
@ -0,0 +1,337 @@
|
|||
/*
|
||||
* Device Tree Source for IBM Ebony
|
||||
*
|
||||
* Copyright (c) 2006, 2007 IBM Corp.
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
|
||||
*
|
||||
* FIXME: Draft only!
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "ibm,ebony";
|
||||
compatible = "ibm,ebony";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GP";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
timebase-frequency = <0>; // Filled in by zImage
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>; /* 32 kB */
|
||||
d-cache-size = <32768>; /* 32 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440gp", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440gp", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
CPC0: cpc {
|
||||
compatible = "ibm,cpc-440gp";
|
||||
dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440gp", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-440gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
SRAM0: sram {
|
||||
compatible = "ibm,sram-440gp";
|
||||
dcr-reg = <0x020 0x008 0x00a 0x001>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
// FIXME: ???
|
||||
compatible = "ibm,dma-440gp";
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440gp", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <4>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full 32-bit
|
||||
range */
|
||||
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
|
||||
0x80000000 0x00000001 0x80000000 0x80000000>;
|
||||
dcr-reg = <0x090 0x00b>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
// ranges property is supplied by zImage
|
||||
// based on firmware's configuration of the
|
||||
// EBC bridge
|
||||
interrupts = <0x5 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
small-flash@0,80000 {
|
||||
compatible = "jedec-flash";
|
||||
bank-width = <1>;
|
||||
reg = <0x00000000 0x00080000 0x00080000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "OpenBIOS";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@1,0 {
|
||||
/* NVRAM & RTC */
|
||||
compatible = "ds1743-nvram";
|
||||
#bytes = <0x2000>;
|
||||
reg = <0x00000001 0x00000000 0x00002000>;
|
||||
};
|
||||
|
||||
large-flash@2,0 {
|
||||
compatible = "jedec-flash";
|
||||
bank-width = <1>;
|
||||
reg = <0x00000002 0x00000000 0x00400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "fs";
|
||||
reg = <0x00000000 0x00380000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "firmware";
|
||||
reg = <0x00380000 0x00080000>;
|
||||
};
|
||||
};
|
||||
|
||||
ir@3,0 {
|
||||
reg = <0x00000003 0x00000000 0x00000010>;
|
||||
};
|
||||
|
||||
fpga@7,0 {
|
||||
compatible = "Ebony-FPGA";
|
||||
reg = <0x00000007 0x00000000 0x00000010>;
|
||||
virtual-reg = <0xe8300000>;
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@40000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x40000200 0x00000008>;
|
||||
virtual-reg = <0xe0000200>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@40000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x40000300 0x00000008>;
|
||||
virtual-reg = <0xe0000300>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@40000400 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0x40000400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
IIC1: i2c@40000500 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0x40000500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@40000700 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,gpio-440gp";
|
||||
reg = <0x40000700 0x00000020>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@40000780 {
|
||||
compatible = "ibm,zmii-440gp", "ibm,zmii";
|
||||
reg = <0x40000780 0x0000000c>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@40000800 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0x40000800 0x00000070>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
EMAC1: ethernet@40000900 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>;
|
||||
reg = <0x40000900 0x00000070>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2 3>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
||||
|
||||
GPT0: gpt@40000a00 {
|
||||
/* FIXME */
|
||||
reg = <0x40000a00 0x000000d4>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
PCIX0: pci@20ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
|
||||
primary;
|
||||
reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x00000002 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
|
||||
0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* Ebony has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
|
||||
|
||||
/* IDSEL 2 */
|
||||
0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
|
||||
|
||||
/* IDSEL 3 */
|
||||
0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
|
||||
|
||||
/* IDSEL 4 */
|
||||
0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@40000200";
|
||||
};
|
||||
};
|
||||
427
arch/powerpc/boot/dts/eiger.dts
Normal file
427
arch/powerpc/boot/dts/eiger.dts
Normal file
|
|
@ -0,0 +1,427 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC (AppliedMicro) Eiger(460SX)
|
||||
*
|
||||
* Copyright 2009 AMCC (AppliedMicro) <ttnguyen@amcc.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,eiger";
|
||||
compatible = "amcc,eiger";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
ethernet2 = &EMAC2;
|
||||
ethernet3 = &EMAC3;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460SX";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460sx";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460sx";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-460sx", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460sx", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460sx", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x62>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <32>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x1 0x4
|
||||
/*TXDE*/ 0x2 0x4
|
||||
/*RXDE*/ 0x3 0x4
|
||||
/*COAL TX0*/ 0x18 0x2
|
||||
/*COAL TX1*/ 0x19 0x2
|
||||
/*COAL TX2*/ 0x1a 0x2
|
||||
/*COAL TX3*/ 0x1b 0x2
|
||||
/*COAL RX0*/ 0x1c 0x2
|
||||
/*COAL RX1*/ 0x1d 0x2
|
||||
/*COAL RX2*/ 0x1e 0x2
|
||||
/*COAL RX3*/ 0x1f 0x2>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460sx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460sx", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
/* reg property is supplied in by U-Boot */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
ndfc@1,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
/* reg property is supplied by U-boot */
|
||||
ccr = <0x00003000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "uboot";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "uboot-environment";
|
||||
reg = <0x00200000 0x00100000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "linux";
|
||||
reg = <0x00300000 0x00300000>;
|
||||
};
|
||||
partition@600000 {
|
||||
label = "root-file-system";
|
||||
reg = <0x00600000 0x01900000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
label = "device-tree";
|
||||
reg = <0x01f00000 0x00020000>;
|
||||
};
|
||||
partition@1f20000 {
|
||||
label = "data";
|
||||
reg = <0x01f20000 0x060E0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600200 0x00000008>;
|
||||
virtual-reg = <0xef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-460sx", "ibm,iic";
|
||||
reg = <0xef600400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
index = <0>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-460sx", "ibm,iic";
|
||||
reg = <0xef600500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
index = <1>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef600900 {
|
||||
compatible = "ibm,rgmii-460sx", "ibm,rgmii";
|
||||
reg = <0xef600900 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
RGMII1: emac-rgmii@ef600920 {
|
||||
compatible = "ibm,rgmii-460sx", "ibm,rgmii";
|
||||
reg = <0xef600920 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef600e50 {
|
||||
compatible = "ibm,tah-460sx", "ibm,tah";
|
||||
reg = <0xef600e50 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef600f50 {
|
||||
compatible = "ibm,tah-460sx", "ibm,tah";
|
||||
reg = <0xef600f50 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600a00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600a00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600b00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600b00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
|
||||
EMAC2: ethernet@ef600c00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC2>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x15 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600c00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <16>;
|
||||
cell-index = <2>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII1>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
|
||||
EMAC3: ethernet@ef600d00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC3>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x16 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600d00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <3>;
|
||||
mal-rx-channel = <24>;
|
||||
cell-index = <3>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII1>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600200";
|
||||
};
|
||||
|
||||
};
|
||||
230
arch/powerpc/boot/dts/ep405.dts
Normal file
230
arch/powerpc/boot/dts/ep405.dts
Normal file
|
|
@ -0,0 +1,230 @@
|
|||
/*
|
||||
* Device Tree Source for EP405
|
||||
*
|
||||
* Copyright 2007 IBM Corp.
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "ep405";
|
||||
compatible = "ep405";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405GP";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <200000000>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>;
|
||||
d-cache-size = <16384>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL: mcmal {
|
||||
compatible = "ibm,mcmal-405gp", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0xb 0x4 /* TXEOB */
|
||||
0xc 0x4 /* RXEOB */
|
||||
0xa 0x4 /* SERR */
|
||||
0xd 0x4 /* TXDE */
|
||||
0xe 0x4 /* RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xef600000 0xef600000 0x00a00000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405gp", "ibm,iic";
|
||||
reg = <0xef600500 0x00000011>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
GPIO: gpio@ef600700 {
|
||||
compatible = "ibm,gpio-405gp";
|
||||
reg = <0xef600700 0x00000020>;
|
||||
};
|
||||
|
||||
EMAC: ethernet@ef600800 {
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0xf 0x4 /* Ethernet */
|
||||
0x9 0x4 /* Ethernet Wake Up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by zImage */
|
||||
reg = <0xef600800 0x00000070>;
|
||||
mal-device = <&MAL>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
||||
/* The ranges property is supplied by the bootwrapper
|
||||
* and is based on the firmware's configuration of the
|
||||
* EBC bridge
|
||||
*/
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
/* NVRAM and RTC */
|
||||
nvrtc@4,200000 {
|
||||
compatible = "ds1742";
|
||||
reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */
|
||||
};
|
||||
|
||||
/* "BCSR" CPLD contains a PCI irq controller */
|
||||
bcsr@4,0 {
|
||||
compatible = "ep405-bcsr";
|
||||
reg = <0x00000004 0x00000000 0x00000010>;
|
||||
interrupt-controller;
|
||||
/* Routing table */
|
||||
irq-routing = [ 00 /* SYSERR */
|
||||
01 /* STTM */
|
||||
01 /* RTC */
|
||||
01 /* FENET */
|
||||
02 /* NB PCIIRQ mux ? */
|
||||
03 /* SB Winbond 8259 ? */
|
||||
04 /* Serial Ring */
|
||||
05 /* USB (ep405pc) */
|
||||
06 /* XIRQ 0 */
|
||||
06 /* XIRQ 1 */
|
||||
06 /* XIRQ 2 */
|
||||
06 /* XIRQ 3 */
|
||||
06 /* XIRQ 4 */
|
||||
06 /* XIRQ 5 */
|
||||
06 /* XIRQ 6 */
|
||||
07]; /* Reserved */
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0xeec00000 0x00000008 /* Config space access */
|
||||
0xeed80000 0x00000004 /* IACK */
|
||||
0xeed80000 0x00000004 /* Special cycle */
|
||||
0xef480000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
|
||||
0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* That's all I know about IRQs on that thing ... */
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* USB */
|
||||
0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
203
arch/powerpc/boot/dts/ep8248e.dts
Normal file
203
arch/powerpc/boot/dts/ep8248e.dts
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Device Tree for the Embedded Planet EP8248E board running PlanetCore.
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "EP8248E";
|
||||
compatible = "fsl,ep8248e";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
planetcore-SMC1 = &smc1;
|
||||
planetcore-SCC1 = &scc1;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
serial0 = &smc1;
|
||||
serial1 = &scc1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8248@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@f0010100 {
|
||||
compatible = "fsl,mpc8248-localbus",
|
||||
"fsl,pq2-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf0010100 0x40>;
|
||||
|
||||
ranges = <0 0 0xfc000000 0x04000000
|
||||
1 0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,3800000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x3800000 0x800000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
};
|
||||
|
||||
bcsr@1,0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <1 0 0x10>;
|
||||
compatible = "fsl,ep8248e-bcsr";
|
||||
ranges;
|
||||
|
||||
mdio {
|
||||
compatible = "fsl,ep8248e-mdio-bitbang";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1 8 1>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>;
|
||||
};
|
||||
|
||||
soc@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8248-immr", "fsl,pq2-soc", "simple-bus";
|
||||
ranges = <0x00000000 0xf0000000 0x00053000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary -- will go away once kernel uses ranges for get_immrbase().
|
||||
reg = <0xf0000000 0x00053000>;
|
||||
|
||||
cpm@119c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,mpc8248-cpm", "fsl,cpm2",
|
||||
"simple-bus";
|
||||
reg = <0x119c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x2000 0x9800 0x800>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@119f0 {
|
||||
compatible = "fsl,mpc8248-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x119f0 0x10 0x115f0 0x10>;
|
||||
};
|
||||
|
||||
/* Monitor port/SMC1 */
|
||||
smc1: serial@11a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8248-smc-uart",
|
||||
"fsl,cpm2-smc-uart";
|
||||
reg = <0x11a80 0x20 0x87fc 2>;
|
||||
interrupts = <4 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <7>;
|
||||
fsl,cpm-command = <0x1d000000>;
|
||||
linux,planetcore-label = "SMC1";
|
||||
};
|
||||
|
||||
/* "Serial" port/SCC1 */
|
||||
scc1: serial@11a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8248-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x11a00 0x20 0x8000 0x100>;
|
||||
interrupts = <40 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x00800000>;
|
||||
linux,planetcore-label = "SCC1";
|
||||
};
|
||||
|
||||
eth0: ethernet@11300 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8248-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x11300 0x20 0x8400 0x100 0x11390 1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
fsl,cpm-command = <0x12000300>;
|
||||
};
|
||||
|
||||
eth1: ethernet@11320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8248-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x11320 0x20 0x8500 0x100 0x113b0 1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <33 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
fsl,cpm-command = <0x16200300>;
|
||||
};
|
||||
|
||||
usb@11b60 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8248-usb",
|
||||
"fsl,cpm2-usb";
|
||||
reg = <0x11b60 0x18 0x8b00 0x100>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupts = <11 8>;
|
||||
fsl,cpm-command = <0x2e600000>;
|
||||
};
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@10c00 {
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0x10c00 0x80>;
|
||||
compatible = "fsl,mpc8248-pic", "fsl,pq2-pic";
|
||||
};
|
||||
};
|
||||
};
|
||||
213
arch/powerpc/boot/dts/ep88xc.dts
Normal file
213
arch/powerpc/boot/dts/ep88xc.dts
Normal file
|
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* EP88xC Device Tree Source
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007,2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "EP88xC";
|
||||
compatible = "fsl,ep88xc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,885@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
|
||||
localbus@fa200100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xfa200100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0x0 0x0 0xfc000000 0x4000000
|
||||
0x3 0x0 0xfa000000 0x1000000
|
||||
>;
|
||||
|
||||
flash@0,2000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x2000000 0x2000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
};
|
||||
|
||||
board-control@3,400000 {
|
||||
reg = <0x3 0x400000 0x10>;
|
||||
compatible = "fsl,ep88xc-bcsr";
|
||||
};
|
||||
};
|
||||
|
||||
soc@fa200000 {
|
||||
compatible = "fsl,mpc885", "fsl,pq1-soc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xfa200000 0x4000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
// Temporary -- will go away once kernel uses ranges for get_immrbase().
|
||||
reg = <0xfa200000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc885-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc885-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x24>;
|
||||
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
pcmcia@80 {
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
compatible = "fsl,pq-pcmcia";
|
||||
device_type = "pcmcia";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupts = <13 1>;
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
|
||||
command-proc = <0x9c0>;
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0x0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc885-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc885-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
// MON-1
|
||||
serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc885-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x90>;
|
||||
linux,planetcore-label = "SMC1";
|
||||
};
|
||||
|
||||
// SER-1
|
||||
serial@a20 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc885-scc-uart",
|
||||
"fsl,cpm1-scc-uart";
|
||||
reg = <0xa20 0x20 0x3d00 0x80>;
|
||||
interrupts = <29>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <2>;
|
||||
fsl,cpm-command = <0x40>;
|
||||
linux,planetcore-label = "SCC2";
|
||||
};
|
||||
|
||||
usb@a00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc885-usb",
|
||||
"fsl,cpm1-usb";
|
||||
reg = <0xa00 0x18 0x1c00 0x80>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
interrupts = <30>;
|
||||
fsl,cpm-command = <0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
130
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
Normal file
130
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/include/ "b4si-post.dtsi"
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4420-l3-cache-controller", "cache";
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4420-l2-cache-controller";
|
||||
};
|
||||
};
|
||||
79
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
Normal file
79
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4420";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
174
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
Normal file
174
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* B4860 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "b4si-post.dtsi"
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 20>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@110000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x110000 0x1000 0x111000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@118000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x118000 0x1000 0x119000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 9>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4860-l3-cache-controller", "cache";
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4860-l2-cache-controller";
|
||||
};
|
||||
};
|
||||
93
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
Normal file
93
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* B4860 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4860";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
269
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
Normal file
269
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <20 2 0 0>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
interrupts = <20 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0
|
||||
94 2 0 0
|
||||
95 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
reg = <0x1000 0x1000 0x1002000 0x10000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0x1A000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x30000 0x1000 0x1022000 0x10000>;
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x31000 0x1000 0x1042000 0x10000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@100000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x100000 0x1000 0x101000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 2>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 4>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 0>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
fsl,portid-mapping = <0x8000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 1>;
|
||||
|
||||
|
||||
/* PCIe, DMA, SRIO */
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <8 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* AXI2, Maple */
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* Q/BMan */
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* AXI1, FMAN */
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic4.3.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4-device-config";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "elo3-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "elo3-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qonverge-usb2-dr-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
sdhci,auto-cmd12;
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-sec5.3-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4-l2-cache-controller";
|
||||
reg = <0xc20000 0x1000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
193
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
Normal file
193
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* BSC9131 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <16 2 0 0 20 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,bsc9131-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,bsc9131-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,bsc9131-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
i2c@3000 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
i2c@3100 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
serial0: serial@4500 {
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
interrupts = <18 2 0 0 >;
|
||||
};
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
interrupts = <22 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
gpio-controller@f000 {
|
||||
interrupts = <19 0x2 0 0>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,bsc9131-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
|
||||
dma@21300 {
|
||||
|
||||
dma-channel@0 {
|
||||
interrupts = <62 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@80 {
|
||||
interrupts = <63 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@100 {
|
||||
interrupts = <64 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@180 {
|
||||
interrupts = <65 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
|
||||
interrupts = <40 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
sdhci,auto-cmd12;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec4.4-0.dtsi"
|
||||
crypto@30000 {
|
||||
interrupts = <57 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
interrupts = <58 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
interrupts = <59 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
interrupts = <60 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
interrupts = <61 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
|
||||
timer@41100 {
|
||||
compatible = "fsl,mpic-v1.2-msgr", "fsl,mpic-msg";
|
||||
reg = <0x41400 0x200>;
|
||||
interrupts = <
|
||||
0xb0 2
|
||||
0xb1 2
|
||||
0xb2 2
|
||||
0xb3 2>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: ethernet@b0000 {
|
||||
queue-group@b0000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: ethernet@b1000 {
|
||||
queue-group@b1000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,bsc9131-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
62
arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
Normal file
62
arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* BSC9131 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,BSC9131";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,BSC9131@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "fsl,e500v2";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
185
arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
Normal file
185
arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* BSC9132 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
/* FIXME: Test whether interrupts are split */
|
||||
interrupts = <16 2 0 0 20 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,bsc9132-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,bsc9132-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,bsc9132-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
i2c@3000 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
i2c@3100 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
serial0: serial@4500 {
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
interrupts = <18 2 0 0 >;
|
||||
};
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
interrupts = <22 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
gpio-controller@f000 {
|
||||
interrupts = <19 0x2 0 0>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,bsc9132-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 1 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
|
||||
dma@21300 {
|
||||
|
||||
dma-channel@0 {
|
||||
interrupts = <62 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@80 {
|
||||
interrupts = <63 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@100 {
|
||||
interrupts = <64 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@180 {
|
||||
interrupts = <65 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
|
||||
interrupts = <40 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
fsl,sdhci-auto-cmd12;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec4.4-0.dtsi"
|
||||
crypto@30000 {
|
||||
interrupts = <57 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
interrupts = <58 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
interrupts = <59 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
interrupts = <60 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
interrupts = <61 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: ethernet@b0000 {
|
||||
queue-group@b0000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: ethernet@b1000 {
|
||||
queue-group@b1000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,bsc9132-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* BSC9132 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500v2@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu1: PowerPC,e500v2@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
193
arch/powerpc/boot/dts/fsl/c293si-post.dtsi
Normal file
193
arch/powerpc/boot/dts/fsl/c293si-post.dtsi
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* C293 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,c293-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,c293-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,c293-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2,512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,c293-esdhc", "fsl,esdhc";
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
crypto@80000 {
|
||||
/include/ "qoriq-sec6.0-0.dtsi"
|
||||
};
|
||||
|
||||
crypto@80000 {
|
||||
reg = <0x80000 0x20000>;
|
||||
ranges = <0x0 0x80000 0x20000>;
|
||||
|
||||
jr@1000{
|
||||
interrupts = <45 2 0 0>;
|
||||
};
|
||||
jr@2000{
|
||||
interrupts = <57 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@a0000 {
|
||||
/include/ "qoriq-sec6.0-0.dtsi"
|
||||
};
|
||||
|
||||
crypto@a0000 {
|
||||
reg = <0xa0000 0x20000>;
|
||||
ranges = <0x0 0xa0000 0x20000>;
|
||||
|
||||
jr@1000{
|
||||
interrupts = <49 2 0 0>;
|
||||
};
|
||||
jr@2000{
|
||||
interrupts = <50 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@c0000 {
|
||||
/include/ "qoriq-sec6.0-0.dtsi"
|
||||
};
|
||||
|
||||
crypto@c0000 {
|
||||
reg = <0xc0000 0x20000>;
|
||||
ranges = <0x0 0xc0000 0x20000>;
|
||||
|
||||
jr@1000{
|
||||
interrupts = <55 2 0 0>;
|
||||
};
|
||||
jr@2000{
|
||||
interrupts = <56 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: ethernet@b0000 {
|
||||
queue-group@b0000 {
|
||||
reg = <0x10000 0x1000>;
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: ethernet@b1000 {
|
||||
queue-group@b1000 {
|
||||
reg = <0x11000 0x1000>;
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,c293-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
63
arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
Normal file
63
arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* C293 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,C293";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,e500v2@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
59
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
Normal file
59
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* e500mc Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.06";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-ds; // Decorated Storage
|
||||
power-isa-e.ed; // Embedded.Enhanced Debug
|
||||
power-isa-e.pd; // Embedded.External PID
|
||||
power-isa-e.hv; // Embedded.Hypervisor
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-e.pc; // Embedded.Processor Control
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-exp; // External Proxy
|
||||
power-isa-fp; // Floating Point
|
||||
power-isa-fp.r; // Floating Point.Record
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
52
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
Normal file
52
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* e500v2 Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.03";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-sp; // Signal Processing Engine
|
||||
power-isa-sp.fd; // SPE.Embedded Float Scalar Double
|
||||
power-isa-sp.fs; // SPE.Embedded Float Scalar Single
|
||||
power-isa-sp.fv; // SPE.Embedded Float Vector
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
60
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
Normal file
60
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* e5500 Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.06";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-ds; // Decorated Storage
|
||||
power-isa-e.ed; // Embedded.Enhanced Debug
|
||||
power-isa-e.pd; // Embedded.External PID
|
||||
power-isa-e.hv; // Embedded.Hypervisor
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-e.pc; // Embedded.Processor Control
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-exp; // External Proxy
|
||||
power-isa-fp; // Floating Point
|
||||
power-isa-fp.r; // Floating Point.Record
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
power-isa-64; // 64-bit
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
65
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
Normal file
65
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* e6500 Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.06";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-ds; // Decorated Storage
|
||||
power-isa-e.ed; // Embedded.Enhanced Debug
|
||||
power-isa-e.pd; // Embedded.External PID
|
||||
power-isa-e.hv; // Embedded.Hypervisor
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-e.pc; // Embedded.Processor Control
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-exp; // External Proxy
|
||||
power-isa-fp; // Floating Point
|
||||
power-isa-fp.r; // Floating Point.Record
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
power-isa-64; // 64-bit
|
||||
power-isa-e.pt; // Embedded.Page Table
|
||||
power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
|
||||
power-isa-e.em; // Embedded Multi-Threading
|
||||
power-isa-v; // Vector (AltiVec)
|
||||
fsl,eref-er; // Enhanced Reservations (Load and Reserve and Store Cond.)
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
82
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
Normal file
82
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma0: dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elo3-dma";
|
||||
reg = <0x100300 0x4>,
|
||||
<0x100600 0x4>;
|
||||
ranges = <0x0 0x100100 0x500>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <29 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupts = <30 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
interrupts = <31 2 0 0>;
|
||||
};
|
||||
dma-channel@300 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x300 0x80>;
|
||||
interrupts = <76 2 0 0>;
|
||||
};
|
||||
dma-channel@380 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x380 0x80>;
|
||||
interrupts = <77 2 0 0>;
|
||||
};
|
||||
dma-channel@400 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <78 2 0 0>;
|
||||
};
|
||||
dma-channel@480 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x480 0x80>;
|
||||
interrupts = <79 2 0 0>;
|
||||
};
|
||||
};
|
||||
82
arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
Normal file
82
arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma1: dma@101300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elo3-dma";
|
||||
reg = <0x101300 0x4>,
|
||||
<0x101600 0x4>;
|
||||
ranges = <0x0 0x101100 0x500>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
interrupts = <32 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <33 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupts = <34 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
interrupts = <35 2 0 0>;
|
||||
};
|
||||
dma-channel@300 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x300 0x80>;
|
||||
interrupts = <80 2 0 0>;
|
||||
};
|
||||
dma-channel@380 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x380 0x80>;
|
||||
interrupts = <81 2 0 0>;
|
||||
};
|
||||
dma-channel@400 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <82 2 0 0>;
|
||||
};
|
||||
dma-channel@480 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x480 0x80>;
|
||||
interrupts = <83 2 0 0>;
|
||||
};
|
||||
};
|
||||
82
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
Normal file
82
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma2: dma@102300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elo3-dma";
|
||||
reg = <0x102300 0x4>,
|
||||
<0x102600 0x4>;
|
||||
ranges = <0x0 0x102100 0x500>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
interrupts = <464 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <465 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupts = <466 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
interrupts = <467 2 0 0>;
|
||||
};
|
||||
dma-channel@300 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x300 0x80>;
|
||||
interrupts = <468 2 0 0>;
|
||||
};
|
||||
dma-channel@380 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x380 0x80>;
|
||||
interrupts = <469 2 0 0>;
|
||||
};
|
||||
dma-channel@400 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <470 2 0 0>;
|
||||
};
|
||||
dma-channel@480 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x480 0x80>;
|
||||
interrupts = <471 2 0 0>;
|
||||
};
|
||||
};
|
||||
156
arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
Normal file
156
arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
/* T4240 Interlaken LAC Portal device tree stub with 24 portals.
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "fsl,interlaken-lac-portals";
|
||||
|
||||
lportal0: lac-portal@0 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
lportal1: lac-portal@1000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x1000 0x1000>;
|
||||
};
|
||||
|
||||
lportal2: lac-portal@2000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
|
||||
lportal3: lac-portal@3000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x3000 0x1000>;
|
||||
};
|
||||
|
||||
lportal4: lac-portal@4000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x4000 0x1000>;
|
||||
};
|
||||
|
||||
lportal5: lac-portal@5000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
|
||||
lportal6: lac-portal@6000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x6000 0x1000>;
|
||||
};
|
||||
|
||||
lportal7: lac-portal@7000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x7000 0x1000>;
|
||||
};
|
||||
|
||||
lportal8: lac-portal@8000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x8000 0x1000>;
|
||||
};
|
||||
|
||||
lportal9: lac-portal@9000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
|
||||
lportal10: lac-portal@A000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xA000 0x1000>;
|
||||
};
|
||||
|
||||
lportal11: lac-portal@B000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xB000 0x1000>;
|
||||
};
|
||||
|
||||
lportal12: lac-portal@C000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xC000 0x1000>;
|
||||
};
|
||||
|
||||
lportal13: lac-portal@D000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xD000 0x1000>;
|
||||
};
|
||||
|
||||
lportal14: lac-portal@E000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xE000 0x1000>;
|
||||
};
|
||||
|
||||
lportal15: lac-portal@F000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xF000 0x1000>;
|
||||
};
|
||||
|
||||
lportal16: lac-portal@10000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x10000 0x1000>;
|
||||
};
|
||||
|
||||
lportal17: lac-portal@11000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
|
||||
lportal18: lac-portal@1200 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
|
||||
lportal19: lac-portal@13000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
|
||||
lportal20: lac-portal@14000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x14000 0x1000>;
|
||||
};
|
||||
|
||||
lportal21: lac-portal@15000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x15000 0x1000>;
|
||||
};
|
||||
|
||||
lportal22: lac-portal@16000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x16000 0x1000>;
|
||||
};
|
||||
|
||||
lportal23: lac-portal@17000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x17000 0x1000>;
|
||||
};
|
||||
45
arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
Normal file
45
arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* T4 Interlaken Look-aside Controller (LAC) device tree stub
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
lac: lac@229000 {
|
||||
compatible = "fsl,interlaken-lac";
|
||||
reg = <0x229000 0x1000>;
|
||||
interrupts = <16 2 1 18>;
|
||||
};
|
||||
|
||||
lac-hv@228000 {
|
||||
compatible = "fsl,interlaken-lac-hv";
|
||||
reg = <0x228000 0x1000>;
|
||||
fsl,non-hv-node = <&lac>;
|
||||
};
|
||||
252
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
Normal file
252
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
Normal file
|
|
@ -0,0 +1,252 @@
|
|||
/*
|
||||
* MPC8536 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <25 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xb000 */
|
||||
&pci3 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <27 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <27 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8536-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8536-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8536-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi@7000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
|
||||
/* mark compat w/8572 to get some erratum treatment */
|
||||
gpio-controller@f000 {
|
||||
compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <74 0x2 0 0>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
cell-index = <2>;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8536-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-timer-0.dtsi"
|
||||
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <28 0x2 0 0>;
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <46 0x2 0 0>;
|
||||
};
|
||||
|
||||
ptp_clock@24e00 {
|
||||
interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
|
||||
ethernet@26000 {
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
usb@2b000 {
|
||||
compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x2b000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <60 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
|
||||
};
|
||||
|
||||
/include/ "pq3-sec3.0-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8536-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* MPC8536 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8536";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8536@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
191
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
Normal file
191
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* MPC8544 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <25 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xb000 */
|
||||
&pci3 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <27 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <27 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8544-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8544-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8544-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8544-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
|
||||
ethernet@26000 {
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec2.1-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8544-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* MPC8544 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8544";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8544@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
159
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
Normal file
159
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* MPC8548 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <25 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <48 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8548-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
/include/ "pq3-etsec1-3.dtsi"
|
||||
|
||||
/include/ "pq3-sec2.1-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-rmu-0.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
67
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
Normal file
67
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* MPC8548 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8548";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
270
arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
Normal file
270
arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* MPC8568 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
sleep = <&pmc 0x08000000>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
sleep = <&pmc 0x80000000>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
sleep = <&pmc 0x20000000>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <48 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
sleep = <&pmc 0x00080000>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8568-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8568-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8568-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
i2c-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000004>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
|
||||
};
|
||||
|
||||
duart-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000002>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8568-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
dma@21300 {
|
||||
sleep = <&pmc 0x00000400>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
ethernet@24000 {
|
||||
sleep = <&pmc 0x00000080>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
ethernet@25000 {
|
||||
sleep = <&pmc 0x00000040>;
|
||||
};
|
||||
|
||||
par_io@e0100 {
|
||||
reg = <0xe0100 0x100>;
|
||||
device_type = "par_io";
|
||||
};
|
||||
|
||||
/include/ "pq3-sec2.1-0.dtsi"
|
||||
crypto@30000 {
|
||||
sleep = <&pmc 0x01000000>;
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-rmu-0.dtsi"
|
||||
rmu@d3000 {
|
||||
sleep = <&pmc 0x00040000>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
ranges = <0 0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
|
||||
pmc: power@70 {
|
||||
compatible = "fsl,mpc8568-pmc",
|
||||
"fsl,mpc8548-pmc";
|
||||
reg = <0x70 0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
sleep = <&pmc 0x00000800>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <396000000>;
|
||||
fsl,qe-num-riscs = <2>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
cell-index = <0>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3000 {
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x10000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
68
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
Normal file
68
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* MPC8568 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8568";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8568@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
sleep = <&pmc 0x00008000 // core
|
||||
&pmc 0x00004000>; // timebase
|
||||
};
|
||||
};
|
||||
};
|
||||
304
arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
Normal file
304
arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
Normal file
|
|
@ -0,0 +1,304 @@
|
|||
/*
|
||||
* MPC8569 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
sleep = <&pmc 0x08000000>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
sleep = <&pmc 0x20000000>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <48 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
sleep = <&pmc 0x00080000>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8569-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8569-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8569-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
i2c-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000004>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
|
||||
};
|
||||
|
||||
duart-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000002>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8569-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
sleep = <&pmc 0x00200000>;
|
||||
};
|
||||
|
||||
par_io@e0100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0100 0x100>;
|
||||
ranges = <0x0 0xe0100 0x100>;
|
||||
device_type = "par_io";
|
||||
};
|
||||
|
||||
/include/ "pq3-sec3.1-0.dtsi"
|
||||
crypto@30000 {
|
||||
sleep = <&pmc 0x01000000>;
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-rmu-0.dtsi"
|
||||
rmu@d3000 {
|
||||
sleep = <&pmc 0x00040000>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
ranges = <0 0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
|
||||
pmc: power@70 {
|
||||
compatible = "fsl,mpc8569-pmc",
|
||||
"fsl,mpc8548-pmc";
|
||||
reg = <0x70 0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
sleep = <&pmc 0x00000800>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
fsl,qe-num-riscs = <4>;
|
||||
fsl,qe-num-snums = <46>;
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
timer@440 {
|
||||
compatible = "fsl,mpc8569-qe-gtm",
|
||||
"fsl,qe-gtm", "fsl,gtm";
|
||||
reg = <0x440 0x40>;
|
||||
interrupts = <12 13 14 15>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
cell-index = <0>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
usb@6c0 {
|
||||
compatible = "fsl,mpc8569-qe-usb",
|
||||
"fsl,mpc8323-qe-usb";
|
||||
reg = <0x6c0 0x40 0x8b00 0x100>;
|
||||
interrupts = <11>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3000 {
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3200 {
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3400 {
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3600 {
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x20000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
67
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
Normal file
67
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* MPC8569 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8569";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8569@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
sleep = <&pmc 0x00008000 // core
|
||||
&pmc 0x00004000>; // timebase
|
||||
};
|
||||
};
|
||||
};
|
||||
196
arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
Normal file
196
arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* MPC8572 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <24 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <24 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <25 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
/include/ "pq3-dma-1.dtsi"
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
gpio-controller@f000 {
|
||||
compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2,1M
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-timer-0.dtsi"
|
||||
|
||||
ptp_clock@24e00 {
|
||||
interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
/include/ "pq3-etsec1-3.dtsi"
|
||||
/include/ "pq3-sec3.0-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue