mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
142
arch/powerpc/boot/dts/a3m071.dts
Normal file
142
arch/powerpc/boot/dts/a3m071.dts
Normal file
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@ -0,0 +1,142 @@
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|||
/*
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* a3m071 board Device Tree Source
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*
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* Copyright 2012 Stefan Roese <sr@denx.de>
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*
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* Copyright (C) 2011 DENX Software Engineering GmbH
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* Heiko Schocher <hs@denx.de>
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*
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* Copyright (C) 2007 Semihalf
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* Marian Balakowicz <m8@semihalf.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
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* option) any later version.
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*/
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/include/ "mpc5200b.dtsi"
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&gpt0 { fsl,has-wdt; };
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/ {
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model = "anonymous,a3m071";
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compatible = "anonymous,a3m071";
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0 0xf0000000 0x0000c000>;
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reg = <0xf0000000 0x00000100>;
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bus-frequency = <0>; /* From boot loader */
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system-frequency = <0>; /* From boot loader */
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spi@f00 {
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status = "disabled";
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};
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usb: usb@1000 {
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status = "disabled";
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};
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psc@2000 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2000 0x100>;
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interrupts = <2 1 0>;
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};
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psc@2200 {
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status = "disabled";
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};
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psc@2400 {
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status = "disabled";
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};
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psc@2600 {
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status = "disabled";
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};
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psc@2800 {
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status = "disabled";
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};
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psc@2c00 { // PSC6
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2c00 0x100>;
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interrupts = <2 4 0>;
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};
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ethernet@3000 {
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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phy0: ethernet-phy@3 {
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reg = <0x03>;
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};
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};
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ata@3a00 {
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status = "disabled";
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};
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i2c@3d00 {
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status = "disabled";
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};
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i2c@3d40 {
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status = "disabled";
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};
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};
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localbus {
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compatible = "fsl,mpc5200b-lpb","simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xfc000000 0x02000000
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3 0 0xe9000000 0x00080000
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5 0 0xe8000000 0x00010000>;
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0 0x0 0x02000000>;
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compatible = "cfi-flash";
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bank-width = <2>;
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partition@0x0 {
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label = "u-boot";
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reg = <0x00000000 0x00040000>;
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read-only;
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};
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partition@0x00040000 {
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label = "env";
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reg = <0x00040000 0x00020000>;
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};
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partition@0x00060000 {
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label = "dtb";
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reg = <0x00060000 0x00020000>;
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};
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partition@0x00080000 {
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label = "kernel";
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reg = <0x00080000 0x00500000>;
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};
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partition@0x00580000 {
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label = "root";
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reg = <0x00580000 0x00A80000>;
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};
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};
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fpga@3,0 {
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compatible = "anonymous,a3m071-fpga";
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reg = <3 0x0 0x00080000
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5 0x0 0x00010000>;
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interrupts = <0 0 3>; /* level low */
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};
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};
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pci@f0000d00 {
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status = "disabled";
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};
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};
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151
arch/powerpc/boot/dts/a4m072.dts
Normal file
151
arch/powerpc/boot/dts/a4m072.dts
Normal file
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|
@ -0,0 +1,151 @@
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|||
/*
|
||||
* a4m072 board Device Tree Source
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||||
*
|
||||
* Copyright (C) 2011 DENX Software Engineering GmbH
|
||||
* Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
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/include/ "mpc5200b.dtsi"
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&gpt0 { fsl,has-wdt; };
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&gpt3 { gpio-controller; };
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&gpt4 { gpio-controller; };
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&gpt5 { gpio-controller; };
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/ {
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model = "anonymous,a4m072";
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compatible = "anonymous,a4m072";
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0 0xf0000000 0x0000c000>;
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reg = <0xf0000000 0x00000100>;
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bus-frequency = <0>; /* From boot loader */
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system-frequency = <0>; /* From boot loader */
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cdm@200 {
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fsl,init-ext-48mhz-en = <0x0>;
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fsl,init-fd-enable = <0x01>;
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fsl,init-fd-counters = <0x3333>;
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};
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spi@f00 {
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status = "disabled";
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};
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psc@2000 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2000 0x100>;
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interrupts = <2 1 0>;
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};
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psc@2200 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2200 0x100>;
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interrupts = <2 2 0>;
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};
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psc@2400 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2400 0x100>;
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interrupts = <2 3 0>;
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};
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psc@2600 {
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status = "disabled";
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};
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psc@2800 {
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status = "disabled";
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};
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psc@2c00 {
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2c00 0x100>;
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interrupts = <2 4 0>;
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};
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ethernet@3000 {
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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phy0: ethernet-phy@1f {
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reg = <0x1f>;
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interrupts = <1 2 0>; /* IRQ 2 active low */
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};
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};
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i2c@3d00 {
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status = "disabled";
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};
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i2c@3d40 {
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hwmon@2e {
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compatible = "nsc,lm87";
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reg = <0x2e>;
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};
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rtc@51 {
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compatible = "nxp,rtc8564";
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reg = <0x51>;
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};
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};
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};
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localbus {
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compatible = "fsl,mpc5200b-lpb","simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xfe000000 0x02000000
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1 0 0x62000000 0x00400000
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2 0 0x64000000 0x00200000
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3 0 0x66000000 0x01000000
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6 0 0x68000000 0x01000000
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7 0 0x6a000000 0x00000004>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x02000000>;
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bank-width = <2>;
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#size-cells = <1>;
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#address-cells = <1>;
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};
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sram0@1,0 {
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compatible = "mtd-ram";
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reg = <1 0x00000 0x00400000>;
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bank-width = <2>;
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};
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};
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pci@f0000d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "fsl,mpc5200-pci";
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reg = <0xf0000d00 0x100>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x16 */
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0xc000 0 0 1 &mpc5200_pic 1 3 3
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0xc000 0 0 2 &mpc5200_pic 1 3 3
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0xc000 0 0 3 &mpc5200_pic 1 3 3
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0xc000 0 0 4 &mpc5200_pic 1 3 3>;
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clock-frequency = <0>; /* From boot loader */
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interrupts = <2 8 0 2 9 0 2 10 0>;
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bus-range = <0 0>;
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ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
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0x02000000 0 0x90000000 0x90000000 0 0x10000000
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0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
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};
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};
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399
arch/powerpc/boot/dts/ac14xx.dts
Normal file
399
arch/powerpc/boot/dts/ac14xx.dts
Normal file
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@ -0,0 +1,399 @@
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/*
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* Device Tree Source for the MPC5121e based ac14xx board
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*
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* Copyright 2012 Anatolij Gustschin <agust@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
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*/
|
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#include <mpc5121.dtsi>
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/ {
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model = "ac14xx";
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compatible = "ifm,ac14xx", "fsl,mpc5121";
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#address-cells = <1>;
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#size-cells = <1>;
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||||
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aliases {
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serial0 = &serial0;
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serial1 = &serial7;
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spi4 = &spi4;
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||||
spi5 = &spi5;
|
||||
};
|
||||
|
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cpus {
|
||||
PowerPC,5121@0 {
|
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timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
|
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bus-frequency = <160000000>; /* 160 MHz csb bus */
|
||||
clock-frequency = <400000000>; /* 400 MHz ppc core */
|
||||
};
|
||||
};
|
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|
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memory {
|
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reg = <0x00000000 0x10000000>; /* 256MB at 0 */
|
||||
};
|
||||
|
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nfc@40000000 {
|
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status = "disabled";
|
||||
};
|
||||
|
||||
localbus@80000020 {
|
||||
ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
|
||||
0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
|
||||
0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
|
||||
0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
|
||||
0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
|
||||
0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
|
||||
partition@0 {
|
||||
label = "dtb-kernel-production";
|
||||
reg = <0x00000000 0x00400000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "filesystem-production";
|
||||
reg = <0x00400000 0x03400000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "recovery";
|
||||
reg = <0x03800000 0x00700000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "uboot-code";
|
||||
reg = <0x03f00000 0x00040000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "uboot-env1";
|
||||
reg = <0x03f40000 0x00020000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "uboot-env2";
|
||||
reg = <0x03f60000 0x00020000>;
|
||||
};
|
||||
};
|
||||
|
||||
fram@1,0 {
|
||||
compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
|
||||
reg = <1 0x00000000 0x00010000>;
|
||||
};
|
||||
|
||||
asi@2,0 {
|
||||
/* masters mapping: CS, CS offset, size */
|
||||
reg = <2 0x00000000 0x00080000
|
||||
6 0x00000000 0x00080000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ifm,ac14xx-asi-fpga";
|
||||
gpios = <
|
||||
&gpio_pic 26 0 /* prog */
|
||||
&gpio_pic 27 0 /* done */
|
||||
&gpio_pic 10 0 /* reset */
|
||||
>;
|
||||
|
||||
master@1 {
|
||||
interrupts = <20 0x2>;
|
||||
interrupt-parent = <&gpio_pic>;
|
||||
chipselect = <2 0x00009000 0x00009100>;
|
||||
label = "AS-i master 1";
|
||||
};
|
||||
|
||||
master@2 {
|
||||
interrupts = <21 0x2>;
|
||||
interrupt-parent = <&gpio_pic>;
|
||||
chipselect = <6 0x00009000 0x00009100>;
|
||||
label = "AS-i master 2";
|
||||
};
|
||||
};
|
||||
|
||||
netx@3,0 {
|
||||
compatible = "ifm,netx";
|
||||
reg = <0x3 0x00000000 0x00020000>;
|
||||
chipselect = <3 0x00101140 0x00203100>;
|
||||
interrupts = <17 0x8>;
|
||||
gpios = <&gpio_pic 15 0>;
|
||||
};
|
||||
|
||||
safety@5,0 {
|
||||
compatible = "ifm,safety";
|
||||
reg = <0x5 0x00000000 0x00010000>;
|
||||
chipselect = <5 0x00009000 0x00009100>;
|
||||
interrupts = <22 0x2>;
|
||||
interrupt-parent = <&gpio_pic>;
|
||||
gpios = <
|
||||
&gpio_pic 12 0 /* prog */
|
||||
&gpio_pic 11 0 /* done */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
osc {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@80000000 {
|
||||
bus-frequency = <80000000>; /* 80 MHz ips bus */
|
||||
|
||||
clock@f00 {
|
||||
compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
|
||||
};
|
||||
|
||||
/*
|
||||
* GPIO PIC:
|
||||
* interrupts cell = <pin nr, sense>
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
gpio_pic: gpio@1100 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sdhc@1500 {
|
||||
cd-gpios = <&gpio_pic 23 0>; /* card detect */
|
||||
wp-gpios = <&gpio_pic 24 0>; /* write protect */
|
||||
wp-inverted; /* WP active high */
|
||||
};
|
||||
|
||||
i2c@1700 {
|
||||
/* use Fast-mode */
|
||||
clock-frequency = <400000>;
|
||||
|
||||
at24@30 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x30>;
|
||||
};
|
||||
|
||||
at24@31 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x31>;
|
||||
};
|
||||
|
||||
temp@48 {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
at24@51 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
at24@52 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
at24@53 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x53>;
|
||||
};
|
||||
|
||||
at24@54 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
at24@55 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x55>;
|
||||
};
|
||||
|
||||
at24@56 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x56>;
|
||||
};
|
||||
|
||||
at24@57 {
|
||||
compatible = "at24,24c01";
|
||||
reg = <0x57>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t00";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
axe_pic: axe-base@2000 {
|
||||
compatible = "fsl,mpc5121-axe-base";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
axe-app {
|
||||
compatible = "fsl,mpc5121-axe-app";
|
||||
interrupt-parent = <&axe_pic>;
|
||||
interrupts = <
|
||||
/* soft interrupts */
|
||||
0 0x0 1 0x0 2 0x0 3 0x0
|
||||
4 0x0 5 0x0 6 0x0 7 0x0
|
||||
/* fifo interrupts */
|
||||
8 0x0 9 0x0 10 0x0 11 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
display@2100 {
|
||||
edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
|
||||
0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
|
||||
1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
|
||||
01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
|
||||
21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
|
||||
3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
|
||||
54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
|
||||
00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
|
||||
};
|
||||
|
||||
can@2300 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can@2380 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
viu@2400 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@2800 {
|
||||
phy0: ethernet-phy@1f {
|
||||
compatible = "smsc,lan8700";
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
enet: ethernet@2800 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
usb@3000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@4000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* PSC3 serial port A, aka ttyPSC0 */
|
||||
serial0: psc@11300 {
|
||||
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
|
||||
fsl,rx-fifo-size = <512>;
|
||||
fsl,tx-fifo-size = <512>;
|
||||
};
|
||||
|
||||
/* PSC4 in SPI mode */
|
||||
spi4: psc@11400 {
|
||||
compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
|
||||
fsl,rx-fifo-size = <768>;
|
||||
fsl,tx-fifo-size = <768>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
num-cs = <1>;
|
||||
cs-gpios = <&gpio_pic 25 0>;
|
||||
|
||||
flash: m25p128@0 {
|
||||
compatible = "st,m25p128";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "spi-flash0";
|
||||
reg = <0x00000000 0x01000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* PSC5 in SPI mode */
|
||||
spi5: psc@11500 {
|
||||
compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
|
||||
fsl,mode = "spi-master";
|
||||
fsl,rx-fifo-size = <128>;
|
||||
fsl,tx-fifo-size = <128>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
lcd@0 {
|
||||
compatible = "ilitek,ili922x";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <100000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
/* PSC7 serial port C, aka ttyPSC2 */
|
||||
serial7: psc@11700 {
|
||||
compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
|
||||
fsl,rx-fifo-size = <512>;
|
||||
fsl,tx-fifo-size = <512>;
|
||||
};
|
||||
|
||||
matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <1>;
|
||||
gpio-activelow;
|
||||
col-gpios-binary;
|
||||
col-switch-delay-ms = <200>;
|
||||
|
||||
col-gpios = <&gpio_pic 1 0>; /* pin1 */
|
||||
|
||||
row-gpios = <&gpio_pic 2 0 /* pin2 */
|
||||
&gpio_pic 3 0 /* pin3 */
|
||||
&gpio_pic 4 0>; /* pin4 */
|
||||
|
||||
linux,keymap = <0x0000006e /* FN LEFT */
|
||||
0x01000067 /* UP */
|
||||
0x02000066 /* FN RIGHT */
|
||||
0x00010069 /* LEFT */
|
||||
0x0101006a /* DOWN */
|
||||
0x0201006c>; /* RIGHT */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
backlight {
|
||||
label = "backlight";
|
||||
gpios = <&gpio_pic 0 0>;
|
||||
default-state = "keep";
|
||||
};
|
||||
green {
|
||||
label = "green";
|
||||
gpios = <&gpio_pic 18 0>;
|
||||
default-state = "keep";
|
||||
};
|
||||
red {
|
||||
label = "red";
|
||||
gpios = <&gpio_pic 19 0>;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
224
arch/powerpc/boot/dts/acadia.dts
Normal file
224
arch/powerpc/boot/dts/acadia.dts
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Acadia (405EZ)
|
||||
*
|
||||
* Copyright IBM Corp. 2008
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,acadia";
|
||||
compatible = "amcc,acadia";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EZ";
|
||||
reg = <0x0>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
timebase-frequency = <0>; /* Filled in by wrapper */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>;
|
||||
d-cache-size = <16384>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>; /* Filled in by wrapper */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405ez", "ibm,uic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
cell-index = <0>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-405ez", "ibm,plb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405ez", "ibm,mcmal";
|
||||
dcr-reg = <0x380 0x62>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
/* 405EZ has only 3 interrupts to the UIC, as
|
||||
* SERR, TXDE, and RXDE are or'd together into
|
||||
* one UIC bit
|
||||
*/
|
||||
interrupts = <
|
||||
0x13 0x4 /* TXEOB */
|
||||
0x15 0x4 /* RXEOB */
|
||||
0x12 0x4 /* SERR, TXDE, RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ez", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dcr-reg = <0x0a 0x05>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x8>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x5 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x8>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x6 0x4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405ez", "ibm,iic";
|
||||
reg = <0xef600500 0x11>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0xa 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@ef600700 {
|
||||
compatible = "ibm,gpio-405ez";
|
||||
reg = <0xef600700 0x20>;
|
||||
};
|
||||
|
||||
GPIO1: gpio@ef600800 {
|
||||
compatible = "ibm,gpio-405ez";
|
||||
reg = <0xef600800 0x20>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ez", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0x10 0x4 /* Ethernet */
|
||||
0x11 0x4 /* Ethernet Wake up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by wrapper */
|
||||
reg = <0xef600900 0x70>;
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "mii";
|
||||
phy-map = <0x0>;
|
||||
};
|
||||
|
||||
CAN0: can@ef601000 {
|
||||
compatible = "amcc,can-405ez";
|
||||
reg = <0xef601000 0x620>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
CAN1: can@ef601800 {
|
||||
compatible = "amcc,can-405ez";
|
||||
reg = <0xef601800 0x620>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x8 0x4>;
|
||||
};
|
||||
|
||||
cameleon@ef602000 {
|
||||
compatible = "amcc,cameleon-405ez";
|
||||
reg = <0xef602000 0x800>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0xb 0x4 0xc 0x4>;
|
||||
};
|
||||
|
||||
ieee1588@ef602800 {
|
||||
compatible = "amcc,ieee1588-405ez";
|
||||
reg = <0xef602800 0x60>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x4 0x4>;
|
||||
/* This thing is a bit weird. It has it's own UIC
|
||||
* that it uses to generate snapshot triggers. We
|
||||
* don't really support this device yet, and it needs
|
||||
* work to figure this out.
|
||||
*/
|
||||
dcr-reg = <0xe0 0x9>;
|
||||
};
|
||||
|
||||
usb@ef603000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0xef603000 0x80>;
|
||||
interrupts-parent = <&UIC0>;
|
||||
interrupts = <0xd 0x4 0xe 0x4>;
|
||||
};
|
||||
|
||||
dac@ef603300 {
|
||||
compatible = "amcc,dac-405ez";
|
||||
reg = <0xef603300 0x40>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x18 0x4>;
|
||||
};
|
||||
|
||||
adc@ef603400 {
|
||||
compatible = "amcc,adc-405ez";
|
||||
reg = <0xef603400 0x40>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x17 0x4>;
|
||||
};
|
||||
|
||||
spi@ef603500 {
|
||||
compatible = "amcc,spi-405ez";
|
||||
reg = <0xef603500 0x100>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x9 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ez", "ibm,ebc";
|
||||
dcr-reg = <0x12 0x2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by wrapper */
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
183
arch/powerpc/boot/dts/adder875-redboot.dts
Normal file
183
arch/powerpc/boot/dts/adder875-redboot.dts
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* Device Tree Source for MPC885 ADS running RedBoot
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Analogue & Micro Adder MPC875";
|
||||
compatible = "analogue-and-micro,adder875";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
console = &console;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,875@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus@fa200100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xfa200100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xfe000000 0x00800000
|
||||
2 0 0xfa100000 0x00008000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@fa200000 {
|
||||
compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xfa200000 0x00004000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary until get_immrbase() is fixed.
|
||||
reg = <0xfa200000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x24>;
|
||||
compatible = "fsl,mpc875-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus";
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc875-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
clock-frequency = <50000000>;
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc875-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
console: serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc875-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x0090>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &console;
|
||||
};
|
||||
};
|
||||
182
arch/powerpc/boot/dts/adder875-uboot.dts
Normal file
182
arch/powerpc/boot/dts/adder875-uboot.dts
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* Device Tree Source for MPC885 ADS running U-Boot
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Analogue & Micro Adder MPC875";
|
||||
compatible = "analogue-and-micro,adder875";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
console = &console;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,875@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus@ff000100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xff000100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xfe000000 0x01000000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@ff000000 {
|
||||
compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff000000 0x00004000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary until get_immrbase() is fixed.
|
||||
reg = <0xff000000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x24>;
|
||||
compatible = "fsl,mpc875-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus";
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc875-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
clock-frequency = <50000000>;
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc875-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
console: serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc875-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x0090>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &console;
|
||||
};
|
||||
};
|
||||
415
arch/powerpc/boot/dts/akebono.dts
Normal file
415
arch/powerpc/boot/dts/akebono.dts
Normal file
|
|
@ -0,0 +1,415 @@
|
|||
/*
|
||||
* Device Tree Source for IBM Embedded PPC 476 Platform
|
||||
*
|
||||
* Copyright © 2013 Tony Breeds IBM Corporation
|
||||
* Copyright © 2013 Alistair Popple IBM Corporation
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x01f00000 0x00100000; // spin table
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "ibm,akebono";
|
||||
compatible = "ibm,akebono", "ibm,476gtr";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
serial0 = &UART0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <0>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "ok";
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <1>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "disabled";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x01f00000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
|
||||
};
|
||||
|
||||
MPIC: interrupt-controller {
|
||||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0xffc00000 0x00040000>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
single-cpu-affinity;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb6";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
clock-frequency = <200000000>; // 200Mhz
|
||||
|
||||
HSTA0: hsta@310000e0000 {
|
||||
compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
|
||||
reg = <0x310 0x000e0000 0x0 0xf0>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <108 0
|
||||
109 0
|
||||
110 0
|
||||
111 0
|
||||
112 0
|
||||
113 0
|
||||
114 0
|
||||
115 0
|
||||
116 0
|
||||
117 0
|
||||
118 0
|
||||
119 0
|
||||
120 0
|
||||
121 0
|
||||
122 0
|
||||
123 0>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
|
||||
dcr-reg = <0xc0000000 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = < /*TXEOB*/ 77 0x4
|
||||
/*RXEOB*/ 78 0x4
|
||||
/*SERR*/ 76 0x4
|
||||
/*TXDE*/ 79 0x4
|
||||
/*RXDE*/ 80 0x4>;
|
||||
};
|
||||
|
||||
SATA0: sata@30000010000 {
|
||||
compatible = "ibm,476gtr-ahci";
|
||||
reg = <0x300 0x00010000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <93 2>;
|
||||
};
|
||||
|
||||
EHCI0: ehci@30010000000 {
|
||||
compatible = "ibm,476gtr-ehci", "generic-ehci";
|
||||
reg = <0x300 0x10000000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <85 2>;
|
||||
};
|
||||
|
||||
SD0: sd@30000000000 {
|
||||
compatible = "ibm,476gtr-sdhci", "generic-sdhci";
|
||||
reg = <0x300 0x00000000 0x0 0x10000>;
|
||||
interrupts = <91 2>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
};
|
||||
|
||||
OHCI0: ohci@30010010000 {
|
||||
compatible = "ibm,476gtr-ohci", "generic-ohci";
|
||||
reg = <0x300 0x10010000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <89 1>;
|
||||
};
|
||||
|
||||
OHCI1: ohci@30010020000 {
|
||||
compatible = "ibm,476gtr-ohci", "generic-ohci";
|
||||
reg = <0x300 0x10020000 0x0 0x10000>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <88 1>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-4xx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full
|
||||
* 32-bit range
|
||||
*/
|
||||
ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
|
||||
0x80000000 0x0000033f 0x80000000 0x80000000>;
|
||||
clock-frequency = <100000000>;
|
||||
|
||||
RGMII0: emac-rgmii-wol@50004 {
|
||||
compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
|
||||
reg = <0x50004 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@30000 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-476gtr", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
|
||||
/*Wake*/ 0x1 &MPIC 82 0x4>;
|
||||
reg = <0x30000 0x78>;
|
||||
|
||||
/* local-mac-address will normally be added by
|
||||
* the wrapper. If your device doesn't support
|
||||
* passing data to the wrapper (in the form
|
||||
* local-mac-addr=<hwaddr>) then you will need
|
||||
* to set it manually here. */
|
||||
//local-mac-address = [000000000000];
|
||||
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-wol-device = <&RGMII0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
UART0: serial@10000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16750", "ns16550";
|
||||
reg = <0x10000 0x00000008>;
|
||||
virtual-reg = <0xe8010000>;
|
||||
clock-frequency = <1851851>;
|
||||
current-speed = <38400>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <39 2>;
|
||||
};
|
||||
|
||||
IIC0: i2c@00000000 {
|
||||
compatible = "ibm,iic-476gtr", "ibm,iic";
|
||||
reg = <0x0 0x00000020>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <37 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80", "m41st85";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@00000100 {
|
||||
compatible = "ibm,iic-476gtr", "ibm,iic";
|
||||
reg = <0x100 0x00000020>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <38 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
avr@58 {
|
||||
compatible = "ibm,akebono-avr";
|
||||
reg = <0x58>;
|
||||
};
|
||||
};
|
||||
|
||||
FPGA0: fpga@ebc00000 {
|
||||
compatible = "ibm,akebono-fpga";
|
||||
reg = <0xebc00000 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@10100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xc0 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@20100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x100 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@18100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xe0 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE3: pciex@28100000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x3>; /* port number */
|
||||
reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x120 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
|
||||
* PCI devices must be able to write to the HSTA module.
|
||||
*/
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &UART0;
|
||||
};
|
||||
};
|
||||
173
arch/powerpc/boot/dts/amigaone.dts
Normal file
173
arch/powerpc/boot/dts/amigaone.dts
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* AmigaOne Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "AmigaOne";
|
||||
compatible = "eyetech,amigaone";
|
||||
coherency-off;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#cpus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <0>; // 33.3 MHz, from U-boot
|
||||
clock-frequency = <0>; // From U-boot
|
||||
bus-frequency = <0>; // From U-boot
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; // From U-boot
|
||||
};
|
||||
|
||||
pci@80000000 {
|
||||
device_type = "pci";
|
||||
compatible = "mai-logic,articia-s";
|
||||
bus-frequency = <33333333>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
|
||||
0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
|
||||
0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA)
|
||||
// Configuration address and data register.
|
||||
reg = <0xfec00cf8 4
|
||||
0xfee00cfc 4>;
|
||||
8259-interrupt-acknowledge = <0xfef00000>;
|
||||
// Do not define a interrupt-parent here, if there is no
|
||||
// interrupt-map property.
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
isa@7 {
|
||||
device_type = "isa";
|
||||
compatible = "pciclass,0601";
|
||||
vendor-id = <0x00001106>;
|
||||
device-id = <0x00000686>;
|
||||
revision-id = <0x00000010>;
|
||||
class-code = <0x00060100>;
|
||||
subsystem-id = <0>;
|
||||
subsystem-vendor-id = <0>;
|
||||
devsel-speed = <0x00000001>;
|
||||
min-grant = <0>;
|
||||
max-latency = <0>;
|
||||
/* First 4k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
|
||||
ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00001000>;
|
||||
interrupt-parent = <&i8259>;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
dma-controller@0 {
|
||||
compatible = "pnpPNP,200";
|
||||
reg = <1 0x00000000 0x00000020
|
||||
1 0x00000080 0x00000010
|
||||
1 0x000000c0 0x00000020>;
|
||||
};
|
||||
|
||||
i8259: interrupt-controller@20 {
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "pnpPNP,000";
|
||||
interrupt-controller;
|
||||
reg = <1 0x00000020 0x00000002
|
||||
1 0x000000a0 0x00000002
|
||||
1 0x000004d0 0x00000002>;
|
||||
reserved-interrupts = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
timer@40 {
|
||||
// Also adds pcspkr to platform devices.
|
||||
compatible = "pnpPNP,100";
|
||||
reg = <1 0x00000040 0x00000020>;
|
||||
};
|
||||
|
||||
8042@60 {
|
||||
device_type = "8042";
|
||||
reg = <1 0x00000060 0x00000001
|
||||
1 0x00000064 0x00000001>;
|
||||
interrupts = <1 3 12 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
keyboard@0 {
|
||||
compatible = "pnpPNP,303";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
mouse@1 {
|
||||
compatible = "pnpPNP,f03";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@70 {
|
||||
compatible = "pnpPNP,b00";
|
||||
reg = <1 0x00000070 0x00000002>;
|
||||
interrupts = <8 3>;
|
||||
};
|
||||
|
||||
serial@3f8 {
|
||||
device_type = "serial";
|
||||
compatible = "pnpPNP,501","pnpPNP,500";
|
||||
reg = <1 0x000003f8 0x00000008>;
|
||||
interrupts = <4 3>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
serial@2f8 {
|
||||
device_type = "serial";
|
||||
compatible = "pnpPNP,501","pnpPNP,500";
|
||||
reg = <1 0x000002f8 0x00000008>;
|
||||
interrupts = <3 3>;
|
||||
clock-frequency = <1843200>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
parallel@378 {
|
||||
device_type = "parallel";
|
||||
// No ECP support for now, otherwise add "pnpPNP,401".
|
||||
compatible = "pnpPNP,400";
|
||||
reg = <1 0x00000378 0x00000003
|
||||
1 0x00000778 0x00000003>;
|
||||
};
|
||||
|
||||
fdc@3f0 {
|
||||
device_type = "fdc";
|
||||
compatible = "pnpPNP,700";
|
||||
reg = <1 0x000003f0 0x00000008>;
|
||||
interrupts = <6 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
disk@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/pci@80000000/isa@7/serial@3f8";
|
||||
};
|
||||
};
|
||||
355
arch/powerpc/boot/dts/arches.dts
Normal file
355
arch/powerpc/boot/dts/arches.dts
Normal file
|
|
@ -0,0 +1,355 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Arches (dual 460GT board)
|
||||
*
|
||||
* (C) Copyright 2008 Applied Micro Circuits Corporation
|
||||
* Victor Gallardo <vgallardo@amcc.com>
|
||||
* Adam Graham <agraham@amcc.com>
|
||||
*
|
||||
* Based on the glacier.dts file
|
||||
* Stefan Roese <sr@denx.de>
|
||||
* Copyright 2008 DENX Software Engineering
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,arches";
|
||||
compatible = "amcc,arches";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
ethernet2 = &EMAC2;
|
||||
serial0 = &UART0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460GT";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-460gt","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460gt";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460gt";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
|
||||
dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
|
||||
0x030 0x008>; /* L2 cache DCR's */
|
||||
cache-line-size = <32>; /* 32 bytes */
|
||||
cache-size = <262144>; /* L2, 256K */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <11 1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-460gt", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
CRYPTO: crypto@180000 {
|
||||
compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
|
||||
reg = <4 0x00180000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <3>;
|
||||
num-rx-chans = <24>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
desc-base-addr-high = <0x8>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460gt", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460gt", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl256n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x02000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <0x00400000 0x01b60000>;
|
||||
};
|
||||
partition@1f60000 {
|
||||
label = "env";
|
||||
reg = <0x01f60000 0x00040000>;
|
||||
};
|
||||
partition@1fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x01fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460gt", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
sttm@4a {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x4a>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x0 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460gt", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460gt", "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460gt", "ibm,tah";
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "sgmii";
|
||||
phy-map = <0xffffffff>;
|
||||
gpcs-address = <0x0000000a>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "sgmii";
|
||||
phy-map = <0x00000000>;
|
||||
gpcs-address = <0x0000000b>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
|
||||
EMAC2: ethernet@ef601100 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC2>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x16 0x4>;
|
||||
reg = <0xef601100 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <16>;
|
||||
cell-index = <2>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
||||
phy-mode = "sgmii";
|
||||
phy-map = <0x00000001>;
|
||||
gpcs-address = <0x0000000C>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
310
arch/powerpc/boot/dts/asp834x-redboot.dts
Normal file
310
arch/powerpc/boot/dts/asp834x-redboot.dts
Normal file
|
|
@ -0,0 +1,310 @@
|
|||
/*
|
||||
* Analogue & Micro ASP8347 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Codehermit
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "Analogue & Micro ASP8347E";
|
||||
compatible = "analogue-and-micro,asp8347e";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8347@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x8000000>; // 128MB at 0
|
||||
};
|
||||
|
||||
localbus@ff005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8347e-localbus",
|
||||
"fsl,pq2pro-localbus",
|
||||
"simple-bus";
|
||||
reg = <0xff005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xf0000000 0x02000000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc8349@ff000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xff000000 0x00100000>;
|
||||
reg = <0xff000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
|
||||
reg = <0x82a8 4>;
|
||||
ranges = <0 0x8100 0x1a8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
|
||||
reg = <0x180 0x28>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <71 8>;
|
||||
};
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port0;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
local-mac-address = [ 00 08 e5 11 32 33 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-handle = <&phy0>;
|
||||
linux,network-index = <0>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 08 e5 11 32 34 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
linux,network-index = <1>;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <400000000>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <400000000>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
|
||||
linux,stdout-path = &serial0;
|
||||
};
|
||||
|
||||
};
|
||||
50
arch/powerpc/boot/dts/b4420qds.dts
Normal file
50
arch/powerpc/boot/dts/b4420qds.dts
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* B4420DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/include/ "fsl/b4420si-pre.dtsi"
|
||||
/include/ "b4qds.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,B4420QDS";
|
||||
compatible = "fsl,B4420QDS";
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4420si-post.dtsi"
|
||||
223
arch/powerpc/boot/dts/b4860emu.dts
Normal file
223
arch/powerpc/boot/dts/b4860emu.dts
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
/*
|
||||
* B4860 emulator Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl/e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4860";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
model = "fsl,B4860QDS";
|
||||
compatible = "fsl,B4860EMU", "fsl,B4860QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 2>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 9>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 4>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 0>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
fsl,portid-mapping = <0x8000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 1>;
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <8 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4-device-config";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "fsl/qoriq-i2c-0.dtsi"
|
||||
/include/ "fsl/qoriq-i2c-1.dtsi"
|
||||
/include/ "fsl/qoriq-duart-0.dtsi"
|
||||
/include/ "fsl/qoriq-duart-1.dtsi"
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4-l2-cache-controller";
|
||||
reg = <0xc20000 0x1000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
61
arch/powerpc/boot/dts/b4860qds.dts
Normal file
61
arch/powerpc/boot/dts/b4860qds.dts
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* B4860DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/b4860si-pre.dtsi"
|
||||
/include/ "b4qds.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,B4860QDS";
|
||||
compatible = "fsl,B4860QDS";
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
reg = <0xf 0xfe0c0000 0 0x11000>;
|
||||
|
||||
port1 {
|
||||
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
|
||||
};
|
||||
port2 {
|
||||
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4860si-post.dtsi"
|
||||
182
arch/powerpc/boot/dts/b4qds.dtsi
Normal file
182
arch/powerpc/boot/dts/b4qds.dtsi
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/*
|
||||
* B4420DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "fsl,B4QDS";
|
||||
compatible = "fsl,B4QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x2 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 10MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x00A00000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
/* 500MB for Root file System Image */
|
||||
reg = <0x00c00000 0x1F400000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
|
||||
reg = <3 0 0x300>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01052000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
};
|
||||
|
||||
sdhc@114000 {
|
||||
/*Disabled as there is no sdhc connector on B4420QDS board*/
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "at24,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@57 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x57>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb@210000 {
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
reg = <0xf 0xfe200000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4si-post.dtsi"
|
||||
300
arch/powerpc/boot/dts/bamboo.dts
Normal file
300
arch/powerpc/boot/dts/bamboo.dts
Normal file
|
|
@ -0,0 +1,300 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Bamboo
|
||||
*
|
||||
* Copyright (c) 2006, 2007 IBM Corp.
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* FIXME: Draft only!
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,bamboo";
|
||||
compatible = "amcc,bamboo";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
serial3 = &UART3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440EP";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440ep","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440ep";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440ep";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440ep", "ibm,dma-440gp";
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Bamboo is oddball in the 44x world and doesn't use the ERPN
|
||||
* bits.
|
||||
*/
|
||||
ranges = <0x00000000 0x00000000 0x00000000 0x80000000
|
||||
0x80000000 0x00000000 0x80000000 0x80000000>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <0x5 0x1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600500 0x00000008>;
|
||||
virtual-reg = <0xef600500>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600600 0x00000008>;
|
||||
virtual-reg = <0xef600600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x4 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x7 0x4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0xef600e00 0x00000070>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>;
|
||||
reg = <0xef600f00 0x00000070>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2 3>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
||||
usb@ef601000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0xef601000 0x00000080>;
|
||||
interrupts = <0x8 0x1 0x9 0x1>;
|
||||
interrupt-parent = < &UIC1 >;
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0x00000000 0xeec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0xeed00000 0x00000004 /* IACK */
|
||||
0x00000000 0xeed00000 0x00000004 /* Special cycle */
|
||||
0x00000000 0xef400000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x40000000
|
||||
0x02000000 0x00000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* Bamboo has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
|
||||
|
||||
/* IDSEL 2 */
|
||||
0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
|
||||
|
||||
/* IDSEL 3 */
|
||||
0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
|
||||
|
||||
/* IDSEL 4 */
|
||||
0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
410
arch/powerpc/boot/dts/bluestone.dts
Normal file
410
arch/powerpc/boot/dts/bluestone.dts
Normal file
|
|
@ -0,0 +1,410 @@
|
|||
/*
|
||||
* Device Tree for Bluestone (APM821xx) board.
|
||||
*
|
||||
* Copyright (c) 2010, Applied Micro Circuits Corporation
|
||||
* Author: Tirumala R Marri <tmarri@apm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "apm,bluestone";
|
||||
compatible = "apm,bluestone";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,apm821xx";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
OCM: ocm@400040000 {
|
||||
compatible = "ibm,ocm";
|
||||
status = "ok";
|
||||
cell-index = <1>;
|
||||
/* configured in U-Boot */
|
||||
reg = <4 0x00040000 0x8000>; /* 32K */
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-apm821xx";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-apm821xx";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
|
||||
dcr-reg = <0x020 0x008
|
||||
0x030 0x008>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <262144>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <11 1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-apm821xx";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal2";
|
||||
descriptor-memory = "ocm";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x00400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "env";
|
||||
reg = <0x00180000 0x00020000>;
|
||||
};
|
||||
partition@1a0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x001a0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
ndfc@1,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000003 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* 2Gb Nand Flash */
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x00000000 0x00C00000>;
|
||||
};
|
||||
partition@c00000 {
|
||||
label = "environment";
|
||||
reg = <0x00C00000 0x00B00000>;
|
||||
};
|
||||
partition@1700000 {
|
||||
label = "kernel";
|
||||
reg = <0x01700000 0x00E00000>;
|
||||
};
|
||||
partition@2500000 {
|
||||
label = "root";
|
||||
reg = <0x02500000 0x08200000>;
|
||||
};
|
||||
partition@a700000 {
|
||||
label = "device-tree";
|
||||
reg = <0x0A700000 0x00B00000>;
|
||||
};
|
||||
partition@b200000 {
|
||||
label = "config";
|
||||
reg = <0x0B200000 0x00D00000>;
|
||||
};
|
||||
partition@bf00000 {
|
||||
label = "diag";
|
||||
reg = <0x0BF00000 0x00C00000>;
|
||||
};
|
||||
partition@cb00000 {
|
||||
label = "vendor";
|
||||
reg = <0x0CB00000 0x3500000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x9 0x8>;
|
||||
};
|
||||
sttm@4C {
|
||||
compatible = "adm,adm1032";
|
||||
reg = <0x4C>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii";
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600c00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600c00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <16384>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
MSI: ppc4xx-msi@C10000000 {
|
||||
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
|
||||
reg = < 0xC 0x10000000 0x100
|
||||
0xC 0x10000000 0x100>;
|
||||
sdr-base = <0x36C>;
|
||||
msi-data = <0x00004440>;
|
||||
msi-mask = <0x0000ffe0>;
|
||||
interrupts =<0 1 2 3 4 5 6 7>;
|
||||
interrupt-parent = <&MSI>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
msi-available-ranges = <0x0 0x100>;
|
||||
interrupt-map = <
|
||||
0 &UIC3 0x18 1
|
||||
1 &UIC3 0x19 1
|
||||
2 &UIC3 0x1A 1
|
||||
3 &UIC3 0x1B 1
|
||||
4 &UIC3 0x1C 1
|
||||
5 &UIC3 0x1D 1
|
||||
6 &UIC3 0x1E 1
|
||||
7 &UIC3 0x1F 1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
34
arch/powerpc/boot/dts/bsc9131rdb.dts
Normal file
34
arch/powerpc/boot/dts/bsc9131rdb.dts
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* BSC9131 RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "fsl/bsc9131si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,bsc9131rdb";
|
||||
compatible = "fsl,bsc9131rdb";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
board_ifc: ifc: ifc@ff71e000 {
|
||||
/* NAND Flash on board */
|
||||
ranges = <0x0 0x0 0x0 0xff800000 0x00004000>;
|
||||
reg = <0x0 0xff71e000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
board_soc: soc: soc@ff700000 {
|
||||
ranges = <0x0 0x0 0xff700000 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "bsc9131rdb.dtsi"
|
||||
/include/ "fsl/bsc9131si-post.dtsi"
|
||||
142
arch/powerpc/boot/dts/bsc9131rdb.dtsi
Normal file
142
arch/powerpc/boot/dts/bsc9131rdb.dtsi
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* BSC9131 RDB Device Tree Source stub (no addresses or top-level ranges)
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&board_ifc {
|
||||
|
||||
nand@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x0 0x0 0x4000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 3MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00300000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@300000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00300000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
/* 8MB for Linux Kernel Image */
|
||||
reg = <0x00400000 0x00800000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
/* Rest space for Root file System Image */
|
||||
reg = <0x00c00000 0x07400000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&board_soc {
|
||||
/* BSC9131RDB does not have any device on i2c@3100 */
|
||||
i2c@3100 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
partition@0 {
|
||||
reg = <0x0 0x00080000>;
|
||||
label = "SPI Flash U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
/* 512KB for DTB Image */
|
||||
partition@80000 {
|
||||
reg = <0x00080000 0x00080000>;
|
||||
label = "SPI Flash DTB Image";
|
||||
};
|
||||
|
||||
/* 4MB for Linux Kernel Image */
|
||||
partition@100000 {
|
||||
reg = <0x00100000 0x00400000>;
|
||||
label = "SPI Flash Kernel Image";
|
||||
};
|
||||
|
||||
/*11MB for RFS Image */
|
||||
partition@500000 {
|
||||
reg = <0x00500000 0x00B00000>;
|
||||
label = "SPI Flash RFS Image";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupts = <3 1 0 0>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupts = <2 1 0 0>;
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
};
|
||||
35
arch/powerpc/boot/dts/bsc9132qds.dts
Normal file
35
arch/powerpc/boot/dts/bsc9132qds.dts
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* BSC9132 QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "fsl/bsc9132si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,bsc9132qds";
|
||||
compatible = "fsl,bsc9132qds";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
ifc: ifc@ff71e000 {
|
||||
/* NOR, NAND Flash on board */
|
||||
ranges = <0x0 0x0 0x0 0x88000000 0x08000000
|
||||
0x1 0x0 0x0 0xff800000 0x00010000>;
|
||||
reg = <0x0 0xff71e000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
soc: soc@ff700000 {
|
||||
ranges = <0x0 0x0 0xff700000 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "bsc9132qds.dtsi"
|
||||
/include/ "fsl/bsc9132si-post.dtsi"
|
||||
101
arch/powerpc/boot/dts/bsc9132qds.dtsi
Normal file
101
arch/powerpc/boot/dts/bsc9132qds.dtsi
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
fpga: fpga@66 {
|
||||
compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
|
||||
reg = <0x66>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x1f>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
phy-handle = <&phy0>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy1>;
|
||||
tbi-handle = <&tbi0>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
};
|
||||
224
arch/powerpc/boot/dts/c293pcie.dts
Normal file
224
arch/powerpc/boot/dts/c293pcie.dts
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* C293 PCIE Device Tree Source
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/c293si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,C293PCIE";
|
||||
compatible = "fsl,C293PCIE";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
ifc: ifc@fffe1e000 {
|
||||
reg = <0xf 0xffe1e000 0 0x2000>;
|
||||
ranges = <0x0 0x0 0xf 0xec000000 0x04000000
|
||||
0x1 0x0 0xf 0xff800000 0x00010000
|
||||
0x2 0x0 0xf 0xffdf0000 0x00010000>;
|
||||
|
||||
};
|
||||
|
||||
soc: soc@fffe00000 {
|
||||
ranges = <0x0 0xf 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci0: pcie@fffe0a000 {
|
||||
reg = <0xf 0xffe0a000 0 0x1000>;
|
||||
ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
|
||||
pcie@0 {
|
||||
ranges = <0x2000000 0x0 0x80000000
|
||||
0x2000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x1000000 0x0 0x0
|
||||
0x1000000 0x0 0x0
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
partition@0 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NOR DTB Image";
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 8 MB for Linux Kernel Image */
|
||||
reg = <0x00100000 0x00800000>;
|
||||
label = "NOR Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@900000 {
|
||||
/* 53MB for rootfs */
|
||||
reg = <0x00900000 0x03500000>;
|
||||
label = "NOR Rootfs Image";
|
||||
};
|
||||
|
||||
partition@3e00000 {
|
||||
/* 1MB for blob encrypted key */
|
||||
reg = <0x03e00000 0x00100000>;
|
||||
label = "NOR blob encrypted key";
|
||||
};
|
||||
|
||||
partition@3f00000 {
|
||||
/* 512KB for u-boot Bootloader Image and evn */
|
||||
reg = <0x03f00000 0x00100000>;
|
||||
label = "NOR U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 16MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x01000000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@1200000 {
|
||||
/* 4078MB for Root file System Image */
|
||||
reg = <0x00600000 0xfee00000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
|
||||
cpld@2,0 {
|
||||
compatible = "fsl,c293pcie-cpld";
|
||||
reg = <0x2 0x0 0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
i2c@3000 {
|
||||
eeprom@50 {
|
||||
compatible = "st,24c1024";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
adt7461@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,s25sl12801";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
partition@0 {
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
/* 1MB for Environment */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "SPI Flash U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 512KB for DTB Image */
|
||||
reg = <0x00100000 0x00080000>;
|
||||
label = "SPI Flash DTB Image";
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
/* 4MB for Linux Kernel Image */
|
||||
reg = <0x00180000 0x00400000>;
|
||||
label = "SPI Flash Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
/* 10.5MB for RFS Image */
|
||||
reg = <0x00580000 0x00a80000>;
|
||||
label = "SPI Flash RFS Image";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupts = <2 1 0 0>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupts = <2 1 0 0>;
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@b0000 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
enet1: ethernet@b1000 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
};
|
||||
/include/ "fsl/c293si-post.dtsi"
|
||||
366
arch/powerpc/boot/dts/c2k.dts
Normal file
366
arch/powerpc/boot/dts/c2k.dts
Normal file
|
|
@ -0,0 +1,366 @@
|
|||
/* Device Tree Source for GEFanuc C2K
|
||||
*
|
||||
* Author: Remi Machet <rmachet@slac.stanford.edu>
|
||||
*
|
||||
* Originated from prpmc2800.dts
|
||||
*
|
||||
* 2008 (c) Stanford University
|
||||
* 2007 (c) MontaVista, Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "C2K";
|
||||
compatible = "GEFanuc,C2K";
|
||||
coherency-off;
|
||||
|
||||
aliases {
|
||||
pci0 = &PCI0;
|
||||
pci1 = &PCI1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "PowerPC,7447";
|
||||
reg = <0>;
|
||||
clock-frequency = <996000000>; /* 996 MHz */
|
||||
bus-frequency = <166666667>; /* 166.6666 MHz */
|
||||
timebase-frequency = <41666667>; /* 166.6666/4 MHz */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
system-controller@d8000000 { /* Marvell Discovery */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "mv64460";
|
||||
compatible = "marvell,mv64360";
|
||||
clock-frequency = <166666667>; /* 166.66... MHz */
|
||||
reg = <0xd8000000 0x00010000>;
|
||||
virtual-reg = <0xd8000000>;
|
||||
ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
|
||||
0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
|
||||
0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
|
||||
0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
|
||||
0xd8100000 0xd8100000 0x00010000 /* FPGA */
|
||||
0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
|
||||
0xf8000000 0xf8000000 0x08000000 /* User FLASH */
|
||||
0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
|
||||
0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
|
||||
|
||||
mdio@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-mdio";
|
||||
reg = <0x2000 4>;
|
||||
PHY0: ethernet-phy@0 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0>;
|
||||
};
|
||||
PHY1: ethernet-phy@1 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <1>;
|
||||
};
|
||||
PHY2: ethernet-phy@2 {
|
||||
interrupts = <76>; /* GPP 12 */
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-group@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,mv64360-eth-group";
|
||||
reg = <0x2000 0x2000>;
|
||||
ethernet@0 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <0>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY0>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@1 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <1>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
ethernet@2 {
|
||||
device_type = "network";
|
||||
compatible = "marvell,mv64360-eth";
|
||||
reg = <2>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy = <&PHY2>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
};
|
||||
|
||||
SDMA0: sdma@4000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x4000 0xc18>;
|
||||
virtual-reg = <0xd8004000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <36>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
SDMA1: sdma@6000 {
|
||||
compatible = "marvell,mv64360-sdma";
|
||||
reg = <0x6000 0xc18>;
|
||||
virtual-reg = <0xd8006000>;
|
||||
interrupt-base = <0>;
|
||||
interrupts = <38>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
BRG0: brg@b200 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb200 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
BRG1: brg@b208 {
|
||||
compatible = "marvell,mv64360-brg";
|
||||
reg = <0xb208 0x8>;
|
||||
clock-src = <8>;
|
||||
clock-frequency = <133333333>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
|
||||
CUNIT: cunit@f200 {
|
||||
reg = <0xf200 0x200>;
|
||||
};
|
||||
|
||||
MPSCROUTING: mpscrouting@b400 {
|
||||
reg = <0xb400 0xc>;
|
||||
};
|
||||
|
||||
MPSCINTR: mpscintr@b800 {
|
||||
reg = <0xb800 0x100>;
|
||||
virtual-reg = <0xd800b800>;
|
||||
};
|
||||
|
||||
MPSC0: mpsc@8000 {
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x8000 0x38>;
|
||||
virtual-reg = <0xd8008000>;
|
||||
sdma = <&SDMA0>;
|
||||
brg = <&BRG0>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <0>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
MPSC1: mpsc@9000 {
|
||||
compatible = "marvell,mv64360-mpsc";
|
||||
reg = <0x9000 0x38>;
|
||||
virtual-reg = <0xd8009000>;
|
||||
sdma = <&SDMA1>;
|
||||
brg = <&BRG1>;
|
||||
cunit = <&CUNIT>;
|
||||
mpscrouting = <&MPSCROUTING>;
|
||||
mpscintr = <&MPSCINTR>;
|
||||
cell-index = <1>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
wdt@b410 { /* watchdog timer */
|
||||
compatible = "marvell,mv64360-wdt";
|
||||
reg = <0xb410 0x8>;
|
||||
};
|
||||
|
||||
i2c@c000 {
|
||||
compatible = "marvell,mv64360-i2c";
|
||||
reg = <0xc000 0x20>;
|
||||
virtual-reg = <0xd800c000>;
|
||||
interrupts = <37>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
PIC: pic {
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
compatible = "marvell,mv64360-pic";
|
||||
reg = <0x0000 0x88>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
mpp@f000 {
|
||||
compatible = "marvell,mv64360-mpp";
|
||||
reg = <0xf000 0x10>;
|
||||
};
|
||||
|
||||
gpp@f100 {
|
||||
compatible = "marvell,mv64360-gpp";
|
||||
reg = <0xf100 0x20>;
|
||||
};
|
||||
|
||||
PCI0: pci@80000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0cf8 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0c34>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* Only one interrupt line for PMC0 slot (INTA) */
|
||||
0x0000 0 0 1 &PIC 88
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
PCI1: pci@a0000000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "marvell,mv64360-pci";
|
||||
reg = <0x0c78 0x8>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
|
||||
0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <66000000>;
|
||||
interrupt-pci-iack = <0x0cb4>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x01: PMC1 ? */
|
||||
0x0800 0 0 1 &PIC 88
|
||||
/* IDSEL 0x02: cPCI bridge */
|
||||
0x1000 0 0 1 &PIC 88
|
||||
/* IDSEL 0x03: USB controller */
|
||||
0x1800 0 0 1 &PIC 91
|
||||
/* IDSEL 0x04: SATA controller */
|
||||
0x2000 0 0 1 &PIC 95
|
||||
>;
|
||||
};
|
||||
|
||||
cpu-error@0070 {
|
||||
compatible = "marvell,mv64360-cpu-error";
|
||||
reg = <0x0070 0x10 0x0128 0x28>;
|
||||
interrupts = <3>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
sram-ctrl@0380 {
|
||||
compatible = "marvell,mv64360-sram-ctrl";
|
||||
reg = <0x0380 0x80>;
|
||||
interrupts = <13>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1d40 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1d40 0x40 0x0c28 0x4>;
|
||||
interrupts = <12>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
pci-error@1dc0 {
|
||||
compatible = "marvell,mv64360-pci-error";
|
||||
reg = <0x1dc0 0x40 0x0ca8 0x4>;
|
||||
interrupts = <16>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
|
||||
mem-ctrl@1400 {
|
||||
compatible = "marvell,mv64360-mem-ctrl";
|
||||
reg = <0x1400 0x60>;
|
||||
interrupts = <17>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
/* Devices attached to the device controller */
|
||||
devicebus@045c {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "marvell,mv64306-devctrl";
|
||||
reg = <0x45C 0x88>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
ranges = <0 0 0xd8100000 0x10000
|
||||
2 0 0xd8110000 0x10000
|
||||
4 0 0xf8000000 0x8000000>;
|
||||
fpga@0,0 {
|
||||
compatible = "sbs,fpga-c2k";
|
||||
reg = <0 0 0x10000>;
|
||||
};
|
||||
fpga_usart@2,0 {
|
||||
compatible = "sbs,fpga_usart-c2k";
|
||||
reg = <2 0 0x10000>;
|
||||
};
|
||||
nor_flash@4,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <4 0 0x8000000>; /* 128MB */
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "boot";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "kernel";
|
||||
reg = <0x00080000 0x00400000>;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "initrd";
|
||||
reg = <0x00480000 0x00B80000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "rootfs";
|
||||
reg = <0x01000000 0x06800000>;
|
||||
};
|
||||
partition@7800000 {
|
||||
label = "recovery";
|
||||
reg = <0x07800000 0x00800000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
chosen {
|
||||
linux,stdout-path = &MPSC0;
|
||||
};
|
||||
};
|
||||
557
arch/powerpc/boot/dts/canyonlands.dts
Normal file
557
arch/powerpc/boot/dts/canyonlands.dts
Normal file
|
|
@ -0,0 +1,557 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Canyonlands (460EX)
|
||||
*
|
||||
* Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,canyonlands";
|
||||
compatible = "amcc,canyonlands";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460EX";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-460ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460ex";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460ex";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
CPM0: cpm {
|
||||
compatible = "ibm,cpm";
|
||||
dcr-access-method = "native";
|
||||
dcr-reg = <0x160 0x003>;
|
||||
unused-units = <0x00000100>;
|
||||
idle-doze = <0x02000000>;
|
||||
standby = <0xfeff791d>;
|
||||
};
|
||||
|
||||
L2C0: l2c {
|
||||
compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
|
||||
dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
|
||||
0x030 0x008>; /* L2 cache DCR's */
|
||||
cache-line-size = <32>; /* 32 bytes */
|
||||
cache-size = <262144>; /* L2, 256K */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <11 1>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-460ex", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
CRYPTO: crypto@180000 {
|
||||
compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
|
||||
reg = <4 0x00180000 0x80400>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1d 0x4>;
|
||||
};
|
||||
|
||||
HWRNG: hwrng@110000 {
|
||||
compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
|
||||
reg = <4 0x00110000 0x50>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <16>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x3 0x4
|
||||
/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4>;
|
||||
};
|
||||
|
||||
USB0: ehci@bffd0400 {
|
||||
compatible = "ibm,usb-ehci-460ex", "usb-ehci";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x1d 4>;
|
||||
reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
|
||||
};
|
||||
|
||||
USB1: usb@bffd0000 {
|
||||
compatible = "ohci-le";
|
||||
reg = <4 0xbffd0000 0x60>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x1e 4>;
|
||||
};
|
||||
|
||||
USBOTG0: usbotg@bff80000 {
|
||||
compatible = "amcc,dwc-otg";
|
||||
reg = <0x4 0xbff80000 0x10000>;
|
||||
interrupt-parent = <&USBOTG0>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0x0 0x1 0x2>;
|
||||
interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
|
||||
/* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
|
||||
/* DMA */ 0x2 &UIC0 0xc 0x4>;
|
||||
};
|
||||
|
||||
SATA0: sata@bffd1000 {
|
||||
compatible = "amcc,sata-460ex";
|
||||
reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
interrupts = <0x0 0x4 /* SATA */
|
||||
0x5 0x4>; /* AHBDMA */
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460ex", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0x00000000 0x00000000 0x04000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpld@2,0 {
|
||||
compatible = "amcc,ppc460ex-bcsr";
|
||||
reg = <2 0x0 0x9>;
|
||||
};
|
||||
|
||||
ndfc@3,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
reg = <0x00000003 0x00000000 0x00002000>;
|
||||
ccr = <0x00001000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "user";
|
||||
reg = <0x00000000 0x03f00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0x19 0x8>;
|
||||
};
|
||||
sttm@48 {
|
||||
compatible = "ad,ad7414";
|
||||
reg = <0x48>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x14 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic-460ex", "ibm,iic";
|
||||
reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@ef600b00 {
|
||||
compatible = "ibm,ppc4xx-gpio";
|
||||
reg = <0xef600b00 0x00000048>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
compatible = "ibm,zmii-460ex", "ibm,zmii";
|
||||
reg = <0xef600d00 0x0000000c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii-460ex", "ibm,rgmii";
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef601450 {
|
||||
compatible = "ibm,tah-460ex", "ibm,tah";
|
||||
reg = <0xef601450 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600e00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460ex", "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
|
||||
reg = <0xef600f00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
|
||||
PCIX0: pci@c0ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
|
||||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
||||
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 0 to 0x3f */
|
||||
bus-range = <0x0 0x3f>;
|
||||
|
||||
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
||||
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08010000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 40 to 0x7f */
|
||||
bus-range = <0x40 0x7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x08011000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 80 to 0xbf */
|
||||
bus-range = <0x80 0xbf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
MSI: ppc4xx-msi@C10000000 {
|
||||
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
|
||||
reg = < 0xC 0x10000000 0x100>;
|
||||
sdr-base = <0x36C>;
|
||||
msi-data = <0x00000000>;
|
||||
msi-mask = <0x44440000>;
|
||||
interrupt-count = <3>;
|
||||
interrupts = <0 1 2 3>;
|
||||
interrupt-parent = <&UIC3>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <0 &UIC3 0x18 1
|
||||
1 &UIC3 0x19 1
|
||||
2 &UIC3 0x1A 1
|
||||
3 &UIC3 0x1B 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
236
arch/powerpc/boot/dts/charon.dts
Normal file
236
arch/powerpc/boot/dts/charon.dts
Normal file
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* charon board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* Copyright (C) 2010 DENX Software Engineering GmbH
|
||||
* Heiko Schocher <hs@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "anon,charon";
|
||||
compatible = "anon,charon";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>; // 128MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200-immr";
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200-cdm";
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200-pic";
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 17 0>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 18 0>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200-xlb";
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
};
|
||||
|
||||
serial@2400 { // PSC3
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <2 3 0>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
fixed-link = <1 1 100 0 0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
};
|
||||
|
||||
|
||||
i2c@3d40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
|
||||
dtt@28 {
|
||||
compatible = "national,lm80";
|
||||
reg = <0x28>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus {
|
||||
compatible = "fsl,mpc5200-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = < 0 0 0xfc000000 0x02000000
|
||||
1 0 0xe0000000 0x04000000 // CS1 range, SM501
|
||||
3 0 0xe8000000 0x00080000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
};
|
||||
|
||||
display@1,0 {
|
||||
compatible = "smi,sm501";
|
||||
reg = <1 0x00000000 0x00800000
|
||||
1 0x03e00000 0x00200000>;
|
||||
mode = "640x480-32@60";
|
||||
interrupts = <1 1 3>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
mram0@3,0 {
|
||||
compatible = "mtd-ram";
|
||||
reg = <3 0x00000 0x80000>;
|
||||
bank-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200-pci";
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 2 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 3 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
89
arch/powerpc/boot/dts/cm5200.dts
Normal file
89
arch/powerpc/boot/dts/cm5200.dts
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* CM5200 board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "mpc5200b.dtsi"
|
||||
|
||||
&gpt0 { fsl,has-wdt; };
|
||||
|
||||
/ {
|
||||
model = "schindler,cm5200";
|
||||
compatible = "schindler,cm5200";
|
||||
|
||||
soc5200@f0000000 {
|
||||
can@900 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can@980 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2000 { // PSC1
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2200 { // PSC2
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2400 { // PSC3
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2600 { // PSC4
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2800 { // PSC5
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2c00 { // PSC6
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
localbus {
|
||||
// 16-bit flash device at LocalPlus Bus CS0
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x2000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
242
arch/powerpc/boot/dts/currituck.dts
Normal file
242
arch/powerpc/boot/dts/currituck.dts
Normal file
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Device Tree Source for IBM Embedded PPC 476 Platform
|
||||
*
|
||||
* Copyright © 2011 Tony Breeds IBM Corporation
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x01f00000 0x00100000; // spin table
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "ibm,currituck";
|
||||
compatible = "ibm,currituck";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
serial0 = &UART0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <0>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "ok";
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,476";
|
||||
reg = <1>;
|
||||
clock-frequency = <1600000000>; // 1.6 GHz
|
||||
timebase-frequency = <100000000>; // 100Mhz
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
status = "disabled";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x01f00000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
|
||||
};
|
||||
|
||||
MPIC: interrupt-controller {
|
||||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
dcr-reg = <0xffc00000 0x00040000>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb6";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
clock-frequency = <200000000>; // 200Mhz
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-4xx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full
|
||||
* 32-bit range
|
||||
*/
|
||||
ranges = <0x00000000 0x00000200 0x00000000 0x80000000
|
||||
0x80000000 0x00000200 0x80000000 0x80000000>;
|
||||
clock-frequency = <100000000>;
|
||||
|
||||
UART0: serial@10000000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16750", "ns16550";
|
||||
reg = <0x10000000 0x00000008>;
|
||||
virtual-reg = <0xe1000000>;
|
||||
clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
|
||||
current-speed = <115200>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <34 2>;
|
||||
};
|
||||
|
||||
FPGA0: fpga@50000000 {
|
||||
compatible = "ibm,currituck-fpga";
|
||||
reg = <0x50000000 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@00000000 {
|
||||
compatible = "ibm,iic-currituck", "ibm,iic";
|
||||
reg = <0x0 0x00000014>;
|
||||
interrupt-parent = <&MPIC>;
|
||||
interrupts = <79 2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rtc@68 {
|
||||
compatible = "stm,m41t80", "m41st85";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@10100000000 { // 4xGBIF1
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x80 0x20>;
|
||||
|
||||
// pci_space < pci_addr > < cpu_addr > < size >
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0 to memsize filled in by zImage */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@30100000000 { // 4xGBIF0
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0x60 0x20>;
|
||||
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0 to memsize filled in by zImage */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@38100000000 { // 2xGBIF0
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
|
||||
0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
|
||||
dcr-reg = <0xA0 0x20>;
|
||||
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
|
||||
0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
|
||||
|
||||
/* Inbound starting at 0 to memsize filled in by zImage */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0x0 0xf>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
|
||||
0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
|
||||
0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
|
||||
0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &UART0;
|
||||
};
|
||||
};
|
||||
161
arch/powerpc/boot/dts/digsy_mtc.dts
Normal file
161
arch/powerpc/boot/dts/digsy_mtc.dts
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* Digsy MTC board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2009 Semihalf
|
||||
*
|
||||
* Based on the CM5200 by M. Balakowicz
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/include/ "mpc5200b.dtsi"
|
||||
|
||||
&gpt0 { gpio-controller; fsl,has-wdt; };
|
||||
&gpt1 { gpio-controller; };
|
||||
|
||||
/ {
|
||||
model = "intercontrol,digsy-mtc";
|
||||
compatible = "intercontrol,digsy-mtc";
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x02000000>; // 32MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
rtc@800 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
msp430@0 {
|
||||
compatible = "spidev";
|
||||
spi-max-frequency = <32000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
psc@2000 { // PSC1
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2200 { // PSC2
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2400 { // PSC3
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
psc@2600 { // PSC4
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2800 { // PSC5
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
};
|
||||
|
||||
psc@2c00 { // PSC6
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
eeprom@50 {
|
||||
compatible = "at,24c08";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@56 {
|
||||
compatible = "mc,rv3029c2";
|
||||
reg = <0x56>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 2 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 3 &mpc5200_pic 0 0 3
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus {
|
||||
ranges = <0 0 0xff000000 0x1000000
|
||||
4 0 0x60000000 0x0001000>;
|
||||
|
||||
// 16-bit flash device at LocalPlus Bus CS0
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x0 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00300000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "user";
|
||||
reg = <0x00500000 0x00a00000>;
|
||||
};
|
||||
partition@f00000 {
|
||||
label = "u-boot";
|
||||
reg = <0x00f00000 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
can@4,0 {
|
||||
compatible = "nxp,sja1000";
|
||||
reg = <4 0x000 0x80>;
|
||||
nxp,external-clock-frequency = <24000000>;
|
||||
interrupts = <1 2 3>; // Level-low
|
||||
};
|
||||
|
||||
can@4,100 {
|
||||
compatible = "nxp,sja1000";
|
||||
reg = <4 0x100 0x80>;
|
||||
nxp,external-clock-frequency = <24000000>;
|
||||
interrupts = <1 2 3>; // Level-low
|
||||
};
|
||||
|
||||
serial@4,200 {
|
||||
compatible = "nxp,sc28l92";
|
||||
reg = <4 0x200 0x10>;
|
||||
interrupts = <1 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
337
arch/powerpc/boot/dts/ebony.dts
Normal file
337
arch/powerpc/boot/dts/ebony.dts
Normal file
|
|
@ -0,0 +1,337 @@
|
|||
/*
|
||||
* Device Tree Source for IBM Ebony
|
||||
*
|
||||
* Copyright (c) 2006, 2007 IBM Corp.
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
|
||||
*
|
||||
* FIXME: Draft only!
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "ibm,ebony";
|
||||
compatible = "ibm,ebony";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GP";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
timebase-frequency = <0>; // Filled in by zImage
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>; /* 32 kB */
|
||||
d-cache-size = <32768>; /* 32 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440gp", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440gp", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
CPC0: cpc {
|
||||
compatible = "ibm,cpc-440gp";
|
||||
dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440gp", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-440gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
SRAM0: sram {
|
||||
compatible = "ibm,sram-440gp";
|
||||
dcr-reg = <0x020 0x008 0x00a 0x001>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
// FIXME: ???
|
||||
compatible = "ibm,dma-440gp";
|
||||
dcr-reg = <0x100 0x027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440gp", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <4>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0x0 0x1 0x2 0x3 0x4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
|
||||
/*RXEOB*/ 0x1 &UIC0 0xb 0x4
|
||||
/*SERR*/ 0x2 &UIC1 0x0 0x4
|
||||
/*TXDE*/ 0x3 &UIC1 0x1 0x4
|
||||
/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
|
||||
interrupt-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full 32-bit
|
||||
range */
|
||||
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
|
||||
0x80000000 0x00000001 0x80000000 0x80000000>;
|
||||
dcr-reg = <0x090 0x00b>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x7 0x4>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
// ranges property is supplied by zImage
|
||||
// based on firmware's configuration of the
|
||||
// EBC bridge
|
||||
interrupts = <0x5 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
small-flash@0,80000 {
|
||||
compatible = "jedec-flash";
|
||||
bank-width = <1>;
|
||||
reg = <0x00000000 0x00080000 0x00080000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "OpenBIOS";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
nvram@1,0 {
|
||||
/* NVRAM & RTC */
|
||||
compatible = "ds1743-nvram";
|
||||
#bytes = <0x2000>;
|
||||
reg = <0x00000001 0x00000000 0x00002000>;
|
||||
};
|
||||
|
||||
large-flash@2,0 {
|
||||
compatible = "jedec-flash";
|
||||
bank-width = <1>;
|
||||
reg = <0x00000002 0x00000000 0x00400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "fs";
|
||||
reg = <0x00000000 0x00380000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "firmware";
|
||||
reg = <0x00380000 0x00080000>;
|
||||
};
|
||||
};
|
||||
|
||||
ir@3,0 {
|
||||
reg = <0x00000003 0x00000000 0x00000010>;
|
||||
};
|
||||
|
||||
fpga@7,0 {
|
||||
compatible = "Ebony-FPGA";
|
||||
reg = <0x00000007 0x00000000 0x00000010>;
|
||||
virtual-reg = <0xe8300000>;
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@40000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x40000200 0x00000008>;
|
||||
virtual-reg = <0xe0000200>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@40000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x40000300 0x00000008>;
|
||||
virtual-reg = <0xe0000300>;
|
||||
clock-frequency = <11059200>;
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@40000400 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0x40000400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
IIC1: i2c@40000500 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <0x40000500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@40000700 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,gpio-440gp";
|
||||
reg = <0x40000700 0x00000020>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@40000780 {
|
||||
compatible = "ibm,zmii-440gp", "ibm,zmii";
|
||||
reg = <0x40000780 0x0000000c>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@40000800 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1c 0x4 0x1d 0x4>;
|
||||
reg = <0x40000800 0x00000070>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0 1>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
EMAC1: ethernet@40000900 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>;
|
||||
reg = <0x40000900 0x00000070>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2 3>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
||||
|
||||
GPT0: gpt@40000a00 {
|
||||
/* FIXME */
|
||||
reg = <0x40000a00 0x000000d4>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
PCIX0: pci@20ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
|
||||
primary;
|
||||
reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
|
||||
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
||||
0x00000002 0x0ed00000 0x00000004 /* Special cycles */
|
||||
0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
|
||||
0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* Ebony has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
|
||||
|
||||
/* IDSEL 2 */
|
||||
0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
|
||||
|
||||
/* IDSEL 3 */
|
||||
0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
|
||||
|
||||
/* IDSEL 4 */
|
||||
0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@40000200";
|
||||
};
|
||||
};
|
||||
427
arch/powerpc/boot/dts/eiger.dts
Normal file
427
arch/powerpc/boot/dts/eiger.dts
Normal file
|
|
@ -0,0 +1,427 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC (AppliedMicro) Eiger(460SX)
|
||||
*
|
||||
* Copyright 2009 AMCC (AppliedMicro) <ttnguyen@amcc.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,eiger";
|
||||
compatible = "amcc,eiger";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
ethernet2 = &EMAC2;
|
||||
ethernet3 = &EMAC3;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,460SX";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-460sx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-460sx";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-460sx";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-460sx", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-460sx", "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-460sx", "ibm,mcmal2";
|
||||
dcr-reg = <0x180 0x62>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <32>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = < /*TXEOB*/ 0x6 0x4
|
||||
/*RXEOB*/ 0x7 0x4
|
||||
/*SERR*/ 0x1 0x4
|
||||
/*TXDE*/ 0x2 0x4
|
||||
/*RXDE*/ 0x3 0x4
|
||||
/*COAL TX0*/ 0x18 0x2
|
||||
/*COAL TX1*/ 0x19 0x2
|
||||
/*COAL TX2*/ 0x1a 0x2
|
||||
/*COAL TX3*/ 0x1b 0x2
|
||||
/*COAL RX0*/ 0x1c 0x2
|
||||
/*COAL RX1*/ 0x1d 0x2
|
||||
/*COAL RX2*/ 0x1e 0x2
|
||||
/*COAL RX3*/ 0x1f 0x2>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-460sx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-460sx", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <0x6 0x4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
/* reg property is supplied in by U-Boot */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x001e0000>;
|
||||
};
|
||||
partition@1e0000 {
|
||||
label = "dtb";
|
||||
reg = <0x001e0000 0x00020000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ramdisk";
|
||||
reg = <0x00200000 0x01400000>;
|
||||
};
|
||||
partition@1600000 {
|
||||
label = "jffs2";
|
||||
reg = <0x01600000 0x00400000>;
|
||||
};
|
||||
partition@1a00000 {
|
||||
label = "user";
|
||||
reg = <0x01a00000 0x02560000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <0x03f60000 0x00040000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x03fa0000 0x00060000>;
|
||||
};
|
||||
};
|
||||
|
||||
ndfc@1,0 {
|
||||
compatible = "ibm,ndfc";
|
||||
/* reg property is supplied by U-boot */
|
||||
ccr = <0x00003000>;
|
||||
bank-settings = <0x80002222>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "uboot";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "uboot-environment";
|
||||
reg = <0x00200000 0x00100000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "linux";
|
||||
reg = <0x00300000 0x00300000>;
|
||||
};
|
||||
partition@600000 {
|
||||
label = "root-file-system";
|
||||
reg = <0x00600000 0x01900000>;
|
||||
};
|
||||
partition@1f00000 {
|
||||
label = "device-tree";
|
||||
reg = <0x01f00000 0x00020000>;
|
||||
};
|
||||
partition@1f20000 {
|
||||
label = "data";
|
||||
reg = <0x01f20000 0x060E0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600200 0x00000008>;
|
||||
virtual-reg = <0xef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-460sx", "ibm,iic";
|
||||
reg = <0xef600400 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
index = <0>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-460sx", "ibm,iic";
|
||||
reg = <0xef600500 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
index = <1>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef600900 {
|
||||
compatible = "ibm,rgmii-460sx", "ibm,rgmii";
|
||||
reg = <0xef600900 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
RGMII1: emac-rgmii@ef600920 {
|
||||
compatible = "ibm,rgmii-460sx", "ibm,rgmii";
|
||||
reg = <0xef600920 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef600e50 {
|
||||
compatible = "ibm,tah-460sx", "ibm,tah";
|
||||
reg = <0xef600e50 0x00000030>;
|
||||
};
|
||||
|
||||
TAH1: emac-tah@ef600f50 {
|
||||
compatible = "ibm,tah-460sx", "ibm,tah";
|
||||
reg = <0xef600f50 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600a00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600a00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600b00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600b00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <8>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
tah-device = <&TAH1>;
|
||||
tah-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
|
||||
EMAC2: ethernet@ef600c00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC2>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x15 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600c00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <16>;
|
||||
cell-index = <2>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII1>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
|
||||
EMAC3: ethernet@ef600d00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-460sx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC3>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC0 0x16 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x1d 0x4>;
|
||||
reg = <0xef600d00 0x00000070>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <3>;
|
||||
mal-rx-channel = <24>;
|
||||
cell-index = <3>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
rx-fifo-size-gige = <16384>;
|
||||
tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII1>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
mdio-device = <&EMAC0>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600200";
|
||||
};
|
||||
|
||||
};
|
||||
230
arch/powerpc/boot/dts/ep405.dts
Normal file
230
arch/powerpc/boot/dts/ep405.dts
Normal file
|
|
@ -0,0 +1,230 @@
|
|||
/*
|
||||
* Device Tree Source for EP405
|
||||
*
|
||||
* Copyright 2007 IBM Corp.
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "ep405";
|
||||
compatible = "ep405";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405GP";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <200000000>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>;
|
||||
d-cache-size = <16384>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405gp";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL: mcmal {
|
||||
compatible = "ibm,mcmal-405gp", "ibm,mcmal";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0xb 0x4 /* TXEOB */
|
||||
0xc 0x4 /* RXEOB */
|
||||
0xa 0x4 /* SERR */
|
||||
0xd 0x4 /* TXDE */
|
||||
0xe 0x4 /* RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xef600000 0xef600000 0x00a00000>;
|
||||
dcr-reg = <0x0a0 0x005>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x0 0x4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0xef600400 0x00000008>;
|
||||
virtual-reg = <0xef600400>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <9600>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405gp", "ibm,iic";
|
||||
reg = <0xef600500 0x00000011>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
GPIO: gpio@ef600700 {
|
||||
compatible = "ibm,gpio-405gp";
|
||||
reg = <0xef600700 0x00000020>;
|
||||
};
|
||||
|
||||
EMAC: ethernet@ef600800 {
|
||||
linux,network-index = <0x0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
0xf 0x4 /* Ethernet */
|
||||
0x9 0x4 /* Ethernet Wake Up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by zImage */
|
||||
reg = <0xef600800 0x00000070>;
|
||||
mal-device = <&MAL>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <1500>;
|
||||
rx-fifo-size = <4096>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <0x00000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405gp", "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
||||
/* The ranges property is supplied by the bootwrapper
|
||||
* and is based on the firmware's configuration of the
|
||||
* EBC bridge
|
||||
*/
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
/* NVRAM and RTC */
|
||||
nvrtc@4,200000 {
|
||||
compatible = "ds1742";
|
||||
reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */
|
||||
};
|
||||
|
||||
/* "BCSR" CPLD contains a PCI irq controller */
|
||||
bcsr@4,0 {
|
||||
compatible = "ep405-bcsr";
|
||||
reg = <0x00000004 0x00000000 0x00000010>;
|
||||
interrupt-controller;
|
||||
/* Routing table */
|
||||
irq-routing = [ 00 /* SYSERR */
|
||||
01 /* STTM */
|
||||
01 /* RTC */
|
||||
01 /* FENET */
|
||||
02 /* NB PCIIRQ mux ? */
|
||||
03 /* SB Winbond 8259 ? */
|
||||
04 /* Serial Ring */
|
||||
05 /* USB (ep405pc) */
|
||||
06 /* XIRQ 0 */
|
||||
06 /* XIRQ 1 */
|
||||
06 /* XIRQ 2 */
|
||||
06 /* XIRQ 3 */
|
||||
06 /* XIRQ 4 */
|
||||
06 /* XIRQ 5 */
|
||||
06 /* XIRQ 6 */
|
||||
07]; /* Reserved */
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0xeec00000 0x00000008 /* Config space access */
|
||||
0xeed80000 0x00000004 /* IACK */
|
||||
0xeed80000 0x00000004 /* Special cycle */
|
||||
0xef480000 0x00000040>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
|
||||
0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* That's all I know about IRQs on that thing ... */
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
|
||||
interrupt-map = <
|
||||
/* USB */
|
||||
0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
203
arch/powerpc/boot/dts/ep8248e.dts
Normal file
203
arch/powerpc/boot/dts/ep8248e.dts
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Device Tree for the Embedded Planet EP8248E board running PlanetCore.
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "EP8248E";
|
||||
compatible = "fsl,ep8248e";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
planetcore-SMC1 = &smc1;
|
||||
planetcore-SCC1 = &scc1;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
serial0 = &smc1;
|
||||
serial1 = &scc1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8248@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@f0010100 {
|
||||
compatible = "fsl,mpc8248-localbus",
|
||||
"fsl,pq2-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf0010100 0x40>;
|
||||
|
||||
ranges = <0 0 0xfc000000 0x04000000
|
||||
1 0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,3800000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x3800000 0x800000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
};
|
||||
|
||||
bcsr@1,0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <1 0 0x10>;
|
||||
compatible = "fsl,ep8248e-bcsr";
|
||||
ranges;
|
||||
|
||||
mdio {
|
||||
compatible = "fsl,ep8248e-mdio-bitbang";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1 8 1>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>;
|
||||
};
|
||||
|
||||
soc@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8248-immr", "fsl,pq2-soc", "simple-bus";
|
||||
ranges = <0x00000000 0xf0000000 0x00053000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary -- will go away once kernel uses ranges for get_immrbase().
|
||||
reg = <0xf0000000 0x00053000>;
|
||||
|
||||
cpm@119c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,mpc8248-cpm", "fsl,cpm2",
|
||||
"simple-bus";
|
||||
reg = <0x119c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x2000 0x9800 0x800>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@119f0 {
|
||||
compatible = "fsl,mpc8248-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x119f0 0x10 0x115f0 0x10>;
|
||||
};
|
||||
|
||||
/* Monitor port/SMC1 */
|
||||
smc1: serial@11a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8248-smc-uart",
|
||||
"fsl,cpm2-smc-uart";
|
||||
reg = <0x11a80 0x20 0x87fc 2>;
|
||||
interrupts = <4 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <7>;
|
||||
fsl,cpm-command = <0x1d000000>;
|
||||
linux,planetcore-label = "SMC1";
|
||||
};
|
||||
|
||||
/* "Serial" port/SCC1 */
|
||||
scc1: serial@11a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8248-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x11a00 0x20 0x8000 0x100>;
|
||||
interrupts = <40 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x00800000>;
|
||||
linux,planetcore-label = "SCC1";
|
||||
};
|
||||
|
||||
eth0: ethernet@11300 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8248-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x11300 0x20 0x8400 0x100 0x11390 1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
fsl,cpm-command = <0x12000300>;
|
||||
};
|
||||
|
||||
eth1: ethernet@11320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8248-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x11320 0x20 0x8500 0x100 0x113b0 1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <33 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
fsl,cpm-command = <0x16200300>;
|
||||
};
|
||||
|
||||
usb@11b60 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8248-usb",
|
||||
"fsl,cpm2-usb";
|
||||
reg = <0x11b60 0x18 0x8b00 0x100>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupts = <11 8>;
|
||||
fsl,cpm-command = <0x2e600000>;
|
||||
};
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@10c00 {
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0x10c00 0x80>;
|
||||
compatible = "fsl,mpc8248-pic", "fsl,pq2-pic";
|
||||
};
|
||||
};
|
||||
};
|
||||
213
arch/powerpc/boot/dts/ep88xc.dts
Normal file
213
arch/powerpc/boot/dts/ep88xc.dts
Normal file
|
|
@ -0,0 +1,213 @@
|
|||
/*
|
||||
* EP88xC Device Tree Source
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007,2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "EP88xC";
|
||||
compatible = "fsl,ep88xc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,885@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
|
||||
localbus@fa200100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xfa200100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0x0 0x0 0xfc000000 0x4000000
|
||||
0x3 0x0 0xfa000000 0x1000000
|
||||
>;
|
||||
|
||||
flash@0,2000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x2000000 0x2000000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
};
|
||||
|
||||
board-control@3,400000 {
|
||||
reg = <0x3 0x400000 0x10>;
|
||||
compatible = "fsl,ep88xc-bcsr";
|
||||
};
|
||||
};
|
||||
|
||||
soc@fa200000 {
|
||||
compatible = "fsl,mpc885", "fsl,pq1-soc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xfa200000 0x4000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
// Temporary -- will go away once kernel uses ranges for get_immrbase().
|
||||
reg = <0xfa200000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc885-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc885-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x24>;
|
||||
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
pcmcia@80 {
|
||||
#address-cells = <3>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
compatible = "fsl,pq-pcmcia";
|
||||
device_type = "pcmcia";
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupts = <13 1>;
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
|
||||
command-proc = <0x9c0>;
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0x0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc885-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc885-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
// MON-1
|
||||
serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc885-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x90>;
|
||||
linux,planetcore-label = "SMC1";
|
||||
};
|
||||
|
||||
// SER-1
|
||||
serial@a20 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc885-scc-uart",
|
||||
"fsl,cpm1-scc-uart";
|
||||
reg = <0xa20 0x20 0x3d00 0x80>;
|
||||
interrupts = <29>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <2>;
|
||||
fsl,cpm-command = <0x40>;
|
||||
linux,planetcore-label = "SCC2";
|
||||
};
|
||||
|
||||
usb@a00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc885-usb",
|
||||
"fsl,cpm1-usb";
|
||||
reg = <0xa00 0x18 0x1c00 0x80>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
interrupts = <30>;
|
||||
fsl,cpm-command = <0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
130
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
Normal file
130
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/include/ "b4si-post.dtsi"
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4420-l3-cache-controller", "cache";
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4420-l2-cache-controller";
|
||||
};
|
||||
};
|
||||
79
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
Normal file
79
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4420";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
174
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
Normal file
174
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* B4860 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "b4si-post.dtsi"
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 20>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@110000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x110000 0x1000 0x111000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@118000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x118000 0x1000 0x119000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 9>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4860-l3-cache-controller", "cache";
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-2.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-2.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-2.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
|
||||
<&pll1 0>, <&pll1 1>, <&pll1 2>;
|
||||
clock-names = "pll0", "pll0-div2", "pll0-div4",
|
||||
"pll1", "pll1-div2", "pll1-div4";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4860-l2-cache-controller";
|
||||
};
|
||||
};
|
||||
93
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
Normal file
93
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* B4860 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4860";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
269
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
Normal file
269
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <20 2 0 0>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
interrupts = <20 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0
|
||||
94 2 0 0
|
||||
95 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
reg = <0x1000 0x1000 0x1002000 0x10000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0x1A000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x30000 0x1000 0x1022000 0x10000>;
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x31000 0x1000 0x1042000 0x10000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@100000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x100000 0x1000 0x101000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 2>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 4>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 0>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
fsl,portid-mapping = <0x8000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 1>;
|
||||
|
||||
|
||||
/* PCIe, DMA, SRIO */
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <8 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* AXI2, Maple */
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* Q/BMan */
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* AXI1, FMAN */
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic4.3.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4-device-config";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "elo3-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "elo3-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qonverge-usb2-dr-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
sdhci,auto-cmd12;
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-sec5.3-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4-l2-cache-controller";
|
||||
reg = <0xc20000 0x1000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
193
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
Normal file
193
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* BSC9131 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <16 2 0 0 20 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,bsc9131-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,bsc9131-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,bsc9131-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
i2c@3000 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
i2c@3100 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
serial0: serial@4500 {
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
interrupts = <18 2 0 0 >;
|
||||
};
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
interrupts = <22 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
gpio-controller@f000 {
|
||||
interrupts = <19 0x2 0 0>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,bsc9131-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
|
||||
dma@21300 {
|
||||
|
||||
dma-channel@0 {
|
||||
interrupts = <62 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@80 {
|
||||
interrupts = <63 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@100 {
|
||||
interrupts = <64 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@180 {
|
||||
interrupts = <65 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
|
||||
interrupts = <40 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
sdhci,auto-cmd12;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec4.4-0.dtsi"
|
||||
crypto@30000 {
|
||||
interrupts = <57 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
interrupts = <58 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
interrupts = <59 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
interrupts = <60 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
interrupts = <61 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
|
||||
timer@41100 {
|
||||
compatible = "fsl,mpic-v1.2-msgr", "fsl,mpic-msg";
|
||||
reg = <0x41400 0x200>;
|
||||
interrupts = <
|
||||
0xb0 2
|
||||
0xb1 2
|
||||
0xb2 2
|
||||
0xb3 2>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: ethernet@b0000 {
|
||||
queue-group@b0000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: ethernet@b1000 {
|
||||
queue-group@b1000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,bsc9131-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
62
arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
Normal file
62
arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* BSC9131 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,BSC9131";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,BSC9131@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "fsl,e500v2";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
185
arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
Normal file
185
arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* BSC9132 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
/* FIXME: Test whether interrupts are split */
|
||||
interrupts = <16 2 0 0 20 2 0 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,bsc9132-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,bsc9132-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,bsc9132-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
i2c@3000 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
i2c@3100 {
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
serial0: serial@4500 {
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
interrupts = <18 2 0 0 >;
|
||||
};
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
interrupts = <22 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
gpio-controller@f000 {
|
||||
interrupts = <19 0x2 0 0>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,bsc9132-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 1 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
|
||||
dma@21300 {
|
||||
|
||||
dma-channel@0 {
|
||||
interrupts = <62 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@80 {
|
||||
interrupts = <63 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@100 {
|
||||
interrupts = <64 2 0 0>;
|
||||
};
|
||||
|
||||
dma-channel@180 {
|
||||
interrupts = <65 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
|
||||
interrupts = <40 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
fsl,sdhci-auto-cmd12;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec4.4-0.dtsi"
|
||||
crypto@30000 {
|
||||
interrupts = <57 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
interrupts = <58 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
interrupts = <59 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
interrupts = <60 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
interrupts = <61 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: ethernet@b0000 {
|
||||
queue-group@b0000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: ethernet@b1000 {
|
||||
queue-group@b1000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,bsc9132-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/bsc9132si-pre.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* BSC9132 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2014 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500v2@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
cpu1: PowerPC,e500v2@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
193
arch/powerpc/boot/dts/fsl/c293si-post.dtsi
Normal file
193
arch/powerpc/boot/dts/fsl/c293si-post.dtsi
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* C293 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,c293-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,c293-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,c293-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2,512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,c293-esdhc", "fsl,esdhc";
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
crypto@80000 {
|
||||
/include/ "qoriq-sec6.0-0.dtsi"
|
||||
};
|
||||
|
||||
crypto@80000 {
|
||||
reg = <0x80000 0x20000>;
|
||||
ranges = <0x0 0x80000 0x20000>;
|
||||
|
||||
jr@1000{
|
||||
interrupts = <45 2 0 0>;
|
||||
};
|
||||
jr@2000{
|
||||
interrupts = <57 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@a0000 {
|
||||
/include/ "qoriq-sec6.0-0.dtsi"
|
||||
};
|
||||
|
||||
crypto@a0000 {
|
||||
reg = <0xa0000 0x20000>;
|
||||
ranges = <0x0 0xa0000 0x20000>;
|
||||
|
||||
jr@1000{
|
||||
interrupts = <49 2 0 0>;
|
||||
};
|
||||
jr@2000{
|
||||
interrupts = <50 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@c0000 {
|
||||
/include/ "qoriq-sec6.0-0.dtsi"
|
||||
};
|
||||
|
||||
crypto@c0000 {
|
||||
reg = <0xc0000 0x20000>;
|
||||
ranges = <0x0 0xc0000 0x20000>;
|
||||
|
||||
jr@1000{
|
||||
interrupts = <55 2 0 0>;
|
||||
};
|
||||
jr@2000{
|
||||
interrupts = <56 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: ethernet@b0000 {
|
||||
queue-group@b0000 {
|
||||
reg = <0x10000 0x1000>;
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: ethernet@b1000 {
|
||||
queue-group@b1000 {
|
||||
reg = <0x11000 0x1000>;
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,c293-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
63
arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
Normal file
63
arch/powerpc/boot/dts/fsl/c293si-pre.dtsi
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* C293 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,C293";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,e500v2@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
59
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
Normal file
59
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* e500mc Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.06";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-ds; // Decorated Storage
|
||||
power-isa-e.ed; // Embedded.Enhanced Debug
|
||||
power-isa-e.pd; // Embedded.External PID
|
||||
power-isa-e.hv; // Embedded.Hypervisor
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-e.pc; // Embedded.Processor Control
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-exp; // External Proxy
|
||||
power-isa-fp; // Floating Point
|
||||
power-isa-fp.r; // Floating Point.Record
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
52
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
Normal file
52
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* e500v2 Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.03";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-sp; // Signal Processing Engine
|
||||
power-isa-sp.fd; // SPE.Embedded Float Scalar Double
|
||||
power-isa-sp.fs; // SPE.Embedded Float Scalar Single
|
||||
power-isa-sp.fv; // SPE.Embedded Float Vector
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
60
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
Normal file
60
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* e5500 Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.06";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-ds; // Decorated Storage
|
||||
power-isa-e.ed; // Embedded.Enhanced Debug
|
||||
power-isa-e.pd; // Embedded.External PID
|
||||
power-isa-e.hv; // Embedded.Hypervisor
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-e.pc; // Embedded.Processor Control
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-exp; // External Proxy
|
||||
power-isa-fp; // Floating Point
|
||||
power-isa-fp.r; // Floating Point.Record
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
power-isa-64; // 64-bit
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
65
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
Normal file
65
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* e6500 Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.06";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-ds; // Decorated Storage
|
||||
power-isa-e.ed; // Embedded.Enhanced Debug
|
||||
power-isa-e.pd; // Embedded.External PID
|
||||
power-isa-e.hv; // Embedded.Hypervisor
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-e.pc; // Embedded.Processor Control
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-exp; // External Proxy
|
||||
power-isa-fp; // Floating Point
|
||||
power-isa-fp.r; // Floating Point.Record
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
power-isa-64; // 64-bit
|
||||
power-isa-e.pt; // Embedded.Page Table
|
||||
power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
|
||||
power-isa-e.em; // Embedded Multi-Threading
|
||||
power-isa-v; // Vector (AltiVec)
|
||||
fsl,eref-er; // Enhanced Reservations (Load and Reserve and Store Cond.)
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
82
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
Normal file
82
arch/powerpc/boot/dts/fsl/elo3-dma-0.dtsi
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma0: dma@100300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elo3-dma";
|
||||
reg = <0x100300 0x4>,
|
||||
<0x100600 0x4>;
|
||||
ranges = <0x0 0x100100 0x500>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
interrupts = <28 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <29 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupts = <30 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
interrupts = <31 2 0 0>;
|
||||
};
|
||||
dma-channel@300 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x300 0x80>;
|
||||
interrupts = <76 2 0 0>;
|
||||
};
|
||||
dma-channel@380 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x380 0x80>;
|
||||
interrupts = <77 2 0 0>;
|
||||
};
|
||||
dma-channel@400 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <78 2 0 0>;
|
||||
};
|
||||
dma-channel@480 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x480 0x80>;
|
||||
interrupts = <79 2 0 0>;
|
||||
};
|
||||
};
|
||||
82
arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
Normal file
82
arch/powerpc/boot/dts/fsl/elo3-dma-1.dtsi
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma1: dma@101300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elo3-dma";
|
||||
reg = <0x101300 0x4>,
|
||||
<0x101600 0x4>;
|
||||
ranges = <0x0 0x101100 0x500>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
interrupts = <32 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <33 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupts = <34 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
interrupts = <35 2 0 0>;
|
||||
};
|
||||
dma-channel@300 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x300 0x80>;
|
||||
interrupts = <80 2 0 0>;
|
||||
};
|
||||
dma-channel@380 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x380 0x80>;
|
||||
interrupts = <81 2 0 0>;
|
||||
};
|
||||
dma-channel@400 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <82 2 0 0>;
|
||||
};
|
||||
dma-channel@480 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x480 0x80>;
|
||||
interrupts = <83 2 0 0>;
|
||||
};
|
||||
};
|
||||
82
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
Normal file
82
arch/powerpc/boot/dts/fsl/elo3-dma-2.dtsi
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma2: dma@102300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,elo3-dma";
|
||||
reg = <0x102300 0x4>,
|
||||
<0x102600 0x4>;
|
||||
ranges = <0x0 0x102100 0x500>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
interrupts = <464 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <465 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
interrupts = <466 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
interrupts = <467 2 0 0>;
|
||||
};
|
||||
dma-channel@300 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x300 0x80>;
|
||||
interrupts = <468 2 0 0>;
|
||||
};
|
||||
dma-channel@380 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x380 0x80>;
|
||||
interrupts = <469 2 0 0>;
|
||||
};
|
||||
dma-channel@400 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x400 0x80>;
|
||||
interrupts = <470 2 0 0>;
|
||||
};
|
||||
dma-channel@480 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x480 0x80>;
|
||||
interrupts = <471 2 0 0>;
|
||||
};
|
||||
};
|
||||
156
arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
Normal file
156
arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
/* T4240 Interlaken LAC Portal device tree stub with 24 portals.
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "fsl,interlaken-lac-portals";
|
||||
|
||||
lportal0: lac-portal@0 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
lportal1: lac-portal@1000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x1000 0x1000>;
|
||||
};
|
||||
|
||||
lportal2: lac-portal@2000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
|
||||
lportal3: lac-portal@3000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x3000 0x1000>;
|
||||
};
|
||||
|
||||
lportal4: lac-portal@4000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x4000 0x1000>;
|
||||
};
|
||||
|
||||
lportal5: lac-portal@5000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
|
||||
lportal6: lac-portal@6000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x6000 0x1000>;
|
||||
};
|
||||
|
||||
lportal7: lac-portal@7000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x7000 0x1000>;
|
||||
};
|
||||
|
||||
lportal8: lac-portal@8000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x8000 0x1000>;
|
||||
};
|
||||
|
||||
lportal9: lac-portal@9000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
|
||||
lportal10: lac-portal@A000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xA000 0x1000>;
|
||||
};
|
||||
|
||||
lportal11: lac-portal@B000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xB000 0x1000>;
|
||||
};
|
||||
|
||||
lportal12: lac-portal@C000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xC000 0x1000>;
|
||||
};
|
||||
|
||||
lportal13: lac-portal@D000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xD000 0x1000>;
|
||||
};
|
||||
|
||||
lportal14: lac-portal@E000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xE000 0x1000>;
|
||||
};
|
||||
|
||||
lportal15: lac-portal@F000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0xF000 0x1000>;
|
||||
};
|
||||
|
||||
lportal16: lac-portal@10000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x10000 0x1000>;
|
||||
};
|
||||
|
||||
lportal17: lac-portal@11000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
|
||||
lportal18: lac-portal@1200 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
|
||||
lportal19: lac-portal@13000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
|
||||
lportal20: lac-portal@14000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x14000 0x1000>;
|
||||
};
|
||||
|
||||
lportal21: lac-portal@15000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x15000 0x1000>;
|
||||
};
|
||||
|
||||
lportal22: lac-portal@16000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x16000 0x1000>;
|
||||
};
|
||||
|
||||
lportal23: lac-portal@17000 {
|
||||
compatible = "fsl,interlaken-lac-portal-v1.0";
|
||||
reg = <0x17000 0x1000>;
|
||||
};
|
||||
45
arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
Normal file
45
arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* T4 Interlaken Look-aside Controller (LAC) device tree stub
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
lac: lac@229000 {
|
||||
compatible = "fsl,interlaken-lac";
|
||||
reg = <0x229000 0x1000>;
|
||||
interrupts = <16 2 1 18>;
|
||||
};
|
||||
|
||||
lac-hv@228000 {
|
||||
compatible = "fsl,interlaken-lac-hv";
|
||||
reg = <0x228000 0x1000>;
|
||||
fsl,non-hv-node = <&lac>;
|
||||
};
|
||||
252
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
Normal file
252
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
Normal file
|
|
@ -0,0 +1,252 @@
|
|||
/*
|
||||
* MPC8536 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <25 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xb000 */
|
||||
&pci3 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <27 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <27 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8536-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8536-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8536-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi@7000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
|
||||
/* mark compat w/8572 to get some erratum treatment */
|
||||
gpio-controller@f000 {
|
||||
compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <74 0x2 0 0>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
cell-index = <2>;
|
||||
interrupts = <41 0x2 0 0>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8536-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-timer-0.dtsi"
|
||||
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <28 0x2 0 0>;
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <46 0x2 0 0>;
|
||||
};
|
||||
|
||||
ptp_clock@24e00 {
|
||||
interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
|
||||
ethernet@26000 {
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
usb@2b000 {
|
||||
compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
|
||||
reg = <0x2b000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <60 0x2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
|
||||
};
|
||||
|
||||
/include/ "pq3-sec3.0-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8536-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* MPC8536 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8536";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8536@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
191
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
Normal file
191
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* MPC8544 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <25 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xb000 */
|
||||
&pci3 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <27 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <27 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8544-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8544-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8544-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8544-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
|
||||
ethernet@26000 {
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec2.1-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8544-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* MPC8544 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8544";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8544@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
159
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
Normal file
159
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* MPC8548 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <25 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <48 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8548-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
/include/ "pq3-etsec1-3.dtsi"
|
||||
|
||||
/include/ "pq3-sec2.1-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-rmu-0.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
67
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
Normal file
67
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* MPC8548 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8548";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
270
arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
Normal file
270
arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* MPC8568 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
sleep = <&pmc 0x08000000>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupts = <24 0x2 0 0>;
|
||||
bus-range = <0 0xff>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
sleep = <&pmc 0x80000000>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
sleep = <&pmc 0x20000000>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <48 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
sleep = <&pmc 0x00080000>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8568-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8568-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8568-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
i2c-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000004>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
|
||||
};
|
||||
|
||||
duart-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000002>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8568-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
dma@21300 {
|
||||
sleep = <&pmc 0x00000400>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
ethernet@24000 {
|
||||
sleep = <&pmc 0x00000080>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
ethernet@25000 {
|
||||
sleep = <&pmc 0x00000040>;
|
||||
};
|
||||
|
||||
par_io@e0100 {
|
||||
reg = <0xe0100 0x100>;
|
||||
device_type = "par_io";
|
||||
};
|
||||
|
||||
/include/ "pq3-sec2.1-0.dtsi"
|
||||
crypto@30000 {
|
||||
sleep = <&pmc 0x01000000>;
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-rmu-0.dtsi"
|
||||
rmu@d3000 {
|
||||
sleep = <&pmc 0x00040000>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
ranges = <0 0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
|
||||
pmc: power@70 {
|
||||
compatible = "fsl,mpc8568-pmc",
|
||||
"fsl,mpc8548-pmc";
|
||||
reg = <0x70 0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
sleep = <&pmc 0x00000800>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <396000000>;
|
||||
fsl,qe-num-riscs = <2>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
cell-index = <0>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3000 {
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x10000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
68
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
Normal file
68
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* MPC8568 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8568";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8568@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
sleep = <&pmc 0x00008000 // core
|
||||
&pmc 0x00004000>; // timebase
|
||||
};
|
||||
};
|
||||
};
|
||||
304
arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
Normal file
304
arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
Normal file
|
|
@ -0,0 +1,304 @@
|
|||
/*
|
||||
* MPC8569 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
sleep = <&pmc 0x08000000>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
sleep = <&pmc 0x20000000>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <48 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
sleep = <&pmc 0x00080000>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8569-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <10>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8569-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8569-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
i2c-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000004>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
|
||||
};
|
||||
|
||||
duart-sleep-nexus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
sleep = <&pmc 0x00000002>;
|
||||
ranges;
|
||||
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8569-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
sleep = <&pmc 0x00200000>;
|
||||
};
|
||||
|
||||
par_io@e0100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xe0100 0x100>;
|
||||
ranges = <0x0 0xe0100 0x100>;
|
||||
device_type = "par_io";
|
||||
};
|
||||
|
||||
/include/ "pq3-sec3.1-0.dtsi"
|
||||
crypto@30000 {
|
||||
sleep = <&pmc 0x01000000>;
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-rmu-0.dtsi"
|
||||
rmu@d3000 {
|
||||
sleep = <&pmc 0x00040000>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
ranges = <0 0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
|
||||
pmc: power@70 {
|
||||
compatible = "fsl,mpc8569-pmc",
|
||||
"fsl,mpc8548-pmc";
|
||||
reg = <0x70 0x20>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
sleep = <&pmc 0x00000800>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
fsl,qe-num-riscs = <4>;
|
||||
fsl,qe-num-snums = <46>;
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
timer@440 {
|
||||
compatible = "fsl,mpc8569-qe-gtm",
|
||||
"fsl,qe-gtm", "fsl,gtm";
|
||||
reg = <0x440 0x40>;
|
||||
interrupts = <12 13 14 15>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
cell-index = <0>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
usb@6c0 {
|
||||
compatible = "fsl,mpc8569-qe-usb",
|
||||
"fsl,mpc8323-qe-usb";
|
||||
reg = <0x6c0 0x40 0x8b00 0x100>;
|
||||
interrupts = <11>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3000 {
|
||||
cell-index = <2>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3200 {
|
||||
cell-index = <4>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3400 {
|
||||
cell-index = <6>;
|
||||
reg = <0x3400 0x200>;
|
||||
interrupts = <41>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@3600 {
|
||||
cell-index = <8>;
|
||||
reg = <0x3600 0x200>;
|
||||
interrupts = <43>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x20000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
67
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
Normal file
67
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* MPC8569 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8569";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8569@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
sleep = <&pmc 0x00008000 // core
|
||||
&pmc 0x00004000>; // timebase
|
||||
};
|
||||
};
|
||||
};
|
||||
196
arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
Normal file
196
arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
/*
|
||||
* MPC8572 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <24 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <24 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <25 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8572-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,mpc8572-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@6000 {
|
||||
compatible = "fsl,mpc8572-memory-controller";
|
||||
reg = <0x6000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
/include/ "pq3-dma-1.dtsi"
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
gpio-controller@f000 {
|
||||
compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,mpc8572-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x100000>; // L2,1M
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-timer-0.dtsi"
|
||||
|
||||
ptp_clock@24e00 {
|
||||
interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
/include/ "pq3-etsec1-3.dtsi"
|
||||
/include/ "pq3-sec3.0-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8572-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
73
arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
Normal file
73
arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* MPC8572 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,MPC8572";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8572@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,8572@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
202
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
Normal file
202
arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* P1010/P1014 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <16 2 0 0 19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1010-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1010-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1010-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <1>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
/include/ "pq3-sata2-0.dtsi"
|
||||
/include/ "pq3-sata2-1.dtsi"
|
||||
|
||||
can0: can@1c000 {
|
||||
compatible = "fsl,p1010-flexcan";
|
||||
reg = <0x1c000 0x1000>;
|
||||
interrupts = <48 0x2 0 0>;
|
||||
};
|
||||
|
||||
can1: can@1d000 {
|
||||
compatible = "fsl,p1010-flexcan";
|
||||
reg = <0x1d000 0x1000>;
|
||||
interrupts = <61 0x2 0 0>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1010-l2-cache-controller",
|
||||
"fsl,p1014-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,p1010-esdhc", "fsl,esdhc";
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec4.4-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: ethernet@b0000 {
|
||||
queue-group@b0000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: ethernet@b1000 {
|
||||
queue-group@b1000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-2.dtsi"
|
||||
enet2: ethernet@b2000 {
|
||||
queue-group@b2000 {
|
||||
fsl,rx-bit-map = <0xff>;
|
||||
fsl,tx-bit-map = <0xff>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,p1010-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
67
arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
Normal file
67
arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* P1010/P1014 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P1010";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
can0 = &can0;
|
||||
can1 = &can1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1010@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
185
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
Normal file
185
arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* P1020/P1011 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>,
|
||||
<16 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1020-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi@7000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
/include/ "pq3-usb2-dr-1.dtsi"
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,p1020-esdhc", "fsl,esdhc";
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
/include/ "pq3-sec3.3-0.dtsi"
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: enet0_grp2: ethernet@b0000 {
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: enet1_grp2: ethernet@b1000 {
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-2.dtsi"
|
||||
enet2: enet2_grp2: ethernet@b2000 {
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,p1020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-grp2-0.dtsi"
|
||||
/include/ "pq3-etsec2-grp2-1.dtsi"
|
||||
/include/ "pq3-etsec2-grp2-2.dtsi"
|
||||
71
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
Normal file
71
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* P1020/P1011 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P1020";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
247
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
Normal file
247
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
Normal file
|
|
@ -0,0 +1,247 @@
|
|||
/*
|
||||
* P1021/P1012 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>,
|
||||
<16 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1021-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1021-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1021-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi@7000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1021-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec3.3-0.dtsi"
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: enet0_grp2: ethernet@b0000 {
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: enet1_grp2: ethernet@b1000 {
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-2.dtsi"
|
||||
enet2: enet2_grp2: ethernet@b2000 {
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,p1021-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
&qe {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe";
|
||||
fsl,qe-num-riscs = <1>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
mdio@2120 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2120 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
};
|
||||
|
||||
ucc@2400 {
|
||||
cell-index = <5>;
|
||||
reg = <0x2400 0x200>;
|
||||
interrupts = <40>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2600 {
|
||||
cell-index = <7>;
|
||||
reg = <0x2600 0x200>;
|
||||
interrupts = <42>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x6000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-grp2-0.dtsi"
|
||||
/include/ "pq3-etsec2-grp2-1.dtsi"
|
||||
/include/ "pq3-etsec2-grp2-2.dtsi"
|
||||
71
arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
Normal file
71
arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* P1021/P1012 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P1021";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1021@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1021@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
247
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
Normal file
247
arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
Normal file
|
|
@ -0,0 +1,247 @@
|
|||
/*
|
||||
* P1022/P1013 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* The localbus on the P1022 is not a simple-bus because of the eLBC
|
||||
* pin muxing when the DIU is enabled.
|
||||
*/
|
||||
compatible = "fsl,p1022-elbc", "fsl,elbc";
|
||||
interrupts = <19 2 0 0>,
|
||||
<16 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xb000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1022-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1022-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1022-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi@7000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-1.dtsi"
|
||||
dma@c300 {
|
||||
dma00: dma-channel@0 {
|
||||
compatible = "fsl,ssi-dma-channel";
|
||||
};
|
||||
dma01: dma-channel@80 {
|
||||
compatible = "fsl,ssi-dma-channel";
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
|
||||
display@10000 {
|
||||
compatible = "fsl,diu", "fsl,p1022-diu";
|
||||
reg = <0x10000 1000>;
|
||||
interrupts = <64 2 0 0>;
|
||||
};
|
||||
|
||||
ssi@15000 {
|
||||
compatible = "fsl,mpc8610-ssi";
|
||||
cell-index = <0>;
|
||||
reg = <0x15000 0x100>;
|
||||
interrupts = <75 2 0 0>;
|
||||
fsl,playback-dma = <&dma00>;
|
||||
fsl,capture-dma = <&dma01>;
|
||||
fsl,fifo-depth = <15>;
|
||||
};
|
||||
|
||||
/include/ "pq3-sata2-0.dtsi"
|
||||
/include/ "pq3-sata2-1.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1022-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
/include/ "pq3-usb2-dr-1.dtsi"
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,p1022-esdhc", "fsl,esdhc";
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "pq3-sec3.3-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
/include/ "pq3-etsec2-0.dtsi"
|
||||
enet0: enet0_grp2: ethernet@b0000 {
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-1.dtsi"
|
||||
enet1: enet1_grp2: ethernet@b1000 {
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,p1022-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
power@e0070{
|
||||
compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
|
||||
reg = <0xe0070 0x20>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "pq3-etsec2-grp2-0.dtsi"
|
||||
/include/ "pq3-etsec2-grp2-1.dtsi"
|
||||
71
arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
Normal file
71
arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* P1022/P1013 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P1022";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1022@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1022@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
229
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
Normal file
229
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
Normal file
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* P1023/P1017 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>,
|
||||
<16 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0xb000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 0 0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p1023-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p1023-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p1023-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi@7000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p1023-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2,256K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000 0x10000>;
|
||||
ranges = <0 0x30000 0x10000>;
|
||||
interrupts = <58 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <45 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <45 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <57 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.2-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <57 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.2-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.2-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,p1023-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
79
arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
Normal file
79
arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* P1023/P1017 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P1023";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P1023@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P1023@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
201
arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
Normal file
201
arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
Normal file
|
|
@ -0,0 +1,201 @@
|
|||
/*
|
||||
* P2020/P2010 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <19 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0xa000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <26 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <26 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x9000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <25 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <25 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x8000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 255>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <24 2 0 0>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <24 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
|
||||
0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,p2020-immr", "simple-bus";
|
||||
bus-frequency = <0>; // Filled out by uboot.
|
||||
|
||||
ecm-law@0 {
|
||||
compatible = "fsl,ecm-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <12>;
|
||||
};
|
||||
|
||||
ecm@1000 {
|
||||
compatible = "fsl,p2020-ecm", "fsl,ecm";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <17 2 0 0>;
|
||||
};
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,p2020-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <18 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-i2c-0.dtsi"
|
||||
/include/ "pq3-i2c-1.dtsi"
|
||||
/include/ "pq3-duart-0.dtsi"
|
||||
/include/ "pq3-espi-0.dtsi"
|
||||
spi0: spi@7000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-1.dtsi"
|
||||
/include/ "pq3-gpio-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@20000 {
|
||||
compatible = "fsl,p2020-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2,512K
|
||||
interrupts = <16 2 0 0>;
|
||||
};
|
||||
|
||||
/include/ "pq3-dma-0.dtsi"
|
||||
/include/ "pq3-usb2-dr-0.dtsi"
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
|
||||
};
|
||||
/include/ "pq3-etsec1-0.dtsi"
|
||||
/include/ "pq3-etsec1-timer-0.dtsi"
|
||||
|
||||
ptp_clock@24e00 {
|
||||
interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
|
||||
};
|
||||
|
||||
|
||||
/include/ "pq3-etsec1-1.dtsi"
|
||||
/include/ "pq3-etsec1-2.dtsi"
|
||||
/include/ "pq3-esdhc-0.dtsi"
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,p2020-esdhc", "fsl,esdhc";
|
||||
};
|
||||
|
||||
/include/ "pq3-sec3.1-0.dtsi"
|
||||
/include/ "pq3-mpic.dtsi"
|
||||
/include/ "pq3-mpic-timer-B.dtsi"
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,p2020-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
72
arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
Normal file
72
arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* P2020/P2010 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500v2_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P2020";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,P2020@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
|
||||
PowerPC,P2020@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
454
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
Normal file
454
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
Normal file
|
|
@ -0,0 +1,454 @@
|
|||
/*
|
||||
* P2041/P2040 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 15>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x201000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 14>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x202000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 13>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 11>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,p2041-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@42000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x42000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@43000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x43000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 27>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
|
||||
ranges = <0 0x20000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
fsl,portid-mapping = <0x0f000000>;
|
||||
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x40 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux2";
|
||||
};
|
||||
|
||||
mux3: mux3@60 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x60 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux3";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p2041-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-gpio-0.dtsi"
|
||||
/include/ "qoriq-usb2-mph-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
phy_type = "utmi";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
port0;
|
||||
};
|
||||
|
||||
/include/ "qoriq-usb2-dr-0.dtsi"
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-0.dtsi"
|
||||
sata@220000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-1.dtsi"
|
||||
sata@221000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sec4.2-0.dtsi"
|
||||
crypto: crypto@300000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
};
|
||||
122
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
Normal file
122
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* P2041 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500mc_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P2041";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&mux1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
clocks = <&mux2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
clocks = <&mux3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
L2_3: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
481
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
Normal file
481
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
Normal file
|
|
@ -0,0 +1,481 @@
|
|||
/*
|
||||
* P3041 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 15>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x201000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 14>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x202000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 13>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x203000 */
|
||||
&pci3 {
|
||||
compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 12>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 12>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 43 1 0 0
|
||||
0000 0 0 2 &mpic 0 1 0 0
|
||||
0000 0 0 3 &mpic 4 1 0 0
|
||||
0000 0 0 4 &mpic 8 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 11>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@42000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x42000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@43000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x43000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 27>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
|
||||
ranges = <0 0x20000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
fsl,portid-mapping = <0x0f000000>;
|
||||
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x40 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux2";
|
||||
};
|
||||
|
||||
mux3: mux3@60 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x60 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux3";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p3041-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-gpio-0.dtsi"
|
||||
/include/ "qoriq-usb2-mph-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
|
||||
phy_type = "utmi";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
port0;
|
||||
};
|
||||
|
||||
/include/ "qoriq-usb2-dr-0.dtsi"
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-0.dtsi"
|
||||
sata@220000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-1.dtsi"
|
||||
sata@221000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sec4.2-0.dtsi"
|
||||
crypto: crypto@300000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
};
|
||||
123
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
Normal file
123
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
Normal file
|
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* P3041 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500mc_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P3041";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&mux1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
clocks = <&mux2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
clocks = <&mux3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
L2_3: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
537
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
Normal file
537
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
Normal file
|
|
@ -0,0 +1,537 @@
|
|||
/*
|
||||
* P4080/P4040 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 15>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x201000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 14>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x202000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 13>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 11>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,srio-rmu-handle = <&rmu>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@42000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x42000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@43000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x43000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@44000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu4>;
|
||||
reg = <0x44000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@45000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu5>;
|
||||
reg = <0x45000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@46000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu6>;
|
||||
reg = <0x46000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@47000 {
|
||||
compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu7>;
|
||||
reg = <0x47000 0x1000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 27
|
||||
16 2 1 26>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
|
||||
ranges = <0 0x20000 0x5000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
fsl,portid-mapping = <0x00f80000>;
|
||||
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu4: pamu@4000 {
|
||||
reg = <0x4000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-rmu-0.dtsi"
|
||||
rmu@d3000 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
pll2: pll2@840 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x840 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll2", "pll2-div2";
|
||||
};
|
||||
|
||||
pll3: pll3@860 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x860 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll3", "pll3-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x40 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux2";
|
||||
};
|
||||
|
||||
mux3: mux3@60 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x60 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux3";
|
||||
};
|
||||
|
||||
mux4: mux4@80 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x80 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
|
||||
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
|
||||
clock-output-names = "cmux4";
|
||||
};
|
||||
|
||||
mux5: mux5@a0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0xa0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
|
||||
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
|
||||
clock-output-names = "cmux5";
|
||||
};
|
||||
|
||||
mux6: mux6@c0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0xc0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
|
||||
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
|
||||
clock-output-names = "cmux6";
|
||||
};
|
||||
|
||||
mux7: mux7@e0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0xe0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
|
||||
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
|
||||
clock-output-names = "cmux7";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p4080-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
voltage-ranges = <3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-gpio-0.dtsi"
|
||||
/include/ "qoriq-usb2-mph-0.dtsi"
|
||||
usb@210000 {
|
||||
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
port0;
|
||||
};
|
||||
/include/ "qoriq-usb2-dr-0.dtsi"
|
||||
usb@211000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
|
||||
};
|
||||
/include/ "qoriq-sec4.0-0.dtsi"
|
||||
crypto: crypto@300000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
};
|
||||
162
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
Normal file
162
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* P4080/P4040 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e500mc_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P4080";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e500mc@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e500mc@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&mux1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,e500mc@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
clocks = <&mux2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,e500mc@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
clocks = <&mux3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
L2_3: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu4: PowerPC,e500mc@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4>;
|
||||
clocks = <&mux4>;
|
||||
next-level-cache = <&L2_4>;
|
||||
fsl,portid-mapping = <0x08000000>;
|
||||
L2_4: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu5: PowerPC,e500mc@5 {
|
||||
device_type = "cpu";
|
||||
reg = <5>;
|
||||
clocks = <&mux5>;
|
||||
next-level-cache = <&L2_5>;
|
||||
fsl,portid-mapping = <0x04000000>;
|
||||
L2_5: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu6: PowerPC,e500mc@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6>;
|
||||
clocks = <&mux6>;
|
||||
next-level-cache = <&L2_6>;
|
||||
fsl,portid-mapping = <0x02000000>;
|
||||
L2_6: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu7: PowerPC,e500mc@7 {
|
||||
device_type = "cpu";
|
||||
reg = <7>;
|
||||
clocks = <&mux7>;
|
||||
next-level-cache = <&L2_7>;
|
||||
fsl,portid-mapping = <0x01000000>;
|
||||
L2_7: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
472
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
Normal file
472
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
Normal file
|
|
@ -0,0 +1,472 @@
|
|||
/*
|
||||
* P5020/5010 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 15>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x201000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 14>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x202000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 13>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x203000 */
|
||||
&pci3 {
|
||||
compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 12>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x50c>; /* PEX4LIODNR */
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 12>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 43 1 0 0
|
||||
0000 0 0 2 &mpic 0 1 0 0
|
||||
0000 0 0 3 &mpic 4 1 0 0
|
||||
0000 0 0 4 &mpic 8 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 11>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 27
|
||||
16 2 1 26>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
|
||||
ranges = <0 0x20000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
fsl,portid-mapping = <0x3c000000>;
|
||||
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p5020-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-gpio-0.dtsi"
|
||||
/include/ "qoriq-usb2-mph-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
phy_type = "utmi";
|
||||
port0;
|
||||
};
|
||||
|
||||
/include/ "qoriq-usb2-dr-0.dtsi"
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-0.dtsi"
|
||||
sata@220000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-1.dtsi"
|
||||
sata@221000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
|
||||
};
|
||||
/include/ "qoriq-sec4.2-0.dtsi"
|
||||
crypto@300000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-raid1.0-0.dtsi"
|
||||
raideng@320000 {
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
};
|
||||
};
|
||||
109
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
Normal file
109
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* P5020/P5010 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e5500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P5020";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
|
||||
raideng = &raideng;
|
||||
raideng_jr0 = &raideng_jr0;
|
||||
raideng_jr1 = &raideng_jr1;
|
||||
raideng_jr2 = &raideng_jr2;
|
||||
raideng_jr3 = &raideng_jr3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e5500@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&mux1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
446
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
Normal file
446
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
Normal file
|
|
@ -0,0 +1,446 @@
|
|||
/*
|
||||
* P5040 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of this
|
||||
* software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
&lbc {
|
||||
compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 15>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 15>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x201000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 14>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 14>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x202000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupts = <16 2 1 13>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
interrupts = <16 2 1 13>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,p5040-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,dcsr-npc";
|
||||
reg = <0x1000 0x1000 0x1000000 0x8000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0xB0000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@40000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x40000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@41000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x41000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@42000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x42000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@43000 {
|
||||
compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x43000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000>;
|
||||
interrupts = <16 2 1 27
|
||||
16 2 1 26>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
|
||||
ranges = <0 0x20000 0x5000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <24 2 0 0
|
||||
16 2 1 30>;
|
||||
fsl,portid-mapping = <0x0f800000>;
|
||||
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
|
||||
pamu4: pamu@4000 {
|
||||
reg = <0x4000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <128 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,p5040-device-config", "fsl,qoriq-device-config-1.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
#sleep-cells = <1>;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
pins: global-utilities@e0e00 {
|
||||
compatible = "fsl,p5040-pin-control", "fsl,qoriq-pin-control-1.0";
|
||||
reg = <0xe0e00 0x200>;
|
||||
#sleep-cells = <2>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
|
||||
ranges = <0x0 0xe1000 0x1000>;
|
||||
reg = <0xe1000 0x1000>;
|
||||
clock-frequency = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x800 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll0", "pll0-div2";
|
||||
};
|
||||
|
||||
pll1: pll1@820 {
|
||||
#clock-cells = <1>;
|
||||
reg = <0x820 0x4>;
|
||||
compatible = "fsl,qoriq-core-pll-1.0";
|
||||
clocks = <&sysclk>;
|
||||
clock-output-names = "pll1", "pll1-div2";
|
||||
};
|
||||
|
||||
mux0: mux0@0 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x0 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux0";
|
||||
};
|
||||
|
||||
mux1: mux1@20 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x20 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux1";
|
||||
};
|
||||
|
||||
mux2: mux2@40 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x40 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux2";
|
||||
};
|
||||
|
||||
mux3: mux3@60 {
|
||||
#clock-cells = <0>;
|
||||
reg = <0x60 0x4>;
|
||||
compatible = "fsl,qoriq-core-mux-1.0";
|
||||
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
|
||||
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
|
||||
clock-output-names = "cmux3";
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,p5040-rcpm", "fsl,qoriq-rcpm-1.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
#sleep-cells = <1>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,p5040-serdes";
|
||||
reg = <0xea000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
fsl,iommu-parent = <&pamu2>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-gpio-0.dtsi"
|
||||
/include/ "qoriq-usb2-mph-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
||||
fsl,iommu-parent = <&pamu4>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
phy_type = "utmi";
|
||||
port0;
|
||||
};
|
||||
|
||||
/include/ "qoriq-usb2-dr-0.dtsi"
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu4>;
|
||||
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-0.dtsi"
|
||||
sata@220000 {
|
||||
fsl,iommu-parent = <&pamu4>;
|
||||
fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sata2-1.dtsi"
|
||||
sata@221000 {
|
||||
fsl,iommu-parent = <&pamu4>;
|
||||
fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-sec5.2-0.dtsi"
|
||||
crypto@300000 {
|
||||
fsl,iommu-parent = <&pamu4>;
|
||||
};
|
||||
};
|
||||
122
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
Normal file
122
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* P5040 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of this
|
||||
* software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e5500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,P5040";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
msi0 = &msi0;
|
||||
msi1 = &msi1;
|
||||
msi2 = &msi2;
|
||||
|
||||
crypto = &crypto;
|
||||
sec_jr0 = &sec_jr0;
|
||||
sec_jr1 = &sec_jr1;
|
||||
sec_jr2 = &sec_jr2;
|
||||
sec_jr3 = &sec_jr3;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e5500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&mux0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
fsl,portid-mapping = <0x80000000>;
|
||||
L2_0: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu1: PowerPC,e5500@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&mux1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
fsl,portid-mapping = <0x40000000>;
|
||||
L2_1: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu2: PowerPC,e5500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
clocks = <&mux2>;
|
||||
next-level-cache = <&L2_2>;
|
||||
fsl,portid-mapping = <0x20000000>;
|
||||
L2_2: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
cpu3: PowerPC,e5500@3 {
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
clocks = <&mux3>;
|
||||
next-level-cache = <&L2_3>;
|
||||
fsl,portid-mapping = <0x10000000>;
|
||||
L2_3: l2-cache {
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* PQ3 DMA device tree stub [ controller @ offset 0x21000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0x21300 0x4>;
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <20 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <21 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <22 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <23 2 0 0>;
|
||||
};
|
||||
};
|
||||
66
arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
Normal file
66
arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,eloplus-dma";
|
||||
reg = <0xc300 0x4>;
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
cell-index = <1>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x0 0x80>;
|
||||
cell-index = <0>;
|
||||
interrupts = <76 2 0 0>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x80 0x80>;
|
||||
cell-index = <1>;
|
||||
interrupts = <77 2 0 0>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x100 0x80>;
|
||||
cell-index = <2>;
|
||||
interrupts = <78 2 0 0>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,eloplus-dma-channel";
|
||||
reg = <0x180 0x80>;
|
||||
cell-index = <3>;
|
||||
interrupts = <79 2 0 0>;
|
||||
};
|
||||
};
|
||||
51
arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
Normal file
51
arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* PQ3 DUART device tree stub [ controller @ offset 0x4000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2 0 0>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "fsl,ns16550", "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <42 2 0 0>;
|
||||
};
|
||||
41
arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
Normal file
41
arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
sdhc@2e000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <72 0x2 0 0>;
|
||||
/* Filled in by U-Boot */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
41
arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
Normal file
41
arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* PQ3 eSPI device tree stub [ controller @ offset 0x7000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
spi@7000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8536-espi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <59 0x2 0 0>;
|
||||
};
|
||||
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
Normal file
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
};
|
||||
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
Normal file
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x25520 0x20>;
|
||||
};
|
||||
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
Normal file
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
ranges = <0x0 0x26000 0x1000>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x26520 0x20>;
|
||||
};
|
||||
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
Normal file
54
arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
|
||||
*
|
||||
* Copyright 2011-2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x27000 0x1000>;
|
||||
ranges = <0x0 0x27000 0x1000>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
|
||||
};
|
||||
|
||||
mdio@27520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x27520 0x20>;
|
||||
};
|
||||
39
arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
Normal file
39
arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
ptp_clock@24e00 {
|
||||
compatible = "fsl,etsec-ptp";
|
||||
reg = <0x24e00 0xb0>;
|
||||
interrupts = <68 2 0 0 69 2 0 0>;
|
||||
};
|
||||
61
arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
Normal file
61
arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
mdio@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-mdio";
|
||||
reg = <0x24000 0x1000 0xb0030 0x4>;
|
||||
};
|
||||
|
||||
ethernet@b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
ranges;
|
||||
|
||||
queue-group@b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb0000 0x1000>;
|
||||
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
|
||||
};
|
||||
};
|
||||
61
arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
Normal file
61
arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
mdio@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x25000 0x1000 0xb1030 0x4>;
|
||||
};
|
||||
|
||||
ethernet@b1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
ranges;
|
||||
|
||||
queue-group@b1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb1000 0x1000>;
|
||||
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
|
||||
};
|
||||
};
|
||||
60
arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
Normal file
60
arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
mdio@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,etsec2-tbi";
|
||||
reg = <0x26000 0x1000 0xb1030 0x4>;
|
||||
};
|
||||
|
||||
ethernet@b2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "fsl,etsec2";
|
||||
fsl,num_rx_queues = <0x8>;
|
||||
fsl,num_tx_queues = <0x8>;
|
||||
fsl,magic-packet;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
ranges;
|
||||
|
||||
queue-group@b2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb2000 0x1000>;
|
||||
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
|
||||
};
|
||||
};
|
||||
42
arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
Normal file
42
arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&enet0_grp2 {
|
||||
queue-group@b4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xb4000 0x1000>;
|
||||
interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
|
||||
};
|
||||
};
|
||||
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Add a link
Reference in a new issue