mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
415
arch/powerpc/boot/dts/akebono.dts
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415
arch/powerpc/boot/dts/akebono.dts
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@ -0,0 +1,415 @@
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/*
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* Device Tree Source for IBM Embedded PPC 476 Platform
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*
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* Copyright © 2013 Tony Breeds IBM Corporation
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* Copyright © 2013 Alistair Popple IBM Corporation
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/memreserve/ 0x01f00000 0x00100000; // spin table
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "ibm,akebono";
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compatible = "ibm,akebono", "ibm,476gtr";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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serial0 = &UART0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,476";
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reg = <0>;
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clock-frequency = <1600000000>; // 1.6 GHz
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timebase-frequency = <100000000>; // 100Mhz
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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status = "ok";
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};
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cpu@1 {
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device_type = "cpu";
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model = "PowerPC,476";
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reg = <1>;
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clock-frequency = <1600000000>; // 1.6 GHz
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timebase-frequency = <100000000>; // 100Mhz
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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status = "disabled";
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x01f00000>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
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};
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MPIC: interrupt-controller {
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compatible = "chrp,open-pic";
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interrupt-controller;
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dcr-reg = <0xffc00000 0x00040000>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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single-cpu-affinity;
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};
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plb {
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compatible = "ibm,plb6";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-frequency = <200000000>; // 200Mhz
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HSTA0: hsta@310000e0000 {
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compatible = "ibm,476gtr-hsta-msi", "ibm,hsta-msi";
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reg = <0x310 0x000e0000 0x0 0xf0>;
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interrupt-parent = <&MPIC>;
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interrupts = <108 0
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109 0
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110 0
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111 0
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112 0
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113 0
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114 0
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115 0
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116 0
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117 0
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118 0
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119 0
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120 0
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121 0
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122 0
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123 0>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-476gtr", "ibm,mcmal2";
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dcr-reg = <0xc0000000 0x062>;
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num-tx-chans = <1>;
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num-rx-chans = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-parent = <&MPIC>;
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interrupts = < /*TXEOB*/ 77 0x4
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/*RXEOB*/ 78 0x4
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/*SERR*/ 76 0x4
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/*TXDE*/ 79 0x4
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/*RXDE*/ 80 0x4>;
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};
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SATA0: sata@30000010000 {
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compatible = "ibm,476gtr-ahci";
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reg = <0x300 0x00010000 0x0 0x10000>;
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interrupt-parent = <&MPIC>;
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interrupts = <93 2>;
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};
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EHCI0: ehci@30010000000 {
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compatible = "ibm,476gtr-ehci", "generic-ehci";
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reg = <0x300 0x10000000 0x0 0x10000>;
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interrupt-parent = <&MPIC>;
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interrupts = <85 2>;
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};
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SD0: sd@30000000000 {
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compatible = "ibm,476gtr-sdhci", "generic-sdhci";
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reg = <0x300 0x00000000 0x0 0x10000>;
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interrupts = <91 2>;
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interrupt-parent = <&MPIC>;
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};
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OHCI0: ohci@30010010000 {
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compatible = "ibm,476gtr-ohci", "generic-ohci";
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reg = <0x300 0x10010000 0x0 0x10000>;
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interrupt-parent = <&MPIC>;
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interrupts = <89 1>;
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};
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OHCI1: ohci@30010020000 {
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compatible = "ibm,476gtr-ohci", "generic-ohci";
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reg = <0x300 0x10020000 0x0 0x10000>;
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interrupt-parent = <&MPIC>;
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interrupts = <88 1>;
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};
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POB0: opb {
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compatible = "ibm,opb-4xx", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Wish there was a nicer way of specifying a full
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* 32-bit range
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*/
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ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
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0x80000000 0x0000033f 0x80000000 0x80000000>;
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clock-frequency = <100000000>;
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RGMII0: emac-rgmii-wol@50004 {
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compatible = "ibm,rgmii-wol-476gtr", "ibm,rgmii-wol";
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reg = <0x50004 0x00000008>;
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has-mdio;
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};
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EMAC0: ethernet@30000 {
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device_type = "network";
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compatible = "ibm,emac-476gtr", "ibm,emac4sync";
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interrupt-parent = <&EMAC0>;
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interrupts = <0x0 0x1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
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/*Wake*/ 0x1 &MPIC 82 0x4>;
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reg = <0x30000 0x78>;
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/* local-mac-address will normally be added by
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* the wrapper. If your device doesn't support
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* passing data to the wrapper (in the form
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* local-mac-addr=<hwaddr>) then you will need
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* to set it manually here. */
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//local-mac-address = [000000000000];
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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rx-fifo-size-gige = <16384>;
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phy-mode = "rgmii";
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phy-map = <0x00000000>;
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rgmii-wol-device = <&RGMII0>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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UART0: serial@10000 {
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device_type = "serial";
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compatible = "ns16750", "ns16550";
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reg = <0x10000 0x00000008>;
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virtual-reg = <0xe8010000>;
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clock-frequency = <1851851>;
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current-speed = <38400>;
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interrupt-parent = <&MPIC>;
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interrupts = <39 2>;
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};
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IIC0: i2c@00000000 {
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compatible = "ibm,iic-476gtr", "ibm,iic";
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reg = <0x0 0x00000020>;
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interrupt-parent = <&MPIC>;
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interrupts = <37 2>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@68 {
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compatible = "stm,m41t80", "m41st85";
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reg = <0x68>;
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};
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};
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IIC1: i2c@00000100 {
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compatible = "ibm,iic-476gtr", "ibm,iic";
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reg = <0x100 0x00000020>;
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interrupt-parent = <&MPIC>;
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interrupts = <38 2>;
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#address-cells = <1>;
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#size-cells = <0>;
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avr@58 {
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compatible = "ibm,akebono-avr";
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reg = <0x58>;
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};
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};
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FPGA0: fpga@ebc00000 {
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compatible = "ibm,akebono-fpga";
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reg = <0xebc00000 0x8>;
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};
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};
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PCIE0: pciex@10100000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
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primary;
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port = <0x0>; /* port number */
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reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
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0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
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dcr-reg = <0xc0 0x20>;
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// pci_space < pci_addr > < cpu_addr > < size >
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ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
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0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
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/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
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* PCI devices must be able to write to the HSTA module.
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*/
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
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/* This drives busses 0 to 0xf */
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bus-range = <0x0 0xf>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
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0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
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0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
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0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
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};
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PCIE1: pciex@20100000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
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primary;
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port = <0x1>; /* port number */
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reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
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0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
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dcr-reg = <0x100 0x20>;
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// pci_space < pci_addr > < cpu_addr > < size >
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ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
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0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
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/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
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* PCI devices must be able to write to the HSTA module.
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*/
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
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/* This drives busses 0 to 0xf */
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bus-range = <0x0 0xf>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
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0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
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0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
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0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
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};
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PCIE2: pciex@18100000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
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primary;
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port = <0x2>; /* port number */
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reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
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0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
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dcr-reg = <0xe0 0x20>;
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// pci_space < pci_addr > < cpu_addr > < size >
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ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
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0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
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/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
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* PCI devices must be able to write to the HSTA module.
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*/
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
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/* This drives busses 0 to 0xf */
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bus-range = <0x0 0xf>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
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0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
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0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
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0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
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};
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PCIE3: pciex@28100000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
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primary;
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port = <0x3>; /* port number */
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reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
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0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
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dcr-reg = <0x120 0x20>;
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// pci_space < pci_addr > < cpu_addr > < size >
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ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
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0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
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/* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
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* PCI devices must be able to write to the HSTA module.
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*/
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
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/* This drives busses 0 to 0xf */
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bus-range = <0x0 0xf>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
|
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* port of the root complex virtual P2P bridge. But I want
|
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* to avoid putting a node for it in the tree, so the numbers
|
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
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0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
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0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
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0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;
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};
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};
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chosen {
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linux,stdout-path = &UART0;
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||||
};
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||||
};
|
||||
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