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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
291
arch/powerpc/boot/dts/p2020rdb.dts
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291
arch/powerpc/boot/dts/p2020rdb.dts
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/*
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* P2020 RDB Device Tree Source
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*
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* Copyright 2009-2012 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/p2020si-pre.dtsi"
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/ {
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model = "fsl,P2020RDB";
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compatible = "fsl,P2020RDB";
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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memory {
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device_type = "memory";
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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/* NOR and NAND Flashes */
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ranges = <0x0 0x0 0x0 0xef000000 0x01000000
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0x1 0x0 0x0 0xffa00000 0x00040000
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0x2 0x0 0x0 0xffb00000 0x00020000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x1000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* This location must not be altered */
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/* 256KB for Vitesse 7385 Switch firmware */
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reg = <0x0 0x00040000>;
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label = "NOR (RO) Vitesse-7385 Firmware";
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read-only;
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};
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partition@40000 {
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/* 256KB for DTB Image */
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reg = <0x00040000 0x00040000>;
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label = "NOR (RO) DTB Image";
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read-only;
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};
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partition@80000 {
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/* 3.5 MB for Linux Kernel Image */
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reg = <0x00080000 0x00380000>;
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label = "NOR (RO) Linux Kernel Image";
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read-only;
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};
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partition@400000 {
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/* 11MB for JFFS2 based Root file System */
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reg = <0x00400000 0x00b00000>;
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label = "NOR (RW) JFFS2 Root File System";
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};
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partition@f00000 {
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/* This location must not be altered */
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/* 512KB for u-boot Bootloader Image */
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/* 512KB for u-boot Environment Variables */
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reg = <0x00f00000 0x00100000>;
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label = "NOR (RO) U-Boot Image";
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read-only;
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p2020-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x40000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND (RO) U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND (RO) DTB Image";
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read-only;
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};
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partition@200000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00200000 0x00400000>;
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label = "NAND (RO) Linux Kernel Image";
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read-only;
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};
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partition@600000 {
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/* 4MB for Compressed Root file System Image */
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reg = <0x00600000 0x00400000>;
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label = "NAND (RO) Compressed RFS Image";
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read-only;
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};
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partition@a00000 {
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/* 7MB for JFFS2 based Root file System */
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reg = <0x00a00000 0x00700000>;
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label = "NAND (RW) JFFS2 Root File System";
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};
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partition@1100000 {
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/* 15MB for JFFS2 based Root file System */
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reg = <0x01100000 0x00f00000>;
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label = "NAND (RW) Writable User area";
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};
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};
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L2switch@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "vitesse-7385";
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reg = <0x2 0x0 0x20000>;
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};
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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i2c@3000 {
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <40000000>;
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partition@0 {
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/* 512KB for u-boot Bootloader Image */
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reg = <0x0 0x00080000>;
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label = "SPI (RO) U-Boot Image";
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read-only;
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};
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partition@80000 {
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/* 512KB for DTB Image */
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reg = <0x00080000 0x00080000>;
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label = "SPI (RO) DTB Image";
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read-only;
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};
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partition@100000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00100000 0x00400000>;
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label = "SPI (RO) Linux Kernel Image";
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read-only;
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};
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partition@500000 {
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/* 4MB for Compressed RFS Image */
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reg = <0x00500000 0x00400000>;
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label = "SPI (RO) Compressed RFS Image";
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read-only;
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};
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partition@900000 {
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/* 7MB for JFFS2 based RFS */
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reg = <0x00900000 0x00700000>;
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label = "SPI (RW) JFFS2 RFS";
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};
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};
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupts = <3 1 0 0>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <3 1 0 0>;
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reg = <0x1>;
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};
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tbi-phy@2 {
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device_type = "tbi-phy";
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reg = <0x2>;
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};
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};
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mdio@25520 {
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26520 {
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status = "disabled";
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};
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ptp_clock@24e00 {
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fsl,tclk-period = <5>;
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fsl,tmr-prsc = <200>;
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fsl,tmr-add = <0xCCCCCCCD>;
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fsl,tmr-fiper1 = <0x3B9AC9FB>;
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fsl,tmr-fiper2 = <0x0001869B>;
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fsl,max-adj = <249999999>;
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};
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enet0: ethernet@24000 {
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fixed-link = <1 1 1000 0 0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "sgmii";
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};
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enet2: ethernet@26000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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};
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pci0: pcie@ffe08000 {
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reg = <0 0xffe08000 0 0x1000>;
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status = "disabled";
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};
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pci1: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci2: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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/include/ "fsl/p2020si-post.dtsi"
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