mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
399
arch/powerpc/boot/dts/tqm8560.dts
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399
arch/powerpc/boot/dts/tqm8560.dts
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/*
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* TQM 8560 Device Tree Source
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*
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* Copyright 2008 Freescale Semiconductor Inc.
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* Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "tqc,tqm8560";
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compatible = "tqc,tqm8560";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8560@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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soc@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x0 0xe0000000 0x100000>;
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bus-frequency = <0>;
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compatible = "fsl,mpc8560-immr", "simple-bus";
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <8>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8560-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8540-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8540-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>;
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cache-size = <0x40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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dtt@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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};
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8560-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy2>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <3>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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device_type = "open-pic";
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compatible = "chrp,open-pic";
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};
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cpm@919c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
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reg = <0x919c0 0x30>;
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ranges;
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muram@80000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x80000 0x10000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0 0x4000 0x9000 0x2000>;
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};
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};
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brg@919f0 {
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compatible = "fsl,mpc8560-brg",
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"fsl,cpm2-brg",
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"fsl,cpm-brg";
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reg = <0x919f0 0x10 0x915f0 0x10>;
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clock-frequency = <0>;
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};
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cpmpic: pic@90c00 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <46 2>;
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interrupt-parent = <&mpic>;
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reg = <0x90c00 0x80>;
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compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
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};
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serial0: serial@91a00 {
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device_type = "serial";
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compatible = "fsl,mpc8560-scc-uart",
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"fsl,cpm2-scc-uart";
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reg = <0x91a00 0x20 0x88000 0x100>;
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fsl,cpm-brg = <1>;
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fsl,cpm-command = <0x800000>;
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current-speed = <115200>;
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interrupts = <40 8>;
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interrupt-parent = <&cpmpic>;
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};
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serial1: serial@91a20 {
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device_type = "serial";
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compatible = "fsl,mpc8560-scc-uart",
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"fsl,cpm2-scc-uart";
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reg = <0x91a20 0x20 0x88100 0x100>;
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fsl,cpm-brg = <2>;
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fsl,cpm-command = <0x4a00000>;
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current-speed = <115200>;
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interrupts = <41 8>;
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interrupt-parent = <&cpmpic>;
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};
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enet2: ethernet@91340 {
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device_type = "network";
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compatible = "fsl,mpc8560-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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fsl,cpm-command = <0x1a400300>;
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interrupts = <34 8>;
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interrupt-parent = <&cpmpic>;
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phy-handle = <&phy3>;
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};
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};
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};
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localbus@e0005000 {
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compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
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"simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0xe0005000 0x100>; // BRx, ORx, etc.
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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ranges = <
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0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
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1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
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2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
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>;
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flash@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <1 0x0 0x8000000>;
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bank-width = <4>;
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device-width = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00200000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x00200000 0x00300000>;
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};
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partition@500000 {
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label = "user";
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reg = <0x00500000 0x07a00000>;
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};
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partition@7f00000 {
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label = "env1";
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reg = <0x07f00000 0x00040000>;
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};
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partition@7f40000 {
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label = "env2";
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reg = <0x07f40000 0x00040000>;
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};
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partition@7f80000 {
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label = "u-boot";
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reg = <0x07f80000 0x00080000>;
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read-only;
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};
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};
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/* Note: CAN support needs be enabled in U-Boot */
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can0@2,0 {
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compatible = "intel,82527"; // Bosch CC770
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reg = <2 0x0 0x100>;
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interrupts = <4 1>;
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interrupt-parent = <&mpic>;
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};
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can1@2,100 {
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compatible = "intel,82527"; // Bosch CC770
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reg = <2 0x100 0x100>;
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interrupts = <4 1>;
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interrupt-parent = <&mpic>;
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};
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};
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pci0: pci@e0008000 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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reg = <0xe0008000 0x1000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 28 */
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0xe000 0 0 1 &mpic 2 1
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0xe000 0 0 2 &mpic 3 1
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0xe000 0 0 3 &mpic 6 1
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0xe000 0 0 4 &mpic 5 1
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/* IDSEL 11 */
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0x5800 0 0 1 &mpic 6 1
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0x5800 0 0 2 &mpic 5 1
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>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 0>;
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ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
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0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
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};
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};
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