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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 00:55:37 +01:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
289
arch/powerpc/include/asm/bitops.h
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289
arch/powerpc/include/asm/bitops.h
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/*
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* PowerPC atomic bit operations.
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*
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* Merged version by David Gibson <david@gibson.dropbear.id.au>.
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* Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
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* Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
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* originally took it from the ppc32 code.
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*
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* Within a word, bits are numbered LSB first. Lot's of places make
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* this assumption by directly testing bits with (val & (1<<nr)).
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* This can cause confusion for large (> 1 word) bitmaps on a
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* big-endian system because, unlike little endian, the number of each
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* bit depends on the word size.
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*
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* The bitop functions are defined to work on unsigned longs, so for a
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* ppc64 system the bits end up numbered:
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* |63..............0|127............64|191...........128|255...........196|
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* and on ppc32:
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* |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
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*
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* There are a few little-endian macros used mostly for filesystem
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* bitmaps, these work on similar bit arrays layouts, but
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* byte-oriented:
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* |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
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*
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* The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
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* number field needs to be reversed compared to the big-endian bit
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* fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_BITOPS_H
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#define _ASM_POWERPC_BITOPS_H
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#ifdef __KERNEL__
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/compiler.h>
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#include <asm/asm-compat.h>
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#include <asm/synch.h>
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/* PPC bit number conversion */
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#define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be))
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#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))
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#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
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#include <asm/barrier.h>
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/* Macro for generating the ***_bits() functions */
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#define DEFINE_BITOP(fn, op, prefix) \
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static __inline__ void fn(unsigned long mask, \
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volatile unsigned long *_p) \
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{ \
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unsigned long old; \
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unsigned long *p = (unsigned long *)_p; \
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__asm__ __volatile__ ( \
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prefix \
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"1:" PPC_LLARX(%0,0,%3,0) "\n" \
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stringify_in_c(op) "%0,%0,%2\n" \
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PPC405_ERR77(0,%3) \
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PPC_STLCX "%0,0,%3\n" \
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"bne- 1b\n" \
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: "=&r" (old), "+m" (*p) \
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: "r" (mask), "r" (p) \
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: "cc", "memory"); \
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}
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DEFINE_BITOP(set_bits, or, "")
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DEFINE_BITOP(clear_bits, andc, "")
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DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER)
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DEFINE_BITOP(change_bits, xor, "")
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static __inline__ void set_bit(int nr, volatile unsigned long *addr)
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{
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set_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
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}
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static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
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{
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clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
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}
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static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
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{
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clear_bits_unlock(BIT_MASK(nr), addr + BIT_WORD(nr));
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}
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static __inline__ void change_bit(int nr, volatile unsigned long *addr)
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{
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change_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
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}
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/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
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* operands. */
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#define DEFINE_TESTOP(fn, op, prefix, postfix, eh) \
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static __inline__ unsigned long fn( \
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unsigned long mask, \
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volatile unsigned long *_p) \
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{ \
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unsigned long old, t; \
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unsigned long *p = (unsigned long *)_p; \
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__asm__ __volatile__ ( \
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prefix \
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"1:" PPC_LLARX(%0,0,%3,eh) "\n" \
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stringify_in_c(op) "%1,%0,%2\n" \
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PPC405_ERR77(0,%3) \
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PPC_STLCX "%1,0,%3\n" \
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"bne- 1b\n" \
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postfix \
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: "=&r" (old), "=&r" (t) \
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: "r" (mask), "r" (p) \
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: "cc", "memory"); \
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return (old & mask); \
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}
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DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER,
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PPC_ATOMIC_EXIT_BARRIER, 0)
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DEFINE_TESTOP(test_and_set_bits_lock, or, "",
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PPC_ACQUIRE_BARRIER, 1)
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DEFINE_TESTOP(test_and_clear_bits, andc, PPC_ATOMIC_ENTRY_BARRIER,
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PPC_ATOMIC_EXIT_BARRIER, 0)
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DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER,
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PPC_ATOMIC_EXIT_BARRIER, 0)
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static __inline__ int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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return test_and_set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
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}
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static __inline__ int test_and_set_bit_lock(unsigned long nr,
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volatile unsigned long *addr)
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{
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return test_and_set_bits_lock(BIT_MASK(nr),
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addr + BIT_WORD(nr)) != 0;
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}
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static __inline__ int test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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return test_and_clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
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}
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static __inline__ int test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
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}
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#include <asm-generic/bitops/non-atomic.h>
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static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
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{
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__asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
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__clear_bit(nr, addr);
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}
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/*
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* Return the zero-based bit position (LE, not IBM bit numbering) of
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* the most significant 1-bit in a double word.
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*/
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static __inline__ __attribute__((const))
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int __ilog2(unsigned long x)
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{
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int lz;
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asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
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return BITS_PER_LONG - 1 - lz;
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}
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static inline __attribute__((const))
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int __ilog2_u32(u32 n)
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{
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int bit;
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asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
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return 31 - bit;
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}
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#ifdef __powerpc64__
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static inline __attribute__((const))
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int __ilog2_u64(u64 n)
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{
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int bit;
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asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
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return 63 - bit;
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}
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#endif
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/*
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* Determines the bit position of the least significant 0 bit in the
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* specified double word. The returned bit position will be
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* zero-based, starting from the right side (63/31 - 0).
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*/
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static __inline__ unsigned long ffz(unsigned long x)
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{
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/* no zero exists anywhere in the 8 byte area. */
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if ((x = ~x) == 0)
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return BITS_PER_LONG;
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/*
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* Calculate the bit position of the least significant '1' bit in x
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* (since x has been changed this will actually be the least significant
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* '0' bit in * the original x). Note: (x & -x) gives us a mask that
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* is the least significant * (RIGHT-most) 1-bit of the value in x.
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*/
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return __ilog2(x & -x);
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}
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static __inline__ int __ffs(unsigned long x)
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{
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return __ilog2(x & -x);
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}
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/*
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* ffs: find first bit set. This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static __inline__ int ffs(int x)
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{
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unsigned long i = (unsigned long)x;
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return __ilog2(i & -i) + 1;
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}
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/*
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* fls: find last (most-significant) bit set.
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* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
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*/
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static __inline__ int fls(unsigned int x)
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{
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int lz;
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asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
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return 32 - lz;
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}
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static __inline__ unsigned long __fls(unsigned long x)
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{
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return __ilog2(x);
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}
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/*
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* 64-bit can do this using one cntlzd (count leading zeroes doubleword)
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* instruction; for 32-bit we use the generic version, which does two
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* 32-bit fls calls.
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*/
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#ifdef __powerpc64__
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static __inline__ int fls64(__u64 x)
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{
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int lz;
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asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
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return 64 - lz;
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}
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#else
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#include <asm-generic/bitops/fls64.h>
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#endif /* __powerpc64__ */
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#ifdef CONFIG_PPC64
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unsigned int __arch_hweight8(unsigned int w);
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unsigned int __arch_hweight16(unsigned int w);
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unsigned int __arch_hweight32(unsigned int w);
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unsigned long __arch_hweight64(__u64 w);
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#include <asm-generic/bitops/const_hweight.h>
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#else
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#include <asm-generic/bitops/hweight.h>
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#endif
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#include <asm-generic/bitops/find.h>
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/* Little-endian versions */
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#include <asm-generic/bitops/le.h>
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/* Bitmap functions for the ext2 filesystem */
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#include <asm-generic/bitops/ext2-atomic-setbit.h>
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#include <asm-generic/bitops/sched.h>
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_BITOPS_H */
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