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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
313
arch/powerpc/kernel/mce_power.c
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313
arch/powerpc/kernel/mce_power.c
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/*
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* Machine check exception handling CPU-side for power7 and power8
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2013 IBM Corporation
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* Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
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*/
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#undef DEBUG
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#define pr_fmt(fmt) "mce_power: " fmt
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <asm/mmu.h>
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#include <asm/mce.h>
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#include <asm/machdep.h>
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/* flush SLBs and reload */
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static void flush_and_reload_slb(void)
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{
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struct slb_shadow *slb;
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unsigned long i, n;
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/* Invalidate all SLBs */
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asm volatile("slbmte %0,%0; slbia" : : "r" (0));
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#ifdef CONFIG_KVM_BOOK3S_HANDLER
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/*
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* If machine check is hit when in guest or in transition, we will
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* only flush the SLBs and continue.
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*/
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if (get_paca()->kvm_hstate.in_guest)
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return;
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#endif
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/* For host kernel, reload the SLBs from shadow SLB buffer. */
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slb = get_slb_shadow();
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if (!slb)
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return;
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n = min_t(u32, be32_to_cpu(slb->persistent), SLB_MIN_SIZE);
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/* Load up the SLB entries from shadow SLB */
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for (i = 0; i < n; i++) {
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unsigned long rb = be64_to_cpu(slb->save_area[i].esid);
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unsigned long rs = be64_to_cpu(slb->save_area[i].vsid);
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rb = (rb & ~0xFFFul) | i;
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asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
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}
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}
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static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
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{
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long handled = 1;
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/*
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* flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
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* reset the error bits whenever we handle them so that at the end
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* we can check whether we handled all of them or not.
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* */
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if (dsisr & slb_error_bits) {
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flush_and_reload_slb();
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/* reset error bits */
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dsisr &= ~(slb_error_bits);
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}
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if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
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if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
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cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);
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/* reset error bits */
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dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
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}
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/* Any other errors we don't understand? */
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if (dsisr & 0xffffffffUL)
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handled = 0;
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return handled;
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}
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static long mce_handle_derror_p7(uint64_t dsisr)
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{
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return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS);
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}
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static long mce_handle_common_ierror(uint64_t srr1)
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{
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long handled = 0;
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switch (P7_SRR1_MC_IFETCH(srr1)) {
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case 0:
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break;
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case P7_SRR1_MC_IFETCH_SLB_PARITY:
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case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
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/* flush and reload SLBs for SLB errors. */
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flush_and_reload_slb();
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handled = 1;
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break;
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case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
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if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
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cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);
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handled = 1;
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}
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break;
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default:
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break;
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}
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return handled;
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}
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static long mce_handle_ierror_p7(uint64_t srr1)
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{
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long handled = 0;
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handled = mce_handle_common_ierror(srr1);
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if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
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flush_and_reload_slb();
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handled = 1;
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}
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return handled;
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}
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static void mce_get_common_ierror(struct mce_error_info *mce_err, uint64_t srr1)
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{
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switch (P7_SRR1_MC_IFETCH(srr1)) {
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case P7_SRR1_MC_IFETCH_SLB_PARITY:
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mce_err->error_type = MCE_ERROR_TYPE_SLB;
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mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
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break;
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case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
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mce_err->error_type = MCE_ERROR_TYPE_SLB;
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mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
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break;
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case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
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mce_err->error_type = MCE_ERROR_TYPE_TLB;
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mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
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break;
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case P7_SRR1_MC_IFETCH_UE:
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case P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL:
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mce_err->error_type = MCE_ERROR_TYPE_UE;
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mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
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break;
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case P7_SRR1_MC_IFETCH_UE_TLB_RELOAD:
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mce_err->error_type = MCE_ERROR_TYPE_UE;
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mce_err->u.ue_error_type =
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MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
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break;
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}
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}
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static void mce_get_ierror_p7(struct mce_error_info *mce_err, uint64_t srr1)
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{
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mce_get_common_ierror(mce_err, srr1);
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if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
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mce_err->error_type = MCE_ERROR_TYPE_SLB;
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mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE;
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}
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}
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static void mce_get_derror_p7(struct mce_error_info *mce_err, uint64_t dsisr)
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{
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if (dsisr & P7_DSISR_MC_UE) {
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mce_err->error_type = MCE_ERROR_TYPE_UE;
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mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
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} else if (dsisr & P7_DSISR_MC_UE_TABLEWALK) {
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mce_err->error_type = MCE_ERROR_TYPE_UE;
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mce_err->u.ue_error_type =
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MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
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} else if (dsisr & P7_DSISR_MC_ERAT_MULTIHIT) {
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mce_err->error_type = MCE_ERROR_TYPE_ERAT;
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mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
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} else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT) {
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mce_err->error_type = MCE_ERROR_TYPE_SLB;
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mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
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} else if (dsisr & P7_DSISR_MC_SLB_PARITY_MFSLB) {
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mce_err->error_type = MCE_ERROR_TYPE_SLB;
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mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
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} else if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
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mce_err->error_type = MCE_ERROR_TYPE_TLB;
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mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
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} else if (dsisr & P7_DSISR_MC_SLB_MULTIHIT_PARITY) {
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mce_err->error_type = MCE_ERROR_TYPE_SLB;
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mce_err->u.slb_error_type = MCE_SLB_ERROR_INDETERMINATE;
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}
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}
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static long mce_handle_ue_error(struct pt_regs *regs)
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{
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long handled = 0;
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/*
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* On specific SCOM read via MMIO we may get a machine check
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* exception with SRR0 pointing inside opal. If that is the
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* case OPAL may have recovery address to re-read SCOM data in
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* different way and hence we can recover from this MC.
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*/
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if (ppc_md.mce_check_early_recovery) {
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if (ppc_md.mce_check_early_recovery(regs))
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handled = 1;
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}
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return handled;
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}
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long __machine_check_early_realmode_p7(struct pt_regs *regs)
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{
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uint64_t srr1, nip, addr;
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long handled = 1;
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struct mce_error_info mce_error_info = { 0 };
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srr1 = regs->msr;
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nip = regs->nip;
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/*
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* Handle memory errors depending whether this was a load/store or
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* ifetch exception. Also, populate the mce error_type and
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* type-specific error_type from either SRR1 or DSISR, depending
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* whether this was a load/store or ifetch exception
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*/
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if (P7_SRR1_MC_LOADSTORE(srr1)) {
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handled = mce_handle_derror_p7(regs->dsisr);
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mce_get_derror_p7(&mce_error_info, regs->dsisr);
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addr = regs->dar;
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} else {
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handled = mce_handle_ierror_p7(srr1);
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mce_get_ierror_p7(&mce_error_info, srr1);
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addr = regs->nip;
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}
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/* Handle UE error. */
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if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
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handled = mce_handle_ue_error(regs);
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save_mce_event(regs, handled, &mce_error_info, nip, addr);
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return handled;
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}
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static void mce_get_ierror_p8(struct mce_error_info *mce_err, uint64_t srr1)
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{
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mce_get_common_ierror(mce_err, srr1);
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if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
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mce_err->error_type = MCE_ERROR_TYPE_ERAT;
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mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
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}
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}
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static void mce_get_derror_p8(struct mce_error_info *mce_err, uint64_t dsisr)
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{
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mce_get_derror_p7(mce_err, dsisr);
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if (dsisr & P8_DSISR_MC_ERAT_MULTIHIT_SEC) {
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mce_err->error_type = MCE_ERROR_TYPE_ERAT;
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mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
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}
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}
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static long mce_handle_ierror_p8(uint64_t srr1)
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{
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long handled = 0;
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handled = mce_handle_common_ierror(srr1);
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if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
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flush_and_reload_slb();
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handled = 1;
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}
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return handled;
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}
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static long mce_handle_derror_p8(uint64_t dsisr)
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{
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return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS);
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}
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long __machine_check_early_realmode_p8(struct pt_regs *regs)
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{
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uint64_t srr1, nip, addr;
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long handled = 1;
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struct mce_error_info mce_error_info = { 0 };
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srr1 = regs->msr;
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nip = regs->nip;
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if (P7_SRR1_MC_LOADSTORE(srr1)) {
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handled = mce_handle_derror_p8(regs->dsisr);
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mce_get_derror_p8(&mce_error_info, regs->dsisr);
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addr = regs->dar;
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} else {
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handled = mce_handle_ierror_p8(srr1);
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mce_get_ierror_p8(&mce_error_info, srr1);
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addr = regs->nip;
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}
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/* Handle UE error. */
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if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
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handled = mce_handle_ue_error(regs);
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save_mce_event(regs, handled, &mce_error_info, nip, addr);
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return handled;
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}
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