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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
302
arch/powerpc/kernel/udbg_16550.c
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302
arch/powerpc/kernel/udbg_16550.c
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/*
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* udbg for NS16550 compatible serial ports
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*
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* Copyright (C) 2001-2005 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <asm/udbg.h>
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#include <asm/io.h>
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#include <asm/reg_a2.h>
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extern u8 real_readb(volatile u8 __iomem *addr);
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extern void real_writeb(u8 data, volatile u8 __iomem *addr);
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extern u8 real_205_readb(volatile u8 __iomem *addr);
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extern void real_205_writeb(u8 data, volatile u8 __iomem *addr);
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#define UART_RBR 0
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#define UART_IER 1
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#define UART_FCR 2
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#define UART_LCR 3
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#define UART_MCR 4
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#define UART_LSR 5
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#define UART_MSR 6
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#define UART_SCR 7
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#define UART_THR UART_RBR
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#define UART_IIR UART_FCR
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#define UART_DLL UART_RBR
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#define UART_DLM UART_IER
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#define UART_DLAB UART_LCR
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#define LSR_DR 0x01 /* Data ready */
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#define LSR_OE 0x02 /* Overrun */
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#define LSR_PE 0x04 /* Parity error */
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#define LSR_FE 0x08 /* Framing error */
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#define LSR_BI 0x10 /* Break */
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#define LSR_THRE 0x20 /* Xmit holding register empty */
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#define LSR_TEMT 0x40 /* Xmitter empty */
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#define LSR_ERR 0x80 /* Error */
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#define LCR_DLAB 0x80
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static u8 (*udbg_uart_in)(unsigned int reg);
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static void (*udbg_uart_out)(unsigned int reg, u8 data);
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static void udbg_uart_flush(void)
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{
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if (!udbg_uart_in)
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return;
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/* wait for idle */
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while ((udbg_uart_in(UART_LSR) & LSR_THRE) == 0)
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cpu_relax();
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}
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static void udbg_uart_putc(char c)
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{
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if (!udbg_uart_out)
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return;
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if (c == '\n')
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udbg_uart_putc('\r');
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udbg_uart_flush();
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udbg_uart_out(UART_THR, c);
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}
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static int udbg_uart_getc_poll(void)
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{
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if (!udbg_uart_in)
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return -1;
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if (!(udbg_uart_in(UART_LSR) & LSR_DR))
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return udbg_uart_in(UART_RBR);
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return -1;
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}
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static int udbg_uart_getc(void)
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{
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if (!udbg_uart_in)
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return -1;
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/* wait for char */
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while (!(udbg_uart_in(UART_LSR) & LSR_DR))
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cpu_relax();
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return udbg_uart_in(UART_RBR);
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}
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static void udbg_use_uart(void)
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{
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udbg_putc = udbg_uart_putc;
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udbg_flush = udbg_uart_flush;
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udbg_getc = udbg_uart_getc;
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udbg_getc_poll = udbg_uart_getc_poll;
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}
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void udbg_uart_setup(unsigned int speed, unsigned int clock)
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{
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unsigned int dll, base_bauds;
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if (!udbg_uart_out)
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return;
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if (clock == 0)
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clock = 1843200;
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if (speed == 0)
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speed = 9600;
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base_bauds = clock / 16;
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dll = base_bauds / speed;
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udbg_uart_out(UART_LCR, 0x00);
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udbg_uart_out(UART_IER, 0xff);
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udbg_uart_out(UART_IER, 0x00);
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udbg_uart_out(UART_LCR, LCR_DLAB);
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udbg_uart_out(UART_DLL, dll & 0xff);
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udbg_uart_out(UART_DLM, dll >> 8);
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/* 8 data, 1 stop, no parity */
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udbg_uart_out(UART_LCR, 0x3);
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/* RTS/DTR */
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udbg_uart_out(UART_MCR, 0x3);
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/* Clear & enable FIFOs */
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udbg_uart_out(UART_FCR, 0x7);
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}
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unsigned int udbg_probe_uart_speed(unsigned int clock)
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{
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unsigned int dll, dlm, divisor, prescaler, speed;
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u8 old_lcr;
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old_lcr = udbg_uart_in(UART_LCR);
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/* select divisor latch registers. */
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udbg_uart_out(UART_LCR, old_lcr | LCR_DLAB);
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/* now, read the divisor */
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dll = udbg_uart_in(UART_DLL);
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dlm = udbg_uart_in(UART_DLM);
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divisor = dlm << 8 | dll;
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/* check prescaling */
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if (udbg_uart_in(UART_MCR) & 0x80)
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prescaler = 4;
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else
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prescaler = 1;
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/* restore the LCR */
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udbg_uart_out(UART_LCR, old_lcr);
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/* calculate speed */
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speed = (clock / prescaler) / (divisor * 16);
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/* sanity check */
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if (speed > (clock / 16))
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speed = 9600;
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return speed;
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}
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static union {
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unsigned char __iomem *mmio_base;
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unsigned long pio_base;
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} udbg_uart;
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static unsigned int udbg_uart_stride = 1;
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static u8 udbg_uart_in_pio(unsigned int reg)
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{
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return inb(udbg_uart.pio_base + (reg * udbg_uart_stride));
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}
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static void udbg_uart_out_pio(unsigned int reg, u8 data)
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{
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outb(data, udbg_uart.pio_base + (reg * udbg_uart_stride));
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}
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void udbg_uart_init_pio(unsigned long port, unsigned int stride)
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{
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if (!port)
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return;
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udbg_uart.pio_base = port;
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udbg_uart_stride = stride;
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udbg_uart_in = udbg_uart_in_pio;
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udbg_uart_out = udbg_uart_out_pio;
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udbg_use_uart();
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}
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static u8 udbg_uart_in_mmio(unsigned int reg)
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{
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return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride));
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}
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static void udbg_uart_out_mmio(unsigned int reg, u8 data)
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{
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out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data);
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}
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void udbg_uart_init_mmio(void __iomem *addr, unsigned int stride)
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{
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if (!addr)
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return;
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udbg_uart.mmio_base = addr;
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udbg_uart_stride = stride;
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udbg_uart_in = udbg_uart_in_mmio;
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udbg_uart_out = udbg_uart_out_mmio;
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udbg_use_uart();
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}
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#ifdef CONFIG_PPC_MAPLE
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#define UDBG_UART_MAPLE_ADDR ((void __iomem *)0xf40003f8)
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static u8 udbg_uart_in_maple(unsigned int reg)
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{
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return real_readb(UDBG_UART_MAPLE_ADDR + reg);
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}
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static void udbg_uart_out_maple(unsigned int reg, u8 val)
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{
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real_writeb(val, UDBG_UART_MAPLE_ADDR + reg);
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}
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void __init udbg_init_maple_realmode(void)
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{
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udbg_uart_in = udbg_uart_in_maple;
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udbg_uart_out = udbg_uart_out_maple;
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udbg_use_uart();
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}
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#endif /* CONFIG_PPC_MAPLE */
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#ifdef CONFIG_PPC_PASEMI
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#define UDBG_UART_PAS_ADDR ((void __iomem *)0xfcff03f8UL)
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static u8 udbg_uart_in_pas(unsigned int reg)
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{
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return real_205_readb(UDBG_UART_PAS_ADDR + reg);
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}
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static void udbg_uart_out_pas(unsigned int reg, u8 val)
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{
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real_205_writeb(val, UDBG_UART_PAS_ADDR + reg);
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}
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void __init udbg_init_pas_realmode(void)
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{
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udbg_uart_in = udbg_uart_in_pas;
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udbg_uart_out = udbg_uart_out_pas;
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udbg_use_uart();
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}
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#endif /* CONFIG_PPC_PASEMI */
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#ifdef CONFIG_PPC_EARLY_DEBUG_44x
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#include <platforms/44x/44x.h>
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static u8 udbg_uart_in_44x_as1(unsigned int reg)
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{
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return as1_readb((void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg);
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}
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static void udbg_uart_out_44x_as1(unsigned int reg, u8 val)
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{
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as1_writeb(val, (void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg);
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}
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void __init udbg_init_44x_as1(void)
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{
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udbg_uart_in = udbg_uart_in_44x_as1;
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udbg_uart_out = udbg_uart_out_44x_as1;
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udbg_use_uart();
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}
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#endif /* CONFIG_PPC_EARLY_DEBUG_44x */
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#ifdef CONFIG_PPC_EARLY_DEBUG_40x
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static u8 udbg_uart_in_40x(unsigned int reg)
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{
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return real_readb((void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR
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+ reg);
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}
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static void udbg_uart_out_40x(unsigned int reg, u8 val)
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{
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real_writeb(val, (void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR
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+ reg);
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}
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void __init udbg_init_40x_realmode(void)
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{
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udbg_uart_in = udbg_uart_in_40x;
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udbg_uart_out = udbg_uart_out_40x;
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udbg_use_uart();
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}
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#endif /* CONFIG_PPC_EARLY_DEBUG_40x */
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