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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
332
arch/powerpc/mm/slb.c
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332
arch/powerpc/mm/slb.c
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/*
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* PowerPC64 SLB support.
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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* Based on earlier code written by:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/paca.h>
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#include <asm/cputable.h>
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#include <asm/cacheflush.h>
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#include <asm/smp.h>
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#include <linux/compiler.h>
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#include <asm/udbg.h>
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#include <asm/code-patching.h>
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extern void slb_allocate_realmode(unsigned long ea);
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extern void slb_allocate_user(unsigned long ea);
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static void slb_allocate(unsigned long ea)
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{
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/* Currently, we do real mode for all SLBs including user, but
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* that will change if we bring back dynamic VSIDs
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*/
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slb_allocate_realmode(ea);
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}
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#define slb_esid_mask(ssize) \
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(((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
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static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
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unsigned long slot)
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{
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return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | slot;
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}
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static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
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unsigned long flags)
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{
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return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
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((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
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}
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static inline void slb_shadow_update(unsigned long ea, int ssize,
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unsigned long flags,
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unsigned long entry)
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{
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/*
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* Clear the ESID first so the entry is not valid while we are
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* updating it. No write barriers are needed here, provided
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* we only update the current CPU's SLB shadow buffer.
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*/
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get_slb_shadow()->save_area[entry].esid = 0;
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get_slb_shadow()->save_area[entry].vsid =
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cpu_to_be64(mk_vsid_data(ea, ssize, flags));
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get_slb_shadow()->save_area[entry].esid =
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cpu_to_be64(mk_esid_data(ea, ssize, entry));
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}
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static inline void slb_shadow_clear(unsigned long entry)
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{
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get_slb_shadow()->save_area[entry].esid = 0;
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}
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static inline void create_shadowed_slbe(unsigned long ea, int ssize,
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unsigned long flags,
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unsigned long entry)
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{
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/*
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* Updating the shadow buffer before writing the SLB ensures
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* we don't get a stale entry here if we get preempted by PHYP
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* between these two statements.
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*/
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slb_shadow_update(ea, ssize, flags, entry);
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asm volatile("slbmte %0,%1" :
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: "r" (mk_vsid_data(ea, ssize, flags)),
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"r" (mk_esid_data(ea, ssize, entry))
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: "memory" );
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}
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static void __slb_flush_and_rebolt(void)
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{
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/* If you change this make sure you change SLB_NUM_BOLTED
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* and PR KVM appropriately too. */
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unsigned long linear_llp, vmalloc_llp, lflags, vflags;
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unsigned long ksp_esid_data, ksp_vsid_data;
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linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
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vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
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lflags = SLB_VSID_KERNEL | linear_llp;
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vflags = SLB_VSID_KERNEL | vmalloc_llp;
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ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, 2);
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if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) {
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ksp_esid_data &= ~SLB_ESID_V;
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ksp_vsid_data = 0;
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slb_shadow_clear(2);
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} else {
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/* Update stack entry; others don't change */
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slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, 2);
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ksp_vsid_data =
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be64_to_cpu(get_slb_shadow()->save_area[2].vsid);
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}
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/* We need to do this all in asm, so we're sure we don't touch
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* the stack between the slbia and rebolting it. */
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asm volatile("isync\n"
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"slbia\n"
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/* Slot 1 - first VMALLOC segment */
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"slbmte %0,%1\n"
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/* Slot 2 - kernel stack */
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"slbmte %2,%3\n"
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"isync"
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:: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)),
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"r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, 1)),
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"r"(ksp_vsid_data),
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"r"(ksp_esid_data)
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: "memory");
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}
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void slb_flush_and_rebolt(void)
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{
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WARN_ON(!irqs_disabled());
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/*
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* We can't take a PMU exception in the following code, so hard
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* disable interrupts.
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*/
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hard_irq_disable();
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__slb_flush_and_rebolt();
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get_paca()->slb_cache_ptr = 0;
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}
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void slb_vmalloc_update(void)
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{
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unsigned long vflags;
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vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
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slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, 1);
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slb_flush_and_rebolt();
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}
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/* Helper function to compare esids. There are four cases to handle.
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* 1. The system is not 1T segment size capable. Use the GET_ESID compare.
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* 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare.
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* 3. The system is 1T capable, only one of the two addresses is > 1T. This is not a match.
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* 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare.
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*/
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static inline int esids_match(unsigned long addr1, unsigned long addr2)
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{
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int esid_1t_count;
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/* System is not 1T segment size capable. */
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if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
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return (GET_ESID(addr1) == GET_ESID(addr2));
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esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
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((addr2 >> SID_SHIFT_1T) != 0));
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/* both addresses are < 1T */
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if (esid_1t_count == 0)
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return (GET_ESID(addr1) == GET_ESID(addr2));
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/* One address < 1T, the other > 1T. Not a match */
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if (esid_1t_count == 1)
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return 0;
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/* Both addresses are > 1T. */
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return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2));
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}
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/* Flush all user entries from the segment table of the current processor. */
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void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
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{
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unsigned long offset;
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unsigned long slbie_data = 0;
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unsigned long pc = KSTK_EIP(tsk);
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unsigned long stack = KSTK_ESP(tsk);
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unsigned long exec_base;
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/*
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* We need interrupts hard-disabled here, not just soft-disabled,
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* so that a PMU interrupt can't occur, which might try to access
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* user memory (to get a stack trace) and possible cause an SLB miss
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* which would update the slb_cache/slb_cache_ptr fields in the PACA.
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*/
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hard_irq_disable();
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offset = get_paca()->slb_cache_ptr;
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if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
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offset <= SLB_CACHE_ENTRIES) {
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int i;
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asm volatile("isync" : : : "memory");
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for (i = 0; i < offset; i++) {
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slbie_data = (unsigned long)get_paca()->slb_cache[i]
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<< SID_SHIFT; /* EA */
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slbie_data |= user_segment_size(slbie_data)
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<< SLBIE_SSIZE_SHIFT;
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slbie_data |= SLBIE_C; /* C set for user addresses */
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asm volatile("slbie %0" : : "r" (slbie_data));
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}
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asm volatile("isync" : : : "memory");
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} else {
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__slb_flush_and_rebolt();
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}
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/* Workaround POWER5 < DD2.1 issue */
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if (offset == 1 || offset > SLB_CACHE_ENTRIES)
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asm volatile("slbie %0" : : "r" (slbie_data));
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get_paca()->slb_cache_ptr = 0;
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get_paca()->context = mm->context;
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/*
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* preload some userspace segments into the SLB.
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* Almost all 32 and 64bit PowerPC executables are linked at
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* 0x10000000 so it makes sense to preload this segment.
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*/
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exec_base = 0x10000000;
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if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
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is_kernel_addr(exec_base))
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return;
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slb_allocate(pc);
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if (!esids_match(pc, stack))
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slb_allocate(stack);
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if (!esids_match(pc, exec_base) &&
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!esids_match(stack, exec_base))
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slb_allocate(exec_base);
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}
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static inline void patch_slb_encoding(unsigned int *insn_addr,
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unsigned int immed)
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{
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int insn = (*insn_addr & 0xffff0000) | immed;
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patch_instruction(insn_addr, insn);
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}
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extern u32 slb_compare_rr_to_size[];
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extern u32 slb_miss_kernel_load_linear[];
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extern u32 slb_miss_kernel_load_io[];
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extern u32 slb_compare_rr_to_size[];
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extern u32 slb_miss_kernel_load_vmemmap[];
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void slb_set_size(u16 size)
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{
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if (mmu_slb_size == size)
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return;
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mmu_slb_size = size;
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patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
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}
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void slb_initialize(void)
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{
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unsigned long linear_llp, vmalloc_llp, io_llp;
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unsigned long lflags, vflags;
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static int slb_encoding_inited;
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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unsigned long vmemmap_llp;
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#endif
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/* Prepare our SLB miss handler based on our page size */
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linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
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io_llp = mmu_psize_defs[mmu_io_psize].sllp;
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vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
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get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
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#endif
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if (!slb_encoding_inited) {
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slb_encoding_inited = 1;
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patch_slb_encoding(slb_miss_kernel_load_linear,
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SLB_VSID_KERNEL | linear_llp);
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patch_slb_encoding(slb_miss_kernel_load_io,
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SLB_VSID_KERNEL | io_llp);
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patch_slb_encoding(slb_compare_rr_to_size,
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mmu_slb_size);
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pr_devel("SLB: linear LLP = %04lx\n", linear_llp);
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pr_devel("SLB: io LLP = %04lx\n", io_llp);
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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patch_slb_encoding(slb_miss_kernel_load_vmemmap,
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SLB_VSID_KERNEL | vmemmap_llp);
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pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
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#endif
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}
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get_paca()->stab_rr = SLB_NUM_BOLTED;
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lflags = SLB_VSID_KERNEL | linear_llp;
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vflags = SLB_VSID_KERNEL | vmalloc_llp;
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/* Invalidate the entire SLB (even slot 0) & all the ERATS */
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asm volatile("isync":::"memory");
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asm volatile("slbmte %0,%0"::"r" (0) : "memory");
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asm volatile("isync; slbia; isync":::"memory");
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create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, 0);
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create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, 1);
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/* For the boot cpu, we're running on the stack in init_thread_union,
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* which is in the first segment of the linear mapping, and also
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* get_paca()->kstack hasn't been initialized yet.
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* For secondary cpus, we need to bolt the kernel stack entry now.
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*/
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slb_shadow_clear(2);
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if (raw_smp_processor_id() != boot_cpuid &&
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(get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
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create_shadowed_slbe(get_paca()->kstack,
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mmu_kernel_ssize, lflags, 2);
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asm volatile("isync":::"memory");
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}
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