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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 00:55:37 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
239
arch/powerpc/platforms/52xx/efika.c
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239
arch/powerpc/platforms/52xx/efika.c
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/*
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* Efika 5K2 platform code
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* Some code really inspired from the lite5200b platform.
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*
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* Copyright (C) 2006 bplan GmbH
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <generated/utsrelease.h>
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#include <linux/pci.h>
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#include <linux/of.h>
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#include <asm/dma.h>
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#include <asm/prom.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/rtas.h>
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#include <asm/mpc52xx.h>
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#define EFIKA_PLATFORM_NAME "Efika"
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/* ------------------------------------------------------------------------ */
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/* PCI accesses thru RTAS */
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/* ------------------------------------------------------------------------ */
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#ifdef CONFIG_PCI
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/*
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* Access functions for PCI config space using RTAS calls.
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*/
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static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 * val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
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| (((bus->number - hose->first_busno) & 0xff) << 16)
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| (hose->global_number << 24);
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int ret = -1;
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int rval;
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rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
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*val = ret;
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return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int rtas_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
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| (((bus->number - hose->first_busno) & 0xff) << 16)
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| (hose->global_number << 24);
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int rval;
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rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
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addr, len, val);
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return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops rtas_pci_ops = {
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.read = rtas_read_config,
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.write = rtas_write_config,
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};
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static void __init efika_pcisetup(void)
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{
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const int *bus_range;
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int len;
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struct pci_controller *hose;
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struct device_node *root;
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struct device_node *pcictrl;
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root = of_find_node_by_path("/");
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if (root == NULL) {
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printk(KERN_WARNING EFIKA_PLATFORM_NAME
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": Unable to find the root node\n");
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return;
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}
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for (pcictrl = NULL;;) {
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pcictrl = of_get_next_child(root, pcictrl);
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if ((pcictrl == NULL) || (strcmp(pcictrl->name, "pci") == 0))
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break;
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}
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of_node_put(root);
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if (pcictrl == NULL) {
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printk(KERN_WARNING EFIKA_PLATFORM_NAME
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": Unable to find the PCI bridge node\n");
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return;
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}
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bus_range = of_get_property(pcictrl, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING EFIKA_PLATFORM_NAME
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": Can't get bus-range for %s\n", pcictrl->full_name);
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goto out_put;
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}
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if (bus_range[1] == bus_range[0])
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printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI bus %d",
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bus_range[0]);
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else
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printk(KERN_INFO EFIKA_PLATFORM_NAME ": PCI buses %d..%d",
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bus_range[0], bus_range[1]);
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printk(" controlled by %s\n", pcictrl->full_name);
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printk("\n");
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hose = pcibios_alloc_controller(pcictrl);
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if (!hose) {
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printk(KERN_WARNING EFIKA_PLATFORM_NAME
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": Can't allocate PCI controller structure for %s\n",
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pcictrl->full_name);
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goto out_put;
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}
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hose->first_busno = bus_range[0];
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hose->last_busno = bus_range[1];
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hose->ops = &rtas_pci_ops;
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pci_process_bridge_OF_ranges(hose, pcictrl, 0);
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return;
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out_put:
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of_node_put(pcictrl);
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}
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#else
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static void __init efika_pcisetup(void)
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{}
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#endif
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/* ------------------------------------------------------------------------ */
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/* Platform setup */
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/* ------------------------------------------------------------------------ */
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static void efika_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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const char *revision;
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const char *codegendescription;
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const char *codegenvendor;
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root = of_find_node_by_path("/");
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if (!root)
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return;
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revision = of_get_property(root, "revision", NULL);
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codegendescription = of_get_property(root, "CODEGEN,description", NULL);
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codegenvendor = of_get_property(root, "CODEGEN,vendor", NULL);
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if (codegendescription)
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seq_printf(m, "machine\t\t: %s\n", codegendescription);
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else
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seq_printf(m, "machine\t\t: Efika\n");
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if (revision)
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seq_printf(m, "revision\t: %s\n", revision);
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if (codegenvendor)
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seq_printf(m, "vendor\t\t: %s\n", codegenvendor);
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of_node_put(root);
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}
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#ifdef CONFIG_PM
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static void efika_suspend_prepare(void __iomem *mbar)
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{
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u8 pin = 4; /* GPIO_WKUP_4 (GPIO_PSC6_0 - IRDA_RX) */
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u8 level = 1; /* wakeup on high level */
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/* IOW. to wake it up, short pins 1 and 3 on IRDA connector */
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mpc52xx_set_wakeup_gpio(pin, level);
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}
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#endif
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static void __init efika_setup_arch(void)
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{
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rtas_initialize();
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/* Map important registers from the internal memory map */
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mpc52xx_map_common_devices();
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efika_pcisetup();
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#ifdef CONFIG_PM
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mpc52xx_suspend.board_suspend_prepare = efika_suspend_prepare;
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mpc52xx_pm_init();
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#endif
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if (ppc_md.progress)
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ppc_md.progress("Linux/PPC " UTS_RELEASE " running on Efika ;-)\n", 0x0);
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}
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static int __init efika_probe(void)
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{
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const char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
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"model", NULL);
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if (model == NULL)
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return 0;
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if (strcmp(model, "EFIKA5K2"))
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return 0;
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ISA_DMA_THRESHOLD = ~0L;
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DMA_MODE_READ = 0x44;
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DMA_MODE_WRITE = 0x48;
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return 1;
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}
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define_machine(efika)
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{
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.name = EFIKA_PLATFORM_NAME,
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.probe = efika_probe,
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.setup_arch = efika_setup_arch,
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.init = mpc52xx_declare_of_platform_devices,
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.show_cpuinfo = efika_show_cpuinfo,
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.init_IRQ = mpc52xx_init_irq,
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.get_irq = mpc52xx_get_irq,
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.restart = rtas_restart,
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.power_off = rtas_power_off,
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.halt = rtas_halt,
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.set_rtc_time = rtas_set_rtc_time,
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.get_rtc_time = rtas_get_rtc_time,
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.progress = rtas_progress,
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.get_boot_time = rtas_get_boot_time,
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.calibrate_decr = generic_calibrate_decr,
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#ifdef CONFIG_PCI
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.phys_mem_access_prot = pci_phys_mem_access_prot,
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#endif
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};
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