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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
245
arch/powerpc/sysdev/xics/ics-opal.c
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245
arch/powerpc/sysdev/xics/ics-opal.c
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/*
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* ICS backend for OPAL managed interrupts.
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*
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* Copyright 2011 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/spinlock.h>
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#include <linux/msi.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/errno.h>
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#include <asm/xics.h>
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#include <asm/opal.h>
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#include <asm/firmware.h>
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static int ics_opal_mangle_server(int server)
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{
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/* No link for now */
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return server << 2;
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}
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static int ics_opal_unmangle_server(int server)
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{
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/* No link for now */
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return server >> 2;
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}
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static void ics_opal_unmask_irq(struct irq_data *d)
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{
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unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
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int64_t rc;
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int server;
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pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
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if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
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return;
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server = xics_get_irq_server(d->irq, d->affinity, 0);
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server = ics_opal_mangle_server(server);
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rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
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if (rc != OPAL_SUCCESS)
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pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
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" error %lld\n",
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__func__, d->irq, hw_irq, server, rc);
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}
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static unsigned int ics_opal_startup(struct irq_data *d)
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{
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#ifdef CONFIG_PCI_MSI
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/*
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* The generic MSI code returns with the interrupt disabled on the
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* card, using the MSI mask bits. Firmware doesn't appear to unmask
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* at that level, so we do it here by hand.
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*/
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if (d->msi_desc)
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unmask_msi_irq(d);
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#endif
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/* unmask it */
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ics_opal_unmask_irq(d);
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return 0;
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}
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static void ics_opal_mask_real_irq(unsigned int hw_irq)
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{
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int server = ics_opal_mangle_server(xics_default_server);
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int64_t rc;
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if (hw_irq == XICS_IPI)
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return;
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/* Have to set XIVE to 0xff to be able to remove a slot */
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rc = opal_set_xive(hw_irq, server, 0xff);
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if (rc != OPAL_SUCCESS)
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pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
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__func__, hw_irq, rc);
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}
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static void ics_opal_mask_irq(struct irq_data *d)
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{
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unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
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pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
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if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
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return;
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ics_opal_mask_real_irq(hw_irq);
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}
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static int ics_opal_set_affinity(struct irq_data *d,
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const struct cpumask *cpumask,
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bool force)
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{
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unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
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__be16 oserver;
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int16_t server;
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int8_t priority;
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int64_t rc;
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int wanted_server;
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if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
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return -1;
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rc = opal_get_xive(hw_irq, &oserver, &priority);
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if (rc != OPAL_SUCCESS) {
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pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
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__func__, d->irq, hw_irq, rc);
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return -1;
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}
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server = be16_to_cpu(oserver);
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wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
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if (wanted_server < 0) {
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char cpulist[128];
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cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
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pr_warning("%s: No online cpus in the mask %s for irq %d\n",
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__func__, cpulist, d->irq);
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return -1;
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}
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server = ics_opal_mangle_server(wanted_server);
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pr_devel("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
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d->irq, hw_irq, wanted_server, server);
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rc = opal_set_xive(hw_irq, server, priority);
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if (rc != OPAL_SUCCESS) {
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pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
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" error %lld\n",
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__func__, d->irq, hw_irq, server, rc);
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return -1;
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}
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return IRQ_SET_MASK_OK;
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}
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static struct irq_chip ics_opal_irq_chip = {
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.name = "OPAL ICS",
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.irq_startup = ics_opal_startup,
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.irq_mask = ics_opal_mask_irq,
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.irq_unmask = ics_opal_unmask_irq,
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.irq_eoi = NULL, /* Patched at init time */
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.irq_set_affinity = ics_opal_set_affinity
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};
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static int ics_opal_map(struct ics *ics, unsigned int virq);
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static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec);
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static long ics_opal_get_server(struct ics *ics, unsigned long vec);
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static int ics_opal_host_match(struct ics *ics, struct device_node *node)
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{
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return 1;
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}
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/* Only one global & state struct ics */
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static struct ics ics_hal = {
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.map = ics_opal_map,
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.mask_unknown = ics_opal_mask_unknown,
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.get_server = ics_opal_get_server,
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.host_match = ics_opal_host_match,
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};
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static int ics_opal_map(struct ics *ics, unsigned int virq)
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{
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unsigned int hw_irq = (unsigned int)virq_to_hw(virq);
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int64_t rc;
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__be16 server;
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int8_t priority;
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if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
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return -EINVAL;
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/* Check if HAL knows about this interrupt */
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rc = opal_get_xive(hw_irq, &server, &priority);
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if (rc != OPAL_SUCCESS)
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return -ENXIO;
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irq_set_chip_and_handler(virq, &ics_opal_irq_chip, handle_fasteoi_irq);
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irq_set_chip_data(virq, &ics_hal);
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return 0;
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}
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static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
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{
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int64_t rc;
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__be16 server;
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int8_t priority;
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/* Check if HAL knows about this interrupt */
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rc = opal_get_xive(vec, &server, &priority);
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if (rc != OPAL_SUCCESS)
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return;
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ics_opal_mask_real_irq(vec);
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}
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static long ics_opal_get_server(struct ics *ics, unsigned long vec)
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{
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int64_t rc;
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__be16 server;
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int8_t priority;
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/* Check if HAL knows about this interrupt */
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rc = opal_get_xive(vec, &server, &priority);
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if (rc != OPAL_SUCCESS)
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return -1;
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return ics_opal_unmangle_server(be16_to_cpu(server));
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}
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int __init ics_opal_init(void)
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{
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if (!firmware_has_feature(FW_FEATURE_OPAL))
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return -ENODEV;
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/* We need to patch our irq chip's EOI to point to the
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* right ICP
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*/
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ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
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/* Register ourselves */
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xics_register_ics(&ics_hal);
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pr_info("ICS OPAL backend registered\n");
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return 0;
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}
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