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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
318
arch/s390/include/asm/rwsem.h
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318
arch/s390/include/asm/rwsem.h
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#ifndef _S390_RWSEM_H
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#define _S390_RWSEM_H
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/*
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* S390 version
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* Copyright IBM Corp. 2002
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Based on asm-alpha/semaphore.h and asm-i386/rwsem.h
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*/
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/*
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*
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* The MSW of the count is the negated number of active writers and waiting
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* lockers, and the LSW is the total number of active locks
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*
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* The lock count is initialized to 0 (no active and no waiting lockers).
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*
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* When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an
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* uncontended lock. This can be determined because XADD returns the old value.
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* Readers increment by 1 and see a positive value when uncontended, negative
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* if there are writers (and maybe) readers waiting (in which case it goes to
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* sleep).
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*
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* The value of WAITING_BIAS supports up to 32766 waiting processes. This can
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* be extended to 65534 by manually checking the whole MSW rather than relying
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* on the S flag.
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*
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* The value of ACTIVE_BIAS supports up to 65535 active processes.
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*
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* This should be totally fair - if anything is waiting, a process that wants a
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* lock will go to the back of the queue. When the currently active lock is
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* released, if there's a writer at the front of the queue, then that and only
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* that will be woken up; if there's a bunch of consequtive readers at the
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* front, then they'll all be woken up, but no other readers will be.
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*/
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#ifndef _LINUX_RWSEM_H
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#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
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#endif
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#ifndef CONFIG_64BIT
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#define RWSEM_UNLOCKED_VALUE 0x00000000
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#define RWSEM_ACTIVE_BIAS 0x00000001
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#define RWSEM_ACTIVE_MASK 0x0000ffff
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#define RWSEM_WAITING_BIAS (-0x00010000)
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#else /* CONFIG_64BIT */
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#define RWSEM_UNLOCKED_VALUE 0x0000000000000000L
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#define RWSEM_ACTIVE_BIAS 0x0000000000000001L
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#define RWSEM_ACTIVE_MASK 0x00000000ffffffffL
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#define RWSEM_WAITING_BIAS (-0x0000000100000000L)
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#endif /* CONFIG_64BIT */
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#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
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#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
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/*
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* lock for reading
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*/
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static inline void __down_read(struct rw_semaphore *sem)
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{
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signed long old, new;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: lr %1,%0\n"
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" ahi %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: lgr %1,%0\n"
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" aghi %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS)
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: "cc", "memory");
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if (old < 0)
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rwsem_down_read_failed(sem);
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}
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/*
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* trylock for reading -- returns 1 if successful, 0 if contention
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*/
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static inline int __down_read_trylock(struct rw_semaphore *sem)
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{
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signed long old, new;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: ltr %1,%0\n"
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" jm 1f\n"
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" ahi %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b\n"
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"1:"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: ltgr %1,%0\n"
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" jm 1f\n"
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" aghi %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b\n"
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"1:"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS)
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: "cc", "memory");
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return old >= 0 ? 1 : 0;
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}
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/*
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* lock for writing
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*/
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static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
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{
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signed long old, new, tmp;
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tmp = RWSEM_ACTIVE_WRITE_BIAS;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: lr %1,%0\n"
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" a %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: lgr %1,%0\n"
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" ag %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "m" (tmp)
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: "cc", "memory");
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if (old != 0)
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rwsem_down_write_failed(sem);
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}
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static inline void __down_write(struct rw_semaphore *sem)
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{
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__down_write_nested(sem, 0);
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}
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/*
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* trylock for writing -- returns 1 if successful, 0 if contention
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*/
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static inline int __down_write_trylock(struct rw_semaphore *sem)
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{
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signed long old;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%1\n"
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"0: ltr %0,%0\n"
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" jnz 1f\n"
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" cs %0,%3,%1\n"
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" jl 0b\n"
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#else /* CONFIG_64BIT */
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" lg %0,%1\n"
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"0: ltgr %0,%0\n"
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" jnz 1f\n"
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" csg %0,%3,%1\n"
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" jl 0b\n"
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#endif /* CONFIG_64BIT */
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"1:"
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: "=&d" (old), "=Q" (sem->count)
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: "Q" (sem->count), "d" (RWSEM_ACTIVE_WRITE_BIAS)
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: "cc", "memory");
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return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0;
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}
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/*
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* unlock after reading
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*/
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static inline void __up_read(struct rw_semaphore *sem)
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{
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signed long old, new;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: lr %1,%0\n"
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" ahi %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: lgr %1,%0\n"
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" aghi %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "i" (-RWSEM_ACTIVE_READ_BIAS)
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: "cc", "memory");
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if (new < 0)
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if ((new & RWSEM_ACTIVE_MASK) == 0)
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rwsem_wake(sem);
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}
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/*
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* unlock after writing
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*/
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static inline void __up_write(struct rw_semaphore *sem)
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{
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signed long old, new, tmp;
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tmp = -RWSEM_ACTIVE_WRITE_BIAS;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: lr %1,%0\n"
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" a %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: lgr %1,%0\n"
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" ag %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "m" (tmp)
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: "cc", "memory");
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if (new < 0)
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if ((new & RWSEM_ACTIVE_MASK) == 0)
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rwsem_wake(sem);
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}
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/*
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* downgrade write lock to read lock
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*/
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static inline void __downgrade_write(struct rw_semaphore *sem)
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{
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signed long old, new, tmp;
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tmp = -RWSEM_WAITING_BIAS;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: lr %1,%0\n"
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" a %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: lgr %1,%0\n"
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" ag %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "m" (tmp)
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: "cc", "memory");
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if (new > 1)
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rwsem_downgrade_wake(sem);
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}
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/*
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* implement atomic add functionality
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*/
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static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
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{
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signed long old, new;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: lr %1,%0\n"
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" ar %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: lgr %1,%0\n"
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" agr %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "d" (delta)
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: "cc", "memory");
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}
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/*
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* implement exchange and add functionality
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*/
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static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
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{
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signed long old, new;
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asm volatile(
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#ifndef CONFIG_64BIT
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" l %0,%2\n"
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"0: lr %1,%0\n"
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" ar %1,%4\n"
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" cs %0,%1,%2\n"
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" jl 0b"
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#else /* CONFIG_64BIT */
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" lg %0,%2\n"
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"0: lgr %1,%0\n"
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" agr %1,%4\n"
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" csg %0,%1,%2\n"
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" jl 0b"
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#endif /* CONFIG_64BIT */
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: "=&d" (old), "=&d" (new), "=Q" (sem->count)
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: "Q" (sem->count), "d" (delta)
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: "cc", "memory");
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return new;
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}
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#endif /* _S390_RWSEM_H */
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