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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 17:02:46 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
10
arch/sh/boards/mach-se/7722/Makefile
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10
arch/sh/boards/mach-se/7722/Makefile
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@ -0,0 +1,10 @@
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#
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# Makefile for the HITACHI UL SolutionEngine 7722 specific parts of the kernel
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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#
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obj-y := setup.o irq.o
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122
arch/sh/boards/mach-se/7722/irq.c
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122
arch/sh/boards/mach-se/7722/irq.c
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@ -0,0 +1,122 @@
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/*
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* Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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* Copyright (C) 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "SE7722-FPGA"
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#define pr_fmt(fmt) DRV_NAME ": " fmt
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#define irq_reg_readl ioread16
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#define irq_reg_writel iowrite16
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <asm/sizes.h>
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#include <mach-se/mach/se7722.h>
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#define IRQ01_BASE_ADDR 0x11800000
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#define IRQ01_MODE_REG 0
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#define IRQ01_STS_REG 4
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#define IRQ01_MASK_REG 8
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static void __iomem *se7722_irq_regs;
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struct irq_domain *se7722_irq_domain;
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static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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unsigned long mask;
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int bit;
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chip->irq_mask_ack(data);
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mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
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for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
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generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
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chip->irq_unmask(data);
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}
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static void __init se7722_domain_init(void)
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{
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int i;
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se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
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&irq_domain_simple_ops, NULL);
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if (unlikely(!se7722_irq_domain)) {
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printk("Failed to get IRQ domain\n");
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return;
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}
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for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
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int irq = irq_create_mapping(se7722_irq_domain, i);
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if (unlikely(irq == 0)) {
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printk("Failed to allocate IRQ %d\n", i);
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return;
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}
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}
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}
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static void __init se7722_gc_init(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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unsigned int irq_base;
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irq_base = irq_linear_revmap(se7722_irq_domain, 0);
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gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
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handle_level_irq);
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if (unlikely(!gc))
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return;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->regs.mask = IRQ01_MASK_REG;
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irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
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IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
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irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
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irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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}
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/*
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* Initialize FPGA IRQs
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*/
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void __init init_se7722_IRQ(void)
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{
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se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
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if (unlikely(!se7722_irq_regs)) {
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printk("Failed to remap IRQ01 regs\n");
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return;
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}
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/*
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* All FPGA IRQs disabled by default
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*/
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iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
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__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
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se7722_domain_init();
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se7722_gc_init();
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}
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194
arch/sh/boards/mach-se/7722/setup.c
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194
arch/sh/boards/mach-se/7722/setup.c
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/*
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* linux/arch/sh/boards/se/7722/setup.c
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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* Copyright (C) 2012 Paul Mundt
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*
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* Hitachi UL SolutionEngine 7722 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/ata_platform.h>
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#include <linux/input.h>
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#include <linux/input/sh_keysc.h>
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#include <linux/irqdomain.h>
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#include <linux/smc91x.h>
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#include <linux/sh_intc.h>
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#include <mach-se/mach/se7722.h>
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#include <mach-se/mach/mrshpc.h>
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#include <asm/machvec.h>
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#include <asm/clock.h>
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#include <asm/io.h>
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#include <asm/heartbeat.h>
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#include <cpu/sh7722.h>
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/* Heartbeat */
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static struct resource heartbeat_resource = {
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.start = PA_LED,
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.end = PA_LED,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
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};
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static struct platform_device heartbeat_device = {
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.name = "heartbeat",
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.id = -1,
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.num_resources = 1,
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.resource = &heartbeat_resource,
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};
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/* SMC91x */
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static struct smc91x_platdata smc91x_info = {
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.flags = SMC91X_USE_16BIT,
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};
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static struct resource smc91x_eth_resources[] = {
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[0] = {
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.name = "smc91x-regs" ,
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.start = PA_LAN + 0x300,
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.end = PA_LAN + 0x300 + 0x10 ,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* Filled in later */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_eth_device = {
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.name = "smc91x",
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.id = 0,
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.dev = {
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.dma_mask = NULL, /* don't use dma */
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &smc91x_info,
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},
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.num_resources = ARRAY_SIZE(smc91x_eth_resources),
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.resource = smc91x_eth_resources,
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};
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static struct resource cf_ide_resources[] = {
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[0] = {
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.start = PA_MRSHPC_IO + 0x1f0,
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.end = PA_MRSHPC_IO + 0x1f0 + 8 ,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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.start = PA_MRSHPC_IO + 0x1f0 + 0x206,
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.end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
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.flags = IORESOURCE_IO,
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},
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[2] = {
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/* Filled in later */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cf_ide_device = {
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.name = "pata_platform",
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.id = -1,
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.num_resources = ARRAY_SIZE(cf_ide_resources),
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.resource = cf_ide_resources,
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};
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static struct sh_keysc_info sh_keysc_info = {
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.mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */
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.scan_timing = 3,
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.delay = 5,
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.keycodes = { /* SW1 -> SW30 */
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KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
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KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
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KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
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KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T,
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KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y,
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KEY_Z,
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KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */
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},
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};
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static struct resource sh_keysc_resources[] = {
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[0] = {
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.start = 0x044b0000,
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.end = 0x044b000f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0xbe0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device sh_keysc_device = {
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.name = "sh_keysc",
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.id = 0, /* "keysc0" clock */
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.num_resources = ARRAY_SIZE(sh_keysc_resources),
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.resource = sh_keysc_resources,
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.dev = {
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.platform_data = &sh_keysc_info,
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},
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};
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static struct platform_device *se7722_devices[] __initdata = {
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&heartbeat_device,
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&smc91x_eth_device,
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&cf_ide_device,
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&sh_keysc_device,
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};
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static int __init se7722_devices_setup(void)
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{
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mrshpc_setup_windows();
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/* Wire-up dynamic vectors */
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cf_ide_resources[2].start = cf_ide_resources[2].end =
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irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_MRSHPC0);
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smc91x_eth_resources[1].start = smc91x_eth_resources[1].end =
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irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_SMC);
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return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices));
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}
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device_initcall(se7722_devices_setup);
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static void __init se7722_setup(char **cmdline_p)
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{
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__raw_writew(0x010D, FPGA_OUT); /* FPGA */
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__raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
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__raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
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/* LCDC I/O */
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__raw_writew(0x0020, PORT_PSELD);
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/* SIOF1*/
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__raw_writew(0x0003, PORT_PSELB);
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__raw_writew(0xe000, PORT_PSELC);
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__raw_writew(0x0000, PORT_PKCR);
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/* LCDC */
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__raw_writew(0x4020, PORT_PHCR);
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__raw_writew(0x0000, PORT_PLCR);
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__raw_writew(0x0000, PORT_PMCR);
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__raw_writew(0x0002, PORT_PRCR);
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__raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */
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/* KEYSC */
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__raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */
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__raw_writew(0x0000, PORT_PYCR);
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__raw_writew(0x0000, PORT_PZCR);
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__raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
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__raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
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}
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/*
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* The Machine Vector
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*/
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static struct sh_machine_vector mv_se7722 __initmv = {
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.mv_name = "Solution Engine 7722" ,
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.mv_setup = se7722_setup ,
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.mv_init_irq = init_se7722_IRQ,
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};
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