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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 00:28:51 +01:00
Fixed MTP to work with TWRP
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commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
162
arch/sh/drivers/pci/common.c
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162
arch/sh/drivers/pci/common.c
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/kernel.h>
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/*
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* These functions are used early on before PCI scanning is done
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* and all of the pci_dev and pci_bus structures have been created.
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*/
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static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
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int top_bus, int busnr, int devfn)
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{
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static struct pci_dev dev;
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static struct pci_bus bus;
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dev.bus = &bus;
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dev.sysdata = hose;
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dev.devfn = devfn;
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bus.number = busnr;
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bus.sysdata = hose;
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bus.ops = hose->pci_ops;
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if(busnr != top_bus)
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/* Fake a parent bus structure. */
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bus.parent = &bus;
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else
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bus.parent = NULL;
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return &dev;
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}
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#define EARLY_PCI_OP(rw, size, type) \
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int __init early_##rw##_config_##size(struct pci_channel *hose, \
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int top_bus, int bus, int devfn, int offset, type value) \
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{ \
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return pci_##rw##_config_##size( \
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fake_pci_dev(hose, top_bus, bus, devfn), \
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offset, value); \
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}
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EARLY_PCI_OP(read, byte, u8 *)
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EARLY_PCI_OP(read, word, u16 *)
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EARLY_PCI_OP(read, dword, u32 *)
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EARLY_PCI_OP(write, byte, u8)
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EARLY_PCI_OP(write, word, u16)
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EARLY_PCI_OP(write, dword, u32)
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int __init pci_is_66mhz_capable(struct pci_channel *hose,
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int top_bus, int current_bus)
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{
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u32 pci_devfn;
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unsigned short vid;
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int cap66 = -1;
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u16 stat;
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printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
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for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
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if (PCI_FUNC(pci_devfn))
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continue;
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if (early_read_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_VENDOR_ID, &vid) !=
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PCIBIOS_SUCCESSFUL)
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continue;
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if (vid == 0xffff)
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continue;
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/* check 66MHz capability */
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if (cap66 < 0)
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cap66 = 1;
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if (cap66) {
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early_read_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_STATUS, &stat);
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if (!(stat & PCI_STATUS_66MHZ)) {
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printk(KERN_DEBUG
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"PCI: %02x:%02x not 66MHz capable.\n",
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current_bus, pci_devfn);
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cap66 = 0;
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break;
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}
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}
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}
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return cap66 > 0;
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}
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static void pcibios_enable_err(unsigned long __data)
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{
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struct pci_channel *hose = (struct pci_channel *)__data;
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del_timer(&hose->err_timer);
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printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n");
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enable_irq(hose->err_irq);
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}
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static void pcibios_enable_serr(unsigned long __data)
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{
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struct pci_channel *hose = (struct pci_channel *)__data;
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del_timer(&hose->serr_timer);
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printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n");
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enable_irq(hose->serr_irq);
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}
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void pcibios_enable_timers(struct pci_channel *hose)
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{
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if (hose->err_irq) {
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init_timer(&hose->err_timer);
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hose->err_timer.data = (unsigned long)hose;
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hose->err_timer.function = pcibios_enable_err;
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}
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if (hose->serr_irq) {
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init_timer(&hose->serr_timer);
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hose->serr_timer.data = (unsigned long)hose;
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hose->serr_timer.function = pcibios_enable_serr;
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}
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}
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/*
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* A simple handler for the regular PCI status errors, called from IRQ
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* context.
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*/
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unsigned int pcibios_handle_status_errors(unsigned long addr,
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unsigned int status,
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struct pci_channel *hose)
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{
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unsigned int cmd = 0;
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if (status & PCI_STATUS_REC_MASTER_ABORT) {
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printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr);
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cmd |= PCI_STATUS_REC_MASTER_ABORT;
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}
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if (status & PCI_STATUS_REC_TARGET_ABORT) {
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printk(KERN_DEBUG "PCI: target abort: ");
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pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_MASTER_ABORT, 1);
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printk("\n");
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cmd |= PCI_STATUS_REC_TARGET_ABORT;
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}
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if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) {
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printk(KERN_DEBUG "PCI: parity error detected: ");
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pcibios_report_status(PCI_STATUS_PARITY |
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PCI_STATUS_DETECTED_PARITY, 1);
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printk("\n");
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cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY;
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/* Now back off of the IRQ for awhile */
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if (hose->err_irq) {
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disable_irq_nosync(hose->err_irq);
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hose->err_timer.expires = jiffies + HZ;
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add_timer(&hose->err_timer);
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}
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}
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return cmd;
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}
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