mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
28
arch/sh/include/cpu-sh3/cpu/adc.h
Normal file
28
arch/sh/include/cpu-sh3/cpu/adc.h
Normal file
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|
@ -0,0 +1,28 @@
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|||
#ifndef __ASM_CPU_SH3_ADC_H
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#define __ASM_CPU_SH3_ADC_H
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||||
|
||||
/*
|
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* Copyright (C) 2004 Andriy Skulysh
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||||
*/
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||||
|
||||
|
||||
#define ADDRAH 0xa4000080
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||||
#define ADDRAL 0xa4000082
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||||
#define ADDRBH 0xa4000084
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#define ADDRBL 0xa4000086
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#define ADDRCH 0xa4000088
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#define ADDRCL 0xa400008a
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#define ADDRDH 0xa400008c
|
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#define ADDRDL 0xa400008e
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#define ADCSR 0xa4000090
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|
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#define ADCSR_ADF 0x80
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#define ADCSR_ADIE 0x40
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#define ADCSR_ADST 0x20
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#define ADCSR_MULTI 0x10
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#define ADCSR_CKS 0x08
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#define ADCSR_CH_MASK 0x07
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|
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#define ADCR 0xa4000092
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#endif /* __ASM_CPU_SH3_ADC_H */
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43
arch/sh/include/cpu-sh3/cpu/cache.h
Normal file
43
arch/sh/include/cpu-sh3/cpu/cache.h
Normal file
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|
@ -0,0 +1,43 @@
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|||
/*
|
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* include/asm-sh/cpu-sh3/cache.h
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*
|
||||
* Copyright (C) 1999 Niibe Yutaka
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||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
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#ifndef __ASM_CPU_SH3_CACHE_H
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#define __ASM_CPU_SH3_CACHE_H
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|
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#define L1_CACHE_SHIFT 4
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|
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#define SH_CACHE_VALID 1
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#define SH_CACHE_UPDATED 2
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#define SH_CACHE_COMBINED 4
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#define SH_CACHE_ASSOC 8
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|
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#define SH_CCR 0xffffffec /* Address of Cache Control Register */
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|
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#define CCR_CACHE_CE 0x01 /* Cache Enable */
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#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
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#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
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#define CCR_CACHE_CF 0x08 /* Cache Flush */
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#define CCR_CACHE_ORA 0x20 /* RAM mode */
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#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_PHYSADDR_MASK 0x1ffffc00
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|
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#define CCR_CACHE_ENABLE CCR_CACHE_CE
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#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
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|
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
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defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define CCR3_REG 0xa40000b4
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#define CCR_CACHE_16KB 0x00010000
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#define CCR_CACHE_32KB 0x00020000
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#endif
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#endif /* __ASM_CPU_SH3_CACHE_H */
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41
arch/sh/include/cpu-sh3/cpu/dac.h
Normal file
41
arch/sh/include/cpu-sh3/cpu/dac.h
Normal file
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@ -0,0 +1,41 @@
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|||
#ifndef __ASM_CPU_SH3_DAC_H
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#define __ASM_CPU_SH3_DAC_H
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/*
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* Copyright (C) 2003 Andriy Skulysh
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*/
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#define DADR0 0xa40000a0
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#define DADR1 0xa40000a2
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#define DACR 0xa40000a4
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#define DACR_DAOE1 0x80
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#define DACR_DAOE0 0x40
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#define DACR_DAE 0x20
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static __inline__ void sh_dac_enable(int channel)
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{
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unsigned char v;
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v = __raw_readb(DACR);
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if(channel) v |= DACR_DAOE1;
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else v |= DACR_DAOE0;
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__raw_writeb(v,DACR);
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}
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static __inline__ void sh_dac_disable(int channel)
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{
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unsigned char v;
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v = __raw_readb(DACR);
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if(channel) v &= ~DACR_DAOE1;
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else v &= ~DACR_DAOE0;
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__raw_writeb(v,DACR);
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}
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static __inline__ void sh_dac_output(u8 value, int channel)
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{
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if(channel) __raw_writeb(value,DADR1);
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else __raw_writeb(value,DADR0);
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}
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#endif /* __ASM_CPU_SH3_DAC_H */
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41
arch/sh/include/cpu-sh3/cpu/dma-register.h
Normal file
41
arch/sh/include/cpu-sh3/cpu/dma-register.h
Normal file
|
|
@ -0,0 +1,41 @@
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|||
/*
|
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* SH3 CPU-specific DMA definitions, used by both DMA drivers
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*
|
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
|
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef CPU_DMA_REGISTER_H
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#define CPU_DMA_REGISTER_H
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#define CHCR_TS_LOW_MASK 0x18
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#define CHCR_TS_LOW_SHIFT 3
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#define CHCR_TS_HIGH_MASK 0
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#define CHCR_TS_HIGH_SHIFT 0
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#define DMAOR_INIT DMAOR_DME
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/*
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* The SuperH DMAC supports a number of transmit sizes, we list them here,
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* with their respective values as they appear in the CHCR registers.
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*/
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enum {
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XMIT_SZ_8BIT,
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XMIT_SZ_16BIT,
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XMIT_SZ_32BIT,
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XMIT_SZ_128BIT,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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#define TS_SHIFT { \
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[XMIT_SZ_8BIT] = 0, \
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[XMIT_SZ_16BIT] = 1, \
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[XMIT_SZ_32BIT] = 2, \
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[XMIT_SZ_128BIT] = 4, \
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}
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#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
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#endif
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18
arch/sh/include/cpu-sh3/cpu/dma.h
Normal file
18
arch/sh/include/cpu-sh3/cpu/dma.h
Normal file
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|
@ -0,0 +1,18 @@
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|||
#ifndef __ASM_CPU_SH3_DMA_H
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#define __ASM_CPU_SH3_DMA_H
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#include <linux/sh_intc.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7712)
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#define SH_DMAC_BASE0 0xa4010020
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#else /* SH7705/06/07/09 */
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#define SH_DMAC_BASE0 0xa4000020
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#endif
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#define DMTE0_IRQ evt2irq(0x800)
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#define DMTE4_IRQ evt2irq(0xb80)
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#endif /* __ASM_CPU_SH3_DMA_H */
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27
arch/sh/include/cpu-sh3/cpu/freq.h
Normal file
27
arch/sh/include/cpu-sh3/cpu/freq.h
Normal file
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@ -0,0 +1,27 @@
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|||
/*
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* include/asm-sh/cpu-sh3/freq.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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||||
*
|
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* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
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||||
* for more details.
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||||
*/
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#ifndef __ASM_CPU_SH3_FREQ_H
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#define __ASM_CPU_SH3_FREQ_H
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#ifdef CONFIG_CPU_SUBTYPE_SH7712
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#define FRQCR 0xA415FF80
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#else
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#define FRQCR 0xffffff80
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#endif
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#define MIN_DIVISOR_NR 0
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#define MAX_DIVISOR_NR 4
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#define FRQCR_CKOEN 0x0100
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#define FRQCR_PLLEN 0x0080
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#define FRQCR_PSTBY 0x0040
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#endif /* __ASM_CPU_SH3_FREQ_H */
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81
arch/sh/include/cpu-sh3/cpu/gpio.h
Normal file
81
arch/sh/include/cpu-sh3/cpu/gpio.h
Normal file
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@ -0,0 +1,81 @@
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/*
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* include/asm-sh/cpu-sh3/gpio.h
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*
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* Copyright (C) 2007 Markus Brunner, Mark Jonas
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||||
*
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* Addresses for the Pin Function Controller
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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||||
*/
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#ifndef _CPU_SH3_GPIO_H
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#define _CPU_SH3_GPIO_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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/* Control registers */
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#define PORT_PACR 0xA4050100UL
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#define PORT_PBCR 0xA4050102UL
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#define PORT_PCCR 0xA4050104UL
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#define PORT_PDCR 0xA4050106UL
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#define PORT_PECR 0xA4050108UL
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#define PORT_PFCR 0xA405010AUL
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#define PORT_PGCR 0xA405010CUL
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#define PORT_PHCR 0xA405010EUL
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#define PORT_PJCR 0xA4050110UL
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#define PORT_PKCR 0xA4050112UL
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#define PORT_PLCR 0xA4050114UL
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#define PORT_PMCR 0xA4050116UL
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#define PORT_PPCR 0xA4050118UL
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#define PORT_PRCR 0xA405011AUL
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#define PORT_PSCR 0xA405011CUL
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#define PORT_PTCR 0xA405011EUL
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#define PORT_PUCR 0xA4050120UL
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#define PORT_PVCR 0xA4050122UL
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/* Data registers */
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#define PORT_PADR 0xA4050140UL
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/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
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#define PORT_PBDR 0xA4050142UL
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#define PORT_PCDR 0xA4050144UL
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#define PORT_PDDR 0xA4050146UL
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#define PORT_PEDR 0xA4050148UL
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#define PORT_PFDR 0xA405014AUL
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#define PORT_PGDR 0xA405014CUL
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#define PORT_PHDR 0xA405014EUL
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#define PORT_PJDR 0xA4050150UL
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#define PORT_PKDR 0xA4050152UL
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#define PORT_PLDR 0xA4050154UL
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#define PORT_PMDR 0xA4050156UL
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#define PORT_PPDR 0xA4050158UL
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#define PORT_PRDR 0xA405015AUL
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#define PORT_PSDR 0xA405015CUL
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#define PORT_PTDR 0xA405015EUL
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#define PORT_PUDR 0xA4050160UL
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#define PORT_PVDR 0xA4050162UL
|
||||
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/* Pin Select Registers */
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#define PORT_PSELA 0xA4050124UL
|
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#define PORT_PSELB 0xA4050126UL
|
||||
#define PORT_PSELC 0xA4050128UL
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||||
#define PORT_PSELD 0xA405012AUL
|
||||
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
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||||
|
||||
/* Control registers */
|
||||
#define PORT_PACR 0xa4000100UL
|
||||
#define PORT_PBCR 0xa4000102UL
|
||||
#define PORT_PCCR 0xa4000104UL
|
||||
#define PORT_PFCR 0xa400010aUL
|
||||
|
||||
/* Data registers */
|
||||
#define PORT_PADR 0xa4000120UL
|
||||
#define PORT_PBDR 0xa4000122UL
|
||||
#define PORT_PCDR 0xa4000124UL
|
||||
#define PORT_PFDR 0xa400012aUL
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
45
arch/sh/include/cpu-sh3/cpu/mmu_context.h
Normal file
45
arch/sh/include/cpu-sh3/cpu/mmu_context.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* include/asm-sh/cpu-sh3/mmu_context.h
|
||||
*
|
||||
* Copyright (C) 1999 Niibe Yutaka
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
|
||||
#define __ASM_CPU_SH3_MMU_CONTEXT_H
|
||||
|
||||
#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
|
||||
#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
|
||||
#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
|
||||
#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
|
||||
|
||||
#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
|
||||
#define MMUCR_TI (1 << 2) /* TLB flush bit */
|
||||
|
||||
#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
|
||||
#define MMU_PAGE_ASSOC_BIT 0x80
|
||||
|
||||
#define MMU_NTLB_ENTRIES 128 /* for 7708 */
|
||||
#define MMU_NTLB_WAYS 4
|
||||
#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
|
||||
|
||||
#define TRA 0xffffffd0
|
||||
#define EXPEVT 0xffffffd4
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7712) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||
#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
|
||||
#else
|
||||
#define INTEVT 0xffffffd8
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
|
||||
|
||||
10
arch/sh/include/cpu-sh3/cpu/serial.h
Normal file
10
arch/sh/include/cpu-sh3/cpu/serial.h
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#ifndef __CPU_SH3_SERIAL_H
|
||||
#define __CPU_SH3_SERIAL_H
|
||||
|
||||
#include <linux/serial_sci.h>
|
||||
|
||||
extern struct plat_sci_port_ops sh770x_sci_port_ops;
|
||||
extern struct plat_sci_port_ops sh7710_sci_port_ops;
|
||||
extern struct plat_sci_port_ops sh7720_sci_port_ops;
|
||||
|
||||
#endif /* __CPU_SH3_SERIAL_H */
|
||||
174
arch/sh/include/cpu-sh3/cpu/sh7720.h
Normal file
174
arch/sh/include/cpu-sh3/cpu/sh7720.h
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
#ifndef __ASM_SH7720_H__
|
||||
#define __ASM_SH7720_H__
|
||||
|
||||
enum {
|
||||
/* PTA */
|
||||
GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
|
||||
GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
|
||||
|
||||
/* PTB */
|
||||
GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
|
||||
GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
|
||||
|
||||
/* PTC */
|
||||
GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
|
||||
GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
|
||||
|
||||
/* PTD */
|
||||
GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
|
||||
GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
|
||||
|
||||
/* PTE */
|
||||
GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, GPIO_PTE3,
|
||||
GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
|
||||
|
||||
/* PTF */
|
||||
GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3,
|
||||
GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, GPIO_PTG6,
|
||||
|
||||
/* PTG */
|
||||
GPIO_PTG5, GPIO_PTG4, GPIO_PTG3, GPIO_PTG2,
|
||||
GPIO_PTG1, GPIO_PTG0,
|
||||
|
||||
/* PTH */
|
||||
GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, GPIO_PTH3,
|
||||
GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
|
||||
|
||||
/* PTJ */
|
||||
GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, GPIO_PTJ3,
|
||||
GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
|
||||
|
||||
/* PTK */
|
||||
GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
|
||||
|
||||
/* PTL */
|
||||
GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, GPIO_PTL3,
|
||||
|
||||
/* PTM */
|
||||
GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
|
||||
GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
|
||||
|
||||
/* PTP */
|
||||
GPIO_PTP4, GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
|
||||
|
||||
/* PTR */
|
||||
GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
|
||||
GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
|
||||
|
||||
/* PTS */
|
||||
GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
|
||||
|
||||
/* PTT */
|
||||
GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
|
||||
|
||||
/* PTU */
|
||||
GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
|
||||
|
||||
/* PTV */
|
||||
GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
|
||||
|
||||
/* BSC */
|
||||
GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
|
||||
GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
|
||||
GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
|
||||
GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
|
||||
GPIO_FN_IOIS16, GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
|
||||
GPIO_FN_CS5B_CE1A, GPIO_FN_CS6B_CE1B,
|
||||
GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
|
||||
GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A0,
|
||||
GPIO_FN_REFOUT, GPIO_FN_IRQOUT,
|
||||
|
||||
/* LCDC */
|
||||
GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
|
||||
GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
|
||||
GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
|
||||
GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
|
||||
GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
|
||||
GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
|
||||
GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
|
||||
GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
|
||||
GPIO_FN_LCD_M_DISP,
|
||||
GPIO_FN_LCD_CL1, GPIO_FN_LCD_CL2,
|
||||
GPIO_FN_LCD_DON, GPIO_FN_LCD_FLM,
|
||||
GPIO_FN_LCD_VEPWC, GPIO_FN_LCD_VCPWC,
|
||||
|
||||
/* AFEIF */
|
||||
GPIO_FN_AFE_RXIN, GPIO_FN_AFE_RDET,
|
||||
GPIO_FN_AFE_FS, GPIO_FN_AFE_TXOUT,
|
||||
GPIO_FN_AFE_SCLK, GPIO_FN_AFE_RLYCNT,
|
||||
GPIO_FN_AFE_HC1,
|
||||
|
||||
/* IIC */
|
||||
GPIO_FN_IIC_SCL, GPIO_FN_IIC_SDA,
|
||||
|
||||
/* DAC */
|
||||
GPIO_FN_DA1, GPIO_FN_DA0,
|
||||
|
||||
/* ADC */
|
||||
GPIO_FN_AN3, GPIO_FN_AN2, GPIO_FN_AN1, GPIO_FN_AN0, GPIO_FN_ADTRG,
|
||||
|
||||
/* USB */
|
||||
GPIO_FN_USB1D_RCV, GPIO_FN_USB1D_TXSE0,
|
||||
GPIO_FN_USB1D_TXDPLS, GPIO_FN_USB1D_DMNS,
|
||||
GPIO_FN_USB1D_DPLS, GPIO_FN_USB1D_SPEED,
|
||||
GPIO_FN_USB1D_TXENL, GPIO_FN_USB2_PWR_EN,
|
||||
GPIO_FN_USB1_PWR_EN_USBF_UPLUP, GPIO_FN_USB1D_SUSPEND,
|
||||
|
||||
/* INTC */
|
||||
GPIO_FN_IRQ5, GPIO_FN_IRQ4,
|
||||
GPIO_FN_IRQ3_IRL3, GPIO_FN_IRQ2_IRL2,
|
||||
GPIO_FN_IRQ1_IRL1, GPIO_FN_IRQ0_IRL0,
|
||||
|
||||
/* PCC */
|
||||
GPIO_FN_PCC_REG, GPIO_FN_PCC_DRV,
|
||||
GPIO_FN_PCC_BVD2, GPIO_FN_PCC_BVD1,
|
||||
GPIO_FN_PCC_CD2, GPIO_FN_PCC_CD1,
|
||||
GPIO_FN_PCC_RESET, GPIO_FN_PCC_RDY,
|
||||
GPIO_FN_PCC_VS2, GPIO_FN_PCC_VS1,
|
||||
|
||||
/* HUDI */
|
||||
GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
|
||||
GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_ASEBRKAK, GPIO_FN_TRST,
|
||||
GPIO_FN_TMS, GPIO_FN_TDO, GPIO_FN_TDI, GPIO_FN_TCK,
|
||||
|
||||
/* DMAC */
|
||||
GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DACK0, GPIO_FN_DREQ0,
|
||||
GPIO_FN_TEND1, GPIO_FN_TEND0,
|
||||
|
||||
/* SIOF0 */
|
||||
GPIO_FN_SIOF0_SYNC, GPIO_FN_SIOF0_MCLK,
|
||||
GPIO_FN_SIOF0_TXD, GPIO_FN_SIOF0_RXD,
|
||||
GPIO_FN_SIOF0_SCK,
|
||||
|
||||
/* SIOF1 */
|
||||
GPIO_FN_SIOF1_SYNC, GPIO_FN_SIOF1_MCLK,
|
||||
GPIO_FN_SIOF1_TXD, GPIO_FN_SIOF1_RXD,
|
||||
GPIO_FN_SIOF1_SCK,
|
||||
|
||||
/* SCIF0 */
|
||||
GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD,
|
||||
GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_SCK,
|
||||
|
||||
/* SCIF1 */
|
||||
GPIO_FN_SCIF1_TXD, GPIO_FN_SCIF1_RXD,
|
||||
GPIO_FN_SCIF1_RTS, GPIO_FN_SCIF1_CTS, GPIO_FN_SCIF1_SCK,
|
||||
|
||||
/* TPU */
|
||||
GPIO_FN_TPU_TO1, GPIO_FN_TPU_TO0,
|
||||
GPIO_FN_TPU_TI3B, GPIO_FN_TPU_TI3A,
|
||||
GPIO_FN_TPU_TI2B, GPIO_FN_TPU_TI2A,
|
||||
GPIO_FN_TPU_TO3, GPIO_FN_TPU_TO2,
|
||||
|
||||
/* SIM */
|
||||
GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
|
||||
|
||||
/* MMC */
|
||||
GPIO_FN_MMC_DAT, GPIO_FN_MMC_CMD,
|
||||
GPIO_FN_MMC_CLK, GPIO_FN_MMC_VDDON,
|
||||
GPIO_FN_MMC_ODMOD,
|
||||
|
||||
/* SYSC */
|
||||
GPIO_FN_STATUS0, GPIO_FN_STATUS1,
|
||||
};
|
||||
|
||||
#endif /* __ASM_SH7720_H__ */
|
||||
25
arch/sh/include/cpu-sh3/cpu/watchdog.h
Normal file
25
arch/sh/include/cpu-sh3/cpu/watchdog.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* include/asm-sh/cpu-sh3/watchdog.h
|
||||
*
|
||||
* Copyright (C) 2002, 2003 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#ifndef __ASM_CPU_SH3_WATCHDOG_H
|
||||
#define __ASM_CPU_SH3_WATCHDOG_H
|
||||
|
||||
/* Register definitions */
|
||||
#define WTCNT 0xffffff84
|
||||
#define WTCSR 0xffffff86
|
||||
|
||||
/* Bit definitions */
|
||||
#define WTCSR_TME 0x80
|
||||
#define WTCSR_WT 0x40
|
||||
#define WTCSR_RSTS 0x20
|
||||
#define WTCSR_WOVF 0x10
|
||||
#define WTCSR_IOVF 0x08
|
||||
|
||||
#endif /* __ASM_CPU_SH3_WATCHDOG_H */
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue