mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
52
arch/sh/include/mach-se/mach/mrshpc.h
Normal file
52
arch/sh/include/mach-se/mach/mrshpc.h
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@ -0,0 +1,52 @@
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#ifndef __MACH_SE_MRSHPC_H
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#define __MACH_SE_MRSHPC_H
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#include <linux/io.h>
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static inline void __init mrshpc_setup_windows(void)
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{
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if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0)
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return; /* Not detected */
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if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) {
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__raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
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} else {
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__raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
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}
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/*
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* PC-Card window open
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* flag == COMMON/ATTRIBUTE/IO
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*/
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/* common window open */
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__raw_writew(0x8a84, MRSHPC_MW0CR1);
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if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0)
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/* common mode & bus width 16bit SWAP = 1*/
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__raw_writew(0x0b00, MRSHPC_MW0CR2);
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else
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/* common mode & bus width 16bit SWAP = 0*/
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__raw_writew(0x0300, MRSHPC_MW0CR2);
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/* attribute window open */
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__raw_writew(0x8a85, MRSHPC_MW1CR1);
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if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0)
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/* attribute mode & bus width 16bit SWAP = 1*/
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__raw_writew(0x0a00, MRSHPC_MW1CR2);
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else
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/* attribute mode & bus width 16bit SWAP = 0*/
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__raw_writew(0x0200, MRSHPC_MW1CR2);
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/* I/O window open */
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__raw_writew(0x8a86, MRSHPC_IOWCR1);
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__raw_writew(0x0008, MRSHPC_CDCR); /* I/O card mode */
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if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0)
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__raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
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else
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__raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/
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__raw_writew(0x2000, MRSHPC_ICR);
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__raw_writeb(0x00, PA_MRSHPC_MW2 + 0x206);
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__raw_writeb(0x42, PA_MRSHPC_MW2 + 0x200);
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}
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#endif /* __MACH_SE_MRSHPC_H */
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118
arch/sh/include/mach-se/mach/se.h
Normal file
118
arch/sh/include/mach-se/mach/se.h
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@ -0,0 +1,118 @@
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#ifndef __ASM_SH_HITACHI_SE_H
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#define __ASM_SH_HITACHI_SE_H
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/*
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* linux/include/asm-sh/hitachi_se.h
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* Hitachi SolutionEngine support
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*/
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#include <linux/sh_intc.h>
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/* Box specific addresses. */
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#define PA_ROM 0x00000000 /* EPROM */
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#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
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#define PA_FROM 0x01000000 /* EPROM */
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#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
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#define PA_EXT1 0x04000000
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#define PA_EXT1_SIZE 0x04000000
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#define PA_EXT2 0x08000000
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#define PA_EXT2_SIZE 0x04000000
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#define PA_SDRAM 0x0c000000
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#define PA_SDRAM_SIZE 0x04000000
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#define PA_EXT4 0x12000000
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#define PA_EXT4_SIZE 0x02000000
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#define PA_EXT5 0x14000000
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#define PA_EXT5_SIZE 0x04000000
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#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
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#define PA_83902 0xb0000000 /* DP83902A */
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#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
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#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
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#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
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#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
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#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
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#define PA_LED 0xb0c00000 /* LED */
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define PA_BCR 0xb0e00000
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#else
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#define PA_BCR 0xb1400000 /* FPGA */
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#endif
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#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
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#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
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#define MRSHPC_OPTION (PA_MRSHPC + 6)
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#define MRSHPC_CSR (PA_MRSHPC + 8)
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#define MRSHPC_ISR (PA_MRSHPC + 10)
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#define MRSHPC_ICR (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
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#define MRSHPC_CDCR (PA_MRSHPC + 28)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
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#define BCR_ILCRA (PA_BCR + 0)
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#define BCR_ILCRB (PA_BCR + 2)
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#define BCR_ILCRC (PA_BCR + 4)
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#define BCR_ILCRD (PA_BCR + 6)
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#define BCR_ILCRE (PA_BCR + 8)
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#define BCR_ILCRF (PA_BCR + 10)
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#define BCR_ILCRG (PA_BCR + 12)
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#if defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define INTC_IRR0 0xa4000004UL
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#define INTC_IRR1 0xa4000006UL
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#define INTC_IRR2 0xa4000008UL
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#define INTC_ICR0 0xfffffee0UL
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#define INTC_ICR1 0xa4000010UL
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#define INTC_ICR2 0xa4000012UL
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#define INTC_INTER 0xa4000014UL
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#define INTC_IPRC 0xa4000016UL
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#define INTC_IPRD 0xa4000018UL
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#define INTC_IPRE 0xa400001aUL
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#define IRQ0_IRQ evt2irq(0x600)
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#define IRQ1_IRQ evt2irq(0x620)
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define IRQ_STNIC evt2irq(0x380)
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#define IRQ_CFCARD evt2irq(0x3c0)
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#else
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#define IRQ_STNIC evt2irq(0x340)
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#define IRQ_CFCARD evt2irq(0x2e0)
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#endif
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/* SH Ether support (SH7710/SH7712) */
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/* Base address */
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#define SH_ETH0_BASE 0xA7000000
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#define SH_ETH1_BASE 0xA7000400
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/* PHY ID */
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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# define PHY_ID 0x00
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#elif defined(CONFIG_CPU_SUBTYPE_SH7712)
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# define PHY_ID 0x01
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#endif
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/* Ether IRQ */
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#define SH_ETH0_IRQ evt2irq(0xc00)
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#define SH_ETH1_IRQ evt2irq(0xc20)
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#define SH_TSU_IRQ evt2irq(0xc40)
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void init_se_IRQ(void);
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#define __IO_PREFIX se
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_HITACHI_SE_H */
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13
arch/sh/include/mach-se/mach/se7206.h
Normal file
13
arch/sh/include/mach-se/mach/se7206.h
Normal file
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@ -0,0 +1,13 @@
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#ifndef __ASM_SH_SE7206_H
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#define __ASM_SH_SE7206_H
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#define PA_SMSC 0x30000000
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#define PA_MRSHPC 0x34000000
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#define PA_LED 0x31400000
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void init_se7206_IRQ(void);
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#define __IO_PREFIX se7206
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_SE7206_H */
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142
arch/sh/include/mach-se/mach/se7343.h
Normal file
142
arch/sh/include/mach-se/mach/se7343.h
Normal file
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@ -0,0 +1,142 @@
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#ifndef __ASM_SH_HITACHI_SE7343_H
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#define __ASM_SH_HITACHI_SE7343_H
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/*
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* include/asm-sh/se/se7343.h
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*
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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*
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* SH-Mobile SolutionEngine 7343 support
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*/
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#include <linux/sh_intc.h>
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|
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/* Box specific addresses. */
|
||||
|
||||
/* Area 0 */
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#define PA_ROM 0x00000000 /* EPROM */
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#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
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#define PA_FROM 0x00400000 /* Flash ROM */
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#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
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#define PA_SRAM 0x00800000 /* SRAM */
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#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
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/* Area 1 */
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#define PA_EXT1 0x04000000
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#define PA_EXT1_SIZE 0x04000000
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/* Area 2 */
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#define PA_EXT2 0x08000000
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#define PA_EXT2_SIZE 0x04000000
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/* Area 3 */
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#define PA_SDRAM 0x0c000000
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#define PA_SDRAM_SIZE 0x04000000
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/* Area 4 */
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#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
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#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
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#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
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#define MRSHPC_OPTION (PA_MRSHPC + 6)
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#define MRSHPC_CSR (PA_MRSHPC + 8)
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#define MRSHPC_ISR (PA_MRSHPC + 10)
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#define MRSHPC_ICR (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
|
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#define MRSHPC_CDCR (PA_MRSHPC + 28)
|
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
|
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#define PA_LED 0xb0C00000 /* LED */
|
||||
#define LED_SHIFT 0
|
||||
#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
|
||||
/* Area 5 */
|
||||
#define PA_EXT5 0x14000000
|
||||
#define PA_EXT5_SIZE 0x04000000
|
||||
/* Area 6 */
|
||||
#define PA_LCD1 0xb8000000
|
||||
#define PA_LCD2 0xb8800000
|
||||
|
||||
#define PORT_PACR 0xA4050100
|
||||
#define PORT_PBCR 0xA4050102
|
||||
#define PORT_PCCR 0xA4050104
|
||||
#define PORT_PDCR 0xA4050106
|
||||
#define PORT_PECR 0xA4050108
|
||||
#define PORT_PFCR 0xA405010A
|
||||
#define PORT_PGCR 0xA405010C
|
||||
#define PORT_PHCR 0xA405010E
|
||||
#define PORT_PJCR 0xA4050110
|
||||
#define PORT_PKCR 0xA4050112
|
||||
#define PORT_PLCR 0xA4050114
|
||||
#define PORT_PMCR 0xA4050116
|
||||
#define PORT_PNCR 0xA4050118
|
||||
#define PORT_PQCR 0xA405011A
|
||||
#define PORT_PRCR 0xA405011C
|
||||
#define PORT_PSCR 0xA405011E
|
||||
#define PORT_PTCR 0xA4050140
|
||||
#define PORT_PUCR 0xA4050142
|
||||
#define PORT_PVCR 0xA4050144
|
||||
#define PORT_PWCR 0xA4050146
|
||||
#define PORT_PYCR 0xA4050148
|
||||
#define PORT_PZCR 0xA405014A
|
||||
|
||||
#define PORT_PSELA 0xA405014C
|
||||
#define PORT_PSELB 0xA405014E
|
||||
#define PORT_PSELC 0xA4050150
|
||||
#define PORT_PSELD 0xA4050152
|
||||
#define PORT_PSELE 0xA4050154
|
||||
|
||||
#define PORT_HIZCRA 0xA4050156
|
||||
#define PORT_HIZCRB 0xA4050158
|
||||
#define PORT_HIZCRC 0xA405015C
|
||||
|
||||
#define PORT_DRVCR 0xA4050180
|
||||
|
||||
#define PORT_PADR 0xA4050120
|
||||
#define PORT_PBDR 0xA4050122
|
||||
#define PORT_PCDR 0xA4050124
|
||||
#define PORT_PDDR 0xA4050126
|
||||
#define PORT_PEDR 0xA4050128
|
||||
#define PORT_PFDR 0xA405012A
|
||||
#define PORT_PGDR 0xA405012C
|
||||
#define PORT_PHDR 0xA405012E
|
||||
#define PORT_PJDR 0xA4050130
|
||||
#define PORT_PKDR 0xA4050132
|
||||
#define PORT_PLDR 0xA4050134
|
||||
#define PORT_PMDR 0xA4050136
|
||||
#define PORT_PNDR 0xA4050138
|
||||
#define PORT_PQDR 0xA405013A
|
||||
#define PORT_PRDR 0xA405013C
|
||||
#define PORT_PTDR 0xA4050160
|
||||
#define PORT_PUDR 0xA4050162
|
||||
#define PORT_PVDR 0xA4050164
|
||||
#define PORT_PWDR 0xA4050166
|
||||
#define PORT_PYDR 0xA4050168
|
||||
|
||||
#define FPGA_IN 0xb1400000
|
||||
#define FPGA_OUT 0xb1400002
|
||||
|
||||
#define IRQ0_IRQ evt2irq(0x600)
|
||||
#define IRQ1_IRQ evt2irq(0x620)
|
||||
#define IRQ4_IRQ evt2irq(0x680)
|
||||
#define IRQ5_IRQ evt2irq(0x6a0)
|
||||
|
||||
#define SE7343_FPGA_IRQ_MRSHPC0 0
|
||||
#define SE7343_FPGA_IRQ_MRSHPC1 1
|
||||
#define SE7343_FPGA_IRQ_MRSHPC2 2
|
||||
#define SE7343_FPGA_IRQ_MRSHPC3 3
|
||||
#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */
|
||||
#define SE7343_FPGA_IRQ_USB 8
|
||||
#define SE7343_FPGA_IRQ_UARTA 10
|
||||
#define SE7343_FPGA_IRQ_UARTB 11
|
||||
|
||||
#define SE7343_FPGA_IRQ_NR 12
|
||||
|
||||
struct irq_domain;
|
||||
|
||||
/* arch/sh/boards/se/7343/irq.c */
|
||||
extern struct irq_domain *se7343_irq_domain;
|
||||
|
||||
void init_7343se_IRQ(void);
|
||||
|
||||
#endif /* __ASM_SH_HITACHI_SE7343_H */
|
||||
72
arch/sh/include/mach-se/mach/se7721.h
Normal file
72
arch/sh/include/mach-se/mach/se7721.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Renesas Solutions Corp.
|
||||
*
|
||||
* Hitachi UL SolutionEngine 7721 Support.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_SH_SE7721_H
|
||||
#define __ASM_SH_SE7721_H
|
||||
|
||||
#include <linux/sh_intc.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
/* Box specific addresses. */
|
||||
#define SE_AREA0_WIDTH 2 /* Area0: 32bit */
|
||||
#define PA_ROM 0xa0000000 /* EPROM */
|
||||
#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
|
||||
#define PA_FROM 0xa1000000 /* Flash-ROM */
|
||||
#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
|
||||
#define PA_EXT1 0xa4000000
|
||||
#define PA_EXT1_SIZE 0x04000000
|
||||
#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
|
||||
#define PA_SDRAM_SIZE 0x04000000
|
||||
|
||||
#define PA_EXT4 0xb0000000
|
||||
#define PA_EXT4_SIZE 0x04000000
|
||||
|
||||
#define PA_PERIPHERAL 0xB8000000
|
||||
|
||||
#define PA_PCIC PA_PERIPHERAL
|
||||
#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0)
|
||||
#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000)
|
||||
#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000)
|
||||
#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000)
|
||||
#define MRSHPC_OPTION (PA_MRSHPC + 6)
|
||||
#define MRSHPC_CSR (PA_MRSHPC + 8)
|
||||
#define MRSHPC_ISR (PA_MRSHPC + 10)
|
||||
#define MRSHPC_ICR (PA_MRSHPC + 12)
|
||||
#define MRSHPC_CPWCR (PA_MRSHPC + 14)
|
||||
#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
|
||||
#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
|
||||
#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
|
||||
#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
|
||||
#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
|
||||
#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
|
||||
#define MRSHPC_CDCR (PA_MRSHPC + 28)
|
||||
#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
|
||||
|
||||
#define PA_LED 0xB6800000 /* 8bit LED */
|
||||
#define PA_FPGA 0xB7000000 /* FPGA base address */
|
||||
|
||||
#define MRSHPC_IRQ0 evt2irq(0x340)
|
||||
|
||||
#define FPGA_ILSR1 (PA_FPGA + 0x02)
|
||||
#define FPGA_ILSR2 (PA_FPGA + 0x03)
|
||||
#define FPGA_ILSR3 (PA_FPGA + 0x04)
|
||||
#define FPGA_ILSR4 (PA_FPGA + 0x05)
|
||||
#define FPGA_ILSR5 (PA_FPGA + 0x06)
|
||||
#define FPGA_ILSR6 (PA_FPGA + 0x07)
|
||||
#define FPGA_ILSR7 (PA_FPGA + 0x08)
|
||||
#define FPGA_ILSR8 (PA_FPGA + 0x09)
|
||||
|
||||
void init_se7721_IRQ(void);
|
||||
|
||||
#define __IO_PREFIX se7721
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_SE7721_H */
|
||||
102
arch/sh/include/mach-se/mach/se7722.h
Normal file
102
arch/sh/include/mach-se/mach/se7722.h
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
#ifndef __ASM_SH_SE7722_H
|
||||
#define __ASM_SH_SE7722_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/se7722.h
|
||||
*
|
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu
|
||||
*
|
||||
* Hitachi UL SolutionEngine 7722 Support.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
*/
|
||||
#include <linux/sh_intc.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
/* Box specific addresses. */
|
||||
#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
|
||||
#define PA_ROM 0xa0000000 /* EPROM */
|
||||
#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
|
||||
#define PA_FROM 0xa1000000 /* Flash-ROM */
|
||||
#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
|
||||
#define PA_EXT1 0xa4000000
|
||||
#define PA_EXT1_SIZE 0x04000000
|
||||
#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
|
||||
#define PA_SDRAM_SIZE 0x04000000
|
||||
|
||||
#define PA_EXT4 0xb0000000
|
||||
#define PA_EXT4_SIZE 0x04000000
|
||||
|
||||
#define PA_PERIPHERAL 0xB0000000
|
||||
|
||||
#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
|
||||
#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
|
||||
#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
|
||||
#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
|
||||
#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */
|
||||
#define MRSHPC_OPTION (PA_MRSHPC + 6)
|
||||
#define MRSHPC_CSR (PA_MRSHPC + 8)
|
||||
#define MRSHPC_ISR (PA_MRSHPC + 10)
|
||||
#define MRSHPC_ICR (PA_MRSHPC + 12)
|
||||
#define MRSHPC_CPWCR (PA_MRSHPC + 14)
|
||||
#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
|
||||
#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
|
||||
#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
|
||||
#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
|
||||
#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
|
||||
#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
|
||||
#define MRSHPC_CDCR (PA_MRSHPC + 28)
|
||||
#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
|
||||
|
||||
#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
|
||||
#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
|
||||
|
||||
#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
|
||||
/* GPIO */
|
||||
#define FPGA_IN 0xb1840000UL
|
||||
#define FPGA_OUT 0xb1840004UL
|
||||
|
||||
#define PORT_PECR 0xA4050108UL
|
||||
#define PORT_PJCR 0xA4050110UL
|
||||
#define PORT_PSELD 0xA4050154UL
|
||||
#define PORT_PSELB 0xA4050150UL
|
||||
|
||||
#define PORT_PSELC 0xA4050152UL
|
||||
#define PORT_PKCR 0xA4050112UL
|
||||
#define PORT_PHCR 0xA405010EUL
|
||||
#define PORT_PLCR 0xA4050114UL
|
||||
#define PORT_PMCR 0xA4050116UL
|
||||
#define PORT_PRCR 0xA405011CUL
|
||||
#define PORT_PXCR 0xA4050148UL
|
||||
#define PORT_PSELA 0xA405014EUL
|
||||
#define PORT_PYCR 0xA405014AUL
|
||||
#define PORT_PZCR 0xA405014CUL
|
||||
#define PORT_HIZCRA 0xA4050158UL
|
||||
#define PORT_HIZCRC 0xA405015CUL
|
||||
|
||||
/* IRQ */
|
||||
#define IRQ0_IRQ evt2irq(0x600)
|
||||
#define IRQ1_IRQ evt2irq(0x620)
|
||||
|
||||
#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */
|
||||
#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */
|
||||
#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
|
||||
#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */
|
||||
#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */
|
||||
#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
|
||||
#define SE7722_FPGA_IRQ_NR 6
|
||||
|
||||
struct irq_domain;
|
||||
|
||||
/* arch/sh/boards/se/7722/irq.c */
|
||||
extern struct irq_domain *se7722_irq_domain;
|
||||
|
||||
void init_se7722_IRQ(void);
|
||||
|
||||
#define __IO_PREFIX se7722
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_SE7722_H */
|
||||
73
arch/sh/include/mach-se/mach/se7724.h
Normal file
73
arch/sh/include/mach-se/mach/se7724.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
#ifndef __ASM_SH_SE7724_H
|
||||
#define __ASM_SH_SE7724_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/se7724.h
|
||||
*
|
||||
* Copyright (C) 2009 Renesas Solutions Corp.
|
||||
*
|
||||
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
|
||||
*
|
||||
* Hitachi UL SolutionEngine 7724 Support.
|
||||
*
|
||||
* Based on se7722.h
|
||||
* Copyright (C) 2007 Nobuhiro Iwamatsu
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
*/
|
||||
#include <linux/sh_intc.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
/* SH Eth */
|
||||
#define SH_ETH_ADDR (0xA4600000)
|
||||
#define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
|
||||
#define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
|
||||
|
||||
#define PA_LED (0xba203000) /* 8bit LED */
|
||||
#define IRQ_MODE (0xba200010)
|
||||
#define IRQ0_SR (0xba200014)
|
||||
#define IRQ1_SR (0xba200018)
|
||||
#define IRQ2_SR (0xba20001c)
|
||||
#define IRQ0_MR (0xba200020)
|
||||
#define IRQ1_MR (0xba200024)
|
||||
#define IRQ2_MR (0xba200028)
|
||||
|
||||
/* IRQ */
|
||||
#define IRQ0_IRQ evt2irq(0x600)
|
||||
#define IRQ1_IRQ evt2irq(0x620)
|
||||
#define IRQ2_IRQ evt2irq(0x640)
|
||||
|
||||
/* Bits in IRQ012 registers */
|
||||
#define SE7724_FPGA_IRQ_BASE 220
|
||||
|
||||
/* IRQ0 */
|
||||
#define IRQ0_BASE SE7724_FPGA_IRQ_BASE
|
||||
#define IRQ0_KEY (IRQ0_BASE + 12)
|
||||
#define IRQ0_RMII (IRQ0_BASE + 13)
|
||||
#define IRQ0_SMC (IRQ0_BASE + 14)
|
||||
#define IRQ0_MASK 0x7fff
|
||||
#define IRQ0_END IRQ0_SMC
|
||||
/* IRQ1 */
|
||||
#define IRQ1_BASE (IRQ0_END + 1)
|
||||
#define IRQ1_TS (IRQ1_BASE + 0)
|
||||
#define IRQ1_MASK 0x0001
|
||||
#define IRQ1_END IRQ1_TS
|
||||
/* IRQ2 */
|
||||
#define IRQ2_BASE (IRQ1_END + 1)
|
||||
#define IRQ2_USB0 (IRQ1_BASE + 0)
|
||||
#define IRQ2_USB1 (IRQ1_BASE + 1)
|
||||
#define IRQ2_MASK 0x0003
|
||||
#define IRQ2_END IRQ2_USB1
|
||||
|
||||
#define SE7724_FPGA_IRQ_NR (IRQ2_END - IRQ0_BASE)
|
||||
|
||||
/* arch/sh/boards/se/7724/irq.c */
|
||||
void init_se7724_IRQ(void);
|
||||
|
||||
#define __IO_PREFIX se7724
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_SE7724_H */
|
||||
74
arch/sh/include/mach-se/mach/se7751.h
Normal file
74
arch/sh/include/mach-se/mach/se7751.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
#ifndef __ASM_SH_HITACHI_7751SE_H
|
||||
#define __ASM_SH_HITACHI_7751SE_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/hitachi_7751se.h
|
||||
*
|
||||
* Copyright (C) 2000 Kazumoto Kojima
|
||||
*
|
||||
* Hitachi SolutionEngine support
|
||||
|
||||
* Modified for 7751 Solution Engine by
|
||||
* Ian da Silva and Jeremy Siegel, 2001.
|
||||
*/
|
||||
#include <linux/sh_intc.h>
|
||||
|
||||
/* Box specific addresses. */
|
||||
|
||||
#define PA_ROM 0x00000000 /* EPROM */
|
||||
#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
|
||||
#define PA_FROM 0x01000000 /* EPROM */
|
||||
#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
|
||||
#define PA_EXT1 0x04000000
|
||||
#define PA_EXT1_SIZE 0x04000000
|
||||
#define PA_EXT2 0x08000000
|
||||
#define PA_EXT2_SIZE 0x04000000
|
||||
#define PA_SDRAM 0x0c000000
|
||||
#define PA_SDRAM_SIZE 0x04000000
|
||||
|
||||
#define PA_EXT4 0x12000000
|
||||
#define PA_EXT4_SIZE 0x02000000
|
||||
#define PA_EXT5 0x14000000
|
||||
#define PA_EXT5_SIZE 0x04000000
|
||||
#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
|
||||
|
||||
#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
|
||||
#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
|
||||
#define PA_LED 0xba000000 /* LED */
|
||||
#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
|
||||
|
||||
#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
|
||||
#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
|
||||
#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
|
||||
#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
|
||||
#define MRSHPC_MODE (PA_MRSHPC + 4)
|
||||
#define MRSHPC_OPTION (PA_MRSHPC + 6)
|
||||
#define MRSHPC_CSR (PA_MRSHPC + 8)
|
||||
#define MRSHPC_ISR (PA_MRSHPC + 10)
|
||||
#define MRSHPC_ICR (PA_MRSHPC + 12)
|
||||
#define MRSHPC_CPWCR (PA_MRSHPC + 14)
|
||||
#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
|
||||
#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
|
||||
#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
|
||||
#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
|
||||
#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
|
||||
#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
|
||||
#define MRSHPC_CDCR (PA_MRSHPC + 28)
|
||||
#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
|
||||
|
||||
#define BCR_ILCRA (PA_BCR + 0)
|
||||
#define BCR_ILCRB (PA_BCR + 2)
|
||||
#define BCR_ILCRC (PA_BCR + 4)
|
||||
#define BCR_ILCRD (PA_BCR + 6)
|
||||
#define BCR_ILCRE (PA_BCR + 8)
|
||||
#define BCR_ILCRF (PA_BCR + 10)
|
||||
#define BCR_ILCRG (PA_BCR + 12)
|
||||
|
||||
#define IRQ_79C973 evt2irq(0x3a0)
|
||||
|
||||
void init_7751se_IRQ(void);
|
||||
|
||||
#define __IO_PREFIX sh7751se
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_HITACHI_7751SE_H */
|
||||
109
arch/sh/include/mach-se/mach/se7780.h
Normal file
109
arch/sh/include/mach-se/mach/se7780.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
#ifndef __ASM_SH_SE7780_H
|
||||
#define __ASM_SH_SE7780_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/se7780.h
|
||||
*
|
||||
* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
|
||||
*
|
||||
* Hitachi UL SolutionEngine 7780 Support.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/sh_intc.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
/* Box specific addresses. */
|
||||
#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
|
||||
#define PA_ROM 0xa0000000 /* EPROM */
|
||||
#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
|
||||
#define PA_FROM 0xa1000000 /* Flash-ROM */
|
||||
#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
|
||||
#define PA_EXT1 0xa4000000
|
||||
#define PA_EXT1_SIZE 0x04000000
|
||||
#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */
|
||||
#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */
|
||||
#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
|
||||
#define PA_SDRAM_SIZE 0x08000000
|
||||
|
||||
#define PA_EXT4 0xb0000000
|
||||
#define PA_EXT4_SIZE 0x04000000
|
||||
#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */
|
||||
|
||||
#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */
|
||||
|
||||
#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */
|
||||
#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */
|
||||
#define DISP_CHAR_RAM (7 << 3)
|
||||
#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0)
|
||||
#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1)
|
||||
#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2)
|
||||
#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3)
|
||||
#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4)
|
||||
#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5)
|
||||
#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6)
|
||||
#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7)
|
||||
|
||||
#define DISP_UDC_RAM (5 << 3)
|
||||
#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
|
||||
|
||||
/* FPGA register address and bit */
|
||||
#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
|
||||
#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
|
||||
#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
|
||||
#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
|
||||
#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
|
||||
#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
|
||||
#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
|
||||
#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
|
||||
#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
|
||||
#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
|
||||
#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
|
||||
#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
|
||||
#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
|
||||
#define PA_LED FPGA_DBG_LED
|
||||
#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
|
||||
#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
|
||||
#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */
|
||||
|
||||
/* FPGA INTSEL position */
|
||||
/* INTSEL1 */
|
||||
#define IRQPOS_SMC91CX (0 * 4)
|
||||
#define IRQPOS_SM501 (1 * 4)
|
||||
/* INTSEL2 */
|
||||
#define IRQPOS_EXTINT1 (0 * 4)
|
||||
#define IRQPOS_EXTINT2 (1 * 4)
|
||||
#define IRQPOS_EXTINT3 (2 * 4)
|
||||
#define IRQPOS_EXTINT4 (3 * 4)
|
||||
/* INTSEL3 */
|
||||
#define IRQPOS_PCCPW (0 * 4)
|
||||
|
||||
/* IDE interrupt */
|
||||
#define IRQ_IDE0 evt2irq(0xa60) /* iVDR */
|
||||
|
||||
/* SMC interrupt */
|
||||
#define SMC_IRQ evt2irq(0x300)
|
||||
|
||||
/* SM501 interrupt */
|
||||
#define SM501_IRQ evt2irq(0x200)
|
||||
|
||||
/* interrupt pin */
|
||||
#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
|
||||
#define IRQPIN_EXTINT2 1 /* IRQ1 pin */
|
||||
#define IRQPIN_EXTINT3 2 /* IRQ2 pin */
|
||||
#define IRQPIN_SMC91CX 3 /* IRQ3 pin */
|
||||
#define IRQPIN_EXTINT4 4 /* IRQ4 pin */
|
||||
#define IRQPIN_PCC0 5 /* IRQ5 pin */
|
||||
#define IRQPIN_PCC2 6 /* IRQ6 pin */
|
||||
#define IRQPIN_SM501 7 /* IRQ7 pin */
|
||||
#define IRQPIN_PCCPW 7 /* IRQ7 pin */
|
||||
|
||||
/* arch/sh/boards/se/7780/irq.c */
|
||||
void init_se7780_IRQ(void);
|
||||
|
||||
#define __IO_PREFIX se7780
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_SE7780_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue