mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 07:38:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
6
arch/sh/kernel/cpu/irq/Makefile
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6
arch/sh/kernel/cpu/irq/Makefile
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@ -0,0 +1,6 @@
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#
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# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
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#
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obj-$(CONFIG_SUPERH32) += imask.o
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obj-$(CONFIG_CPU_SH5) += intc-sh5.o
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obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
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84
arch/sh/kernel/cpu/irq/imask.c
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84
arch/sh/kernel/cpu/irq/imask.c
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/*
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* arch/sh/kernel/cpu/irq/imask.c
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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*
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* Simple interrupt handling using IMASK of SR register.
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*
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*/
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/* NOTE: Will not work on level 15 */
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/spinlock.h>
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#include <linux/cache.h>
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#include <linux/irq.h>
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#include <linux/bitmap.h>
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#include <asm/irq.h>
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/* Bitmap of IRQ masked */
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#define IMASK_PRIORITY 15
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static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
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static int interrupt_priority;
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static inline void set_interrupt_registers(int ip)
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{
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unsigned long __dummy;
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asm volatile(
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#ifdef CONFIG_CPU_HAS_SR_RB
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"ldc %2, r6_bank\n\t"
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#endif
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"stc sr, %0\n\t"
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"and #0xf0, %0\n\t"
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"shlr2 %0\n\t"
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"cmp/eq #0x3c, %0\n\t"
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"bt/s 1f ! CLI-ed\n\t"
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" stc sr, %0\n\t"
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"and %1, %0\n\t"
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"or %2, %0\n\t"
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"ldc %0, sr\n"
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"1:"
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: "=&z" (__dummy)
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: "r" (~0xf0), "r" (ip << 4)
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: "t");
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}
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static void mask_imask_irq(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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clear_bit(irq, imask_mask);
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if (interrupt_priority < IMASK_PRIORITY - irq)
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interrupt_priority = IMASK_PRIORITY - irq;
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set_interrupt_registers(interrupt_priority);
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}
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static void unmask_imask_irq(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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set_bit(irq, imask_mask);
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interrupt_priority = IMASK_PRIORITY -
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find_first_zero_bit(imask_mask, IMASK_PRIORITY);
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set_interrupt_registers(interrupt_priority);
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}
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static struct irq_chip imask_irq_chip = {
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.name = "SR.IMASK",
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.irq_mask = mask_imask_irq,
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.irq_unmask = unmask_imask_irq,
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.irq_mask_ack = mask_imask_irq,
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};
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void make_imask_irq(unsigned int irq)
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{
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irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq,
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"level");
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}
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197
arch/sh/kernel/cpu/irq/intc-sh5.c
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197
arch/sh/kernel/cpu/irq/intc-sh5.c
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@ -0,0 +1,197 @@
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/*
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* arch/sh/kernel/cpu/irq/intc-sh5.c
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*
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* Interrupt Controller support for SH5 INTC.
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*
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* Copyright (C) 2000, 2001 Paolo Alberelli
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* Copyright (C) 2003 Paul Mundt
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*
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* Per-interrupt selective. IRLM=0 (Fixed priority) is not
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* supported being useless without a cascaded interrupt
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* controller.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <cpu/irq.h>
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#include <asm/page.h>
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/*
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* Maybe the generic Peripheral block could move to a more
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* generic include file. INTC Block will be defined here
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* and only here to make INTC self-contained in a single
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* file.
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*/
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#define INTC_BLOCK_OFFSET 0x01000000
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/* Base */
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#define INTC_BASE PHYS_PERIPHERAL_BLOCK + \
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INTC_BLOCK_OFFSET
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/* Address */
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#define INTC_ICR_SET (intc_virt + 0x0)
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#define INTC_ICR_CLEAR (intc_virt + 0x8)
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#define INTC_INTPRI_0 (intc_virt + 0x10)
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#define INTC_INTSRC_0 (intc_virt + 0x50)
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#define INTC_INTSRC_1 (intc_virt + 0x58)
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#define INTC_INTREQ_0 (intc_virt + 0x60)
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#define INTC_INTREQ_1 (intc_virt + 0x68)
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#define INTC_INTENB_0 (intc_virt + 0x70)
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#define INTC_INTENB_1 (intc_virt + 0x78)
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#define INTC_INTDSB_0 (intc_virt + 0x80)
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#define INTC_INTDSB_1 (intc_virt + 0x88)
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#define INTC_ICR_IRLM 0x1
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#define INTC_INTPRI_PREGS 8 /* 8 Priority Registers */
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#define INTC_INTPRI_PPREG 8 /* 8 Priorities per Register */
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/*
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* Mapper between the vector ordinal and the IRQ number
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* passed to kernel/device drivers.
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*/
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int intc_evt_to_irq[(0xE20/0x20)+1] = {
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0x000 - 0x0E0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0x100 - 0x1E0 */
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0, 0, 0, 0, 0, 1, 0, 0, /* 0x200 - 0x2E0 */
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2, 0, 0, 3, 0, 0, 0, -1, /* 0x300 - 0x3E0 */
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32, 33, 34, 35, 36, 37, 38, -1, /* 0x400 - 0x4E0 */
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-1, -1, -1, 63, -1, -1, -1, -1, /* 0x500 - 0x5E0 */
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-1, -1, 18, 19, 20, 21, 22, -1, /* 0x600 - 0x6E0 */
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39, 40, 41, 42, -1, -1, -1, -1, /* 0x700 - 0x7E0 */
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4, 5, 6, 7, -1, -1, -1, -1, /* 0x800 - 0x8E0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0x900 - 0x9E0 */
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12, 13, 14, 15, 16, 17, -1, -1, /* 0xA00 - 0xAE0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0xB00 - 0xBE0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0xC00 - 0xCE0 */
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-1, -1, -1, -1, -1, -1, -1, -1, /* 0xD00 - 0xDE0 */
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-1, -1 /* 0xE00 - 0xE20 */
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};
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static unsigned long intc_virt;
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static int irlm; /* IRL mode */
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static void enable_intc_irq(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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unsigned long reg;
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unsigned long bitmask;
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if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
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printk("Trying to use straight IRL0-3 with an encoding platform.\n");
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if (irq < 32) {
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reg = INTC_INTENB_0;
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bitmask = 1 << irq;
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} else {
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reg = INTC_INTENB_1;
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bitmask = 1 << (irq - 32);
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}
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__raw_writel(bitmask, reg);
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}
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static void disable_intc_irq(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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unsigned long reg;
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unsigned long bitmask;
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if (irq < 32) {
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reg = INTC_INTDSB_0;
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bitmask = 1 << irq;
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} else {
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reg = INTC_INTDSB_1;
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bitmask = 1 << (irq - 32);
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}
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__raw_writel(bitmask, reg);
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}
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static struct irq_chip intc_irq_type = {
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.name = "INTC",
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.irq_enable = enable_intc_irq,
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.irq_disable = disable_intc_irq,
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};
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void __init plat_irq_setup(void)
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{
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unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
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unsigned long reg;
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int i;
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intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
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if (!intc_virt) {
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panic("Unable to remap INTC\n");
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}
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/* Set default: per-line enable/disable, priority driven ack/eoi */
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for (i = 0; i < NR_INTC_IRQS; i++)
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irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
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/* Disable all interrupts and set all priorities to 0 to avoid trouble */
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__raw_writel(-1, INTC_INTDSB_0);
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__raw_writel(-1, INTC_INTDSB_1);
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for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
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__raw_writel( NO_PRIORITY, reg);
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#ifdef CONFIG_SH_CAYMAN
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{
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unsigned long data;
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/* Set IRLM */
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/* If all the priorities are set to 'no priority', then
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* assume we are using encoded mode.
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*/
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irlm = platform_int_priority[IRQ_IRL0] +
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platform_int_priority[IRQ_IRL1] +
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platform_int_priority[IRQ_IRL2] +
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platform_int_priority[IRQ_IRL3];
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if (irlm == NO_PRIORITY) {
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/* IRLM = 0 */
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reg = INTC_ICR_CLEAR;
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i = IRQ_INTA;
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printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
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} else {
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/* IRLM = 1 */
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reg = INTC_ICR_SET;
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i = IRQ_IRL0;
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}
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__raw_writel(INTC_ICR_IRLM, reg);
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/* Set interrupt priorities according to platform description */
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for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
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data |= platform_int_priority[i] <<
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((i % INTC_INTPRI_PPREG) * 4);
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if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
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/* Upon the 7th, set Priority Register */
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__raw_writel(data, reg);
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data = 0;
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reg += 8;
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}
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}
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}
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#endif
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/*
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* And now let interrupts come in.
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* sti() is not enough, we need to
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* lower priority, too.
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*/
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__asm__ __volatile__("getcon " __SR ", %0\n\t"
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"and %0, %1, %0\n\t"
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"putcon %0, " __SR "\n\t"
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: "=&r" (__dummy0)
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: "r" (__dummy1));
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}
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83
arch/sh/kernel/cpu/irq/ipr.c
Normal file
83
arch/sh/kernel/cpu/irq/ipr.c
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/*
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* Interrupt handling for IPR-based IRQ.
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2006 Paul Mundt
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*
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* Supported system:
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* On-chip supporting modules (TMU, RTC, etc.).
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* On-chip supporting modules for SH7709/SH7709A/SH7729.
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* Hitachi SolutionEngine external I/O:
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* MS7709SE01, MS7709ASE01, and MS7750SE01
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/topology.h>
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static inline struct ipr_desc *get_ipr_desc(struct irq_data *data)
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{
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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return container_of(chip, struct ipr_desc, chip);
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}
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static void disable_ipr_irq(struct irq_data *data)
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{
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struct ipr_data *p = irq_data_get_irq_chip_data(data);
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unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
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/* Set the priority in IPR to 0 */
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__raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
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(void)__raw_readw(addr); /* Read back to flush write posting */
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}
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static void enable_ipr_irq(struct irq_data *data)
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{
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struct ipr_data *p = irq_data_get_irq_chip_data(data);
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unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
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/* Set priority in IPR back to original value */
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__raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
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}
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/*
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* The shift value is now the number of bits to shift, not the number of
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* bits/4. This is to make it easier to read the value directly from the
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* datasheets. The IPR address is calculated using the ipr_offset table.
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*/
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void register_ipr_controller(struct ipr_desc *desc)
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{
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int i;
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desc->chip.irq_mask = disable_ipr_irq;
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desc->chip.irq_unmask = enable_ipr_irq;
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for (i = 0; i < desc->nr_irqs; i++) {
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struct ipr_data *p = desc->ipr_data + i;
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int res;
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BUG_ON(p->ipr_idx >= desc->nr_offsets);
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BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
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res = irq_alloc_desc_at(p->irq, numa_node_id());
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if (unlikely(res != p->irq && res != -EEXIST)) {
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printk(KERN_INFO "can not get irq_desc for %d\n",
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p->irq);
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continue;
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}
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disable_irq_nosync(p->irq);
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irq_set_chip_and_handler_name(p->irq, &desc->chip,
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handle_level_irq, "level");
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irq_set_chip_data(p->irq, p);
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disable_ipr_irq(irq_get_irq_data(p->irq));
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}
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}
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EXPORT_SYMBOL(register_ipr_controller);
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