mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-29 23:28:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
24
arch/sh/kernel/cpu/sh2a/Makefile
Normal file
24
arch/sh/kernel/cpu/sh2a/Makefile
Normal file
|
|
@ -0,0 +1,24 @@
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|||
#
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# Makefile for the Linux/SuperH SH-2A backends.
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#
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||||
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obj-y := common.o probe.o opcode_helper.o
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common-y += ex.o entry.o
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obj-$(CONFIG_SH_FPU) += fpu.o
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|
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obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7269) += setup-sh7269.o clock-sh7269.o
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obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
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# Pinmux setup
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
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pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o
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obj-$(CONFIG_GPIOLIB) += $(pinmux-y)
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85
arch/sh/kernel/cpu/sh2a/clock-sh7201.c
Normal file
85
arch/sh/kernel/cpu/sh2a/clock-sh7201.c
Normal file
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|
@ -0,0 +1,85 @@
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|||
/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7201.c
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*
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* SH7201 support for the clock framework
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*
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* Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
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*
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* Based on clock-sh4.c
|
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* Copyright (C) 2005 Paul Mundt
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*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static const int pll1rate[]={1,2,3,4,6,8};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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static unsigned int pll2_mult;
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static void master_clk_init(struct clk *clk)
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{
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clk->rate = 10000000 * pll2_mult *
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pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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static struct sh_clk_ops sh7201_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct sh_clk_ops sh7201_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct sh_clk_ops sh7201_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
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return clk->parent->rate / ifc_divisors[idx];
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}
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static struct sh_clk_ops sh7201_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct sh_clk_ops *sh7201_clk_ops[] = {
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&sh7201_master_clk_ops,
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&sh7201_module_clk_ops,
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&sh7201_bus_clk_ops,
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&sh7201_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
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{
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if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
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pll2_mult = 1;
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else if (test_mode_pin(MODE_PIN1))
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pll2_mult = 2;
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else
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pll2_mult = 4;
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if (idx < ARRAY_SIZE(sh7201_clk_ops))
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*ops = sh7201_clk_ops[idx];
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}
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81
arch/sh/kernel/cpu/sh2a/clock-sh7203.c
Normal file
81
arch/sh/kernel/cpu/sh2a/clock-sh7203.c
Normal file
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|
@ -0,0 +1,81 @@
|
|||
/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7203.c
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||||
*
|
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* SH7203 support for the clock framework
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*
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* Copyright (C) 2007 Kieran Bingham (MPC-Data Ltd)
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*
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* Based on clock-sh7263.c
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||||
* Copyright (C) 2006 Yoshinori Sato
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*
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* Based on clock-sh4.c
|
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* Copyright (C) 2005 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static const int pll1rate[]={8,12,16,0};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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static unsigned int pll2_mult;
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
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}
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static struct sh_clk_ops sh7203_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct sh_clk_ops sh7203_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / pfc_divisors[idx-2];
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}
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static struct sh_clk_ops sh7203_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static struct sh_clk_ops sh7203_cpu_clk_ops = {
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.recalc = followparent_recalc,
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};
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static struct sh_clk_ops *sh7203_clk_ops[] = {
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&sh7203_master_clk_ops,
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&sh7203_module_clk_ops,
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&sh7203_bus_clk_ops,
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&sh7203_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
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{
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if (test_mode_pin(MODE_PIN1))
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pll2_mult = 4;
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else if (test_mode_pin(MODE_PIN0))
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pll2_mult = 2;
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else
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pll2_mult = 1;
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if (idx < ARRAY_SIZE(sh7203_clk_ops))
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*ops = sh7203_clk_ops[idx];
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}
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83
arch/sh/kernel/cpu/sh2a/clock-sh7206.c
Normal file
83
arch/sh/kernel/cpu/sh2a/clock-sh7206.c
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7206.c
|
||||
*
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* SH7206 support for the clock framework
|
||||
*
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* Copyright (C) 2006 Yoshinori Sato
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*
|
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* Based on clock-sh4.c
|
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* Copyright (C) 2005 Paul Mundt
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||||
*
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||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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|
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static const int pll1rate[]={1,2,3,4,6,8};
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static const int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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static unsigned int pll2_mult;
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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static struct sh_clk_ops sh7206_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct sh_clk_ops sh7206_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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static struct sh_clk_ops sh7206_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(FREQCR) & 0x0007);
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return clk->parent->rate / ifc_divisors[idx];
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}
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static struct sh_clk_ops sh7206_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct sh_clk_ops *sh7206_clk_ops[] = {
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&sh7206_master_clk_ops,
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&sh7206_module_clk_ops,
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&sh7206_bus_clk_ops,
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&sh7206_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
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{
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if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
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pll2_mult = 1;
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else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
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pll2_mult = 2;
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else if (test_mode_pin(MODE_PIN1))
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pll2_mult = 4;
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if (idx < ARRAY_SIZE(sh7206_clk_ops))
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*ops = sh7206_clk_ops[idx];
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}
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153
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
Normal file
153
arch/sh/kernel/cpu/sh2a/clock-sh7264.c
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh2a/clock-sh7264.c
|
||||
*
|
||||
* SH7264 clock framework support
|
||||
*
|
||||
* Copyright (C) 2012 Phil Edworthy
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
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#include <linux/kernel.h>
|
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#include <linux/io.h>
|
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#include <linux/clkdev.h>
|
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#include <asm/clock.h>
|
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|
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/* SH7264 registers */
|
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#define FRQCR 0xfffe0010
|
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#define STBCR3 0xfffe0408
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#define STBCR4 0xfffe040c
|
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#define STBCR5 0xfffe0410
|
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#define STBCR6 0xfffe0414
|
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#define STBCR7 0xfffe0418
|
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#define STBCR8 0xfffe041c
|
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|
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static const unsigned int pll1rate[] = {8, 12};
|
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|
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static unsigned int pll1_div;
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC */
|
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static struct clk r_clk = {
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default rate for the root input clock, reset this with clk_set_rate()
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk extal_clk = {
|
||||
.rate = 18000000,
|
||||
};
|
||||
|
||||
static unsigned long pll_recalc(struct clk *clk)
|
||||
{
|
||||
unsigned long rate = clk->parent->rate / pll1_div;
|
||||
return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];
|
||||
}
|
||||
|
||||
static struct sh_clk_ops pll_clk_ops = {
|
||||
.recalc = pll_recalc,
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.ops = &pll_clk_ops,
|
||||
.parent = &extal_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
struct clk *main_clks[] = {
|
||||
&r_clk,
|
||||
&extal_clk,
|
||||
&pll_clk,
|
||||
};
|
||||
|
||||
static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = div2,
|
||||
.nr_divisors = ARRAY_SIZE(div2),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
enum { DIV4_I, DIV4_P,
|
||||
DIV4_NR };
|
||||
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
/* The mask field specifies the div2 entries that are valid */
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
|
||||
| CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
|
||||
};
|
||||
|
||||
enum { MSTP77, MSTP74, MSTP72,
|
||||
MSTP60,
|
||||
MSTP35, MSTP34, MSTP33, MSTP32, MSTP30,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
|
||||
[MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
|
||||
[MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
|
||||
[MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
|
||||
[MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
|
||||
[MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
|
||||
[MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
|
||||
[MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
|
||||
[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
|
||||
/* MSTP clocks */
|
||||
CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
|
||||
CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
|
||||
CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
|
||||
CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
|
||||
CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
|
||||
CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
|
||||
CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
|
||||
CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
|
||||
CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
if (test_mode_pin(MODE_PIN0)) {
|
||||
if (test_mode_pin(MODE_PIN1))
|
||||
pll1_div = 3;
|
||||
else
|
||||
pll1_div = 4;
|
||||
} else
|
||||
pll1_div = 1;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
184
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
Normal file
184
arch/sh/kernel/cpu/sh2a/clock-sh7269.c
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh2a/clock-sh7269.c
|
||||
*
|
||||
* SH7269 clock framework support
|
||||
*
|
||||
* Copyright (C) 2012 Phil Edworthy
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <asm/clock.h>
|
||||
|
||||
/* SH7269 registers */
|
||||
#define FRQCR 0xfffe0010
|
||||
#define STBCR3 0xfffe0408
|
||||
#define STBCR4 0xfffe040c
|
||||
#define STBCR5 0xfffe0410
|
||||
#define STBCR6 0xfffe0414
|
||||
#define STBCR7 0xfffe0418
|
||||
|
||||
#define PLL_RATE 20
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC */
|
||||
static struct clk r_clk = {
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default rate for the root input clock, reset this with clk_set_rate()
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk extal_clk = {
|
||||
.rate = 13340000,
|
||||
};
|
||||
|
||||
static unsigned long pll_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * PLL_RATE;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops pll_clk_ops = {
|
||||
.recalc = pll_recalc,
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.ops = &pll_clk_ops,
|
||||
.parent = &extal_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
static unsigned long peripheral0_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 8;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops peripheral0_clk_ops = {
|
||||
.recalc = peripheral0_recalc,
|
||||
};
|
||||
|
||||
static struct clk peripheral0_clk = {
|
||||
.ops = &peripheral0_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
static unsigned long peripheral1_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 4;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops peripheral1_clk_ops = {
|
||||
.recalc = peripheral1_recalc,
|
||||
};
|
||||
|
||||
static struct clk peripheral1_clk = {
|
||||
.ops = &peripheral1_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
struct clk *main_clks[] = {
|
||||
&r_clk,
|
||||
&extal_clk,
|
||||
&pll_clk,
|
||||
&peripheral0_clk,
|
||||
&peripheral1_clk,
|
||||
};
|
||||
|
||||
static int div2[] = { 1, 2, 0, 4 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = div2,
|
||||
.nr_divisors = ARRAY_SIZE(div2),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
enum { DIV4_I, DIV4_B,
|
||||
DIV4_NR };
|
||||
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
/* The mask field specifies the div2 entries that are valid */
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
|
||||
| CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
|
||||
| CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
enum { MSTP72,
|
||||
MSTP60,
|
||||
MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
|
||||
MSTP35, MSTP32, MSTP30,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */
|
||||
[MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */
|
||||
[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
|
||||
[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
|
||||
[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
|
||||
[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
|
||||
[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
|
||||
[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
|
||||
[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
|
||||
[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
|
||||
[MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */
|
||||
[MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */
|
||||
[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
|
||||
|
||||
/* MSTP clocks */
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
|
||||
CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
|
||||
CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
|
||||
CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
|
||||
CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
|
||||
CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
|
||||
};
|
||||
|
||||
int __init arch_clk_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
250
arch/sh/kernel/cpu/sh2a/entry.S
Normal file
250
arch/sh/kernel/cpu/sh2a/entry.S
Normal file
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh2a/entry.S
|
||||
*
|
||||
* The SH-2A exception entry
|
||||
*
|
||||
* Copyright (C) 2008 Yoshinori Sato
|
||||
* Based on arch/sh/kernel/cpu/sh2/entry.S
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <cpu/mmu_context.h>
|
||||
#include <asm/unistd.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
/* Offsets to the stack */
|
||||
OFF_R0 = 0 /* Return value. New ABI also arg4 */
|
||||
OFF_R1 = 4 /* New ABI: arg5 */
|
||||
OFF_R2 = 8 /* New ABI: arg6 */
|
||||
OFF_R3 = 12 /* New ABI: syscall_nr */
|
||||
OFF_R4 = 16 /* New ABI: arg0 */
|
||||
OFF_R5 = 20 /* New ABI: arg1 */
|
||||
OFF_R6 = 24 /* New ABI: arg2 */
|
||||
OFF_R7 = 28 /* New ABI: arg3 */
|
||||
OFF_SP = (15*4)
|
||||
OFF_PC = (16*4)
|
||||
OFF_SR = (16*4+2*4)
|
||||
OFF_TRA = (16*4+6*4)
|
||||
|
||||
#include <asm/entry-macros.S>
|
||||
|
||||
ENTRY(exception_handler)
|
||||
! stack
|
||||
! r0 <- point sp
|
||||
! r1
|
||||
! pc
|
||||
! sr
|
||||
! r0 = temporary
|
||||
! r1 = vector (pseudo EXPEVT / INTEVT / TRA)
|
||||
mov.l r2,@-sp
|
||||
cli
|
||||
mov.l $cpu_mode,r2
|
||||
bld.b #6,@(0,r2) !previus SR.MD
|
||||
bst.b #6,@(4*4,r15) !set cpu mode to SR.MD
|
||||
bt 1f
|
||||
! switch to kernel mode
|
||||
bset.b #6,@(0,r2) !set SR.MD
|
||||
mov.l $current_thread_info,r2
|
||||
mov.l @r2,r2
|
||||
mov #(THREAD_SIZE >> 8),r0
|
||||
shll8 r0
|
||||
add r2,r0 ! r0 = kernel stack tail
|
||||
mov r15,r2 ! r2 = user stack top
|
||||
mov r0,r15 ! switch kernel stack
|
||||
mov.l r1,@-r15 ! TRA
|
||||
sts.l macl, @-r15
|
||||
sts.l mach, @-r15
|
||||
stc.l gbr, @-r15
|
||||
mov.l @(4*4,r2),r0
|
||||
mov.l r0,@-r15 ! original SR
|
||||
sts.l pr,@-r15
|
||||
mov.l @(3*4,r2),r0
|
||||
mov.l r0,@-r15 ! original PC
|
||||
mov r2,r0
|
||||
add #(3+2)*4,r0 ! rewind r0 - r3 + exception frame
|
||||
lds r0,pr ! pr = original SP
|
||||
movmu.l r3,@-r15 ! save regs
|
||||
mov r2,r8 ! r8 = previus stack top
|
||||
mov r1,r9 ! r9 = interrupt vector
|
||||
! restore previous stack
|
||||
mov.l @r8+,r2
|
||||
mov.l @r8+,r0
|
||||
mov.l @r8+,r1
|
||||
bra 2f
|
||||
movml.l r2,@-r15
|
||||
1:
|
||||
! in kernel exception
|
||||
mov r15,r2
|
||||
add #-((OFF_TRA + 4) - OFF_PC) + 5*4,r15
|
||||
movmu.l r3,@-r15
|
||||
mov r2,r8 ! r8 = previous stack top
|
||||
mov r1,r9 ! r9 = interrupt vector
|
||||
! restore exception frame & regs
|
||||
mov.l @r8+,r2 ! old R2
|
||||
mov.l @r8+,r0 ! old R0
|
||||
mov.l @r8+,r1 ! old R1
|
||||
mov.l @r8+,r10 ! old PC
|
||||
mov.l @r8+,r11 ! old SR
|
||||
movml.l r2,@-r15
|
||||
mov.l r10,@(OFF_PC,r15)
|
||||
mov.l r11,@(OFF_SR,r15)
|
||||
mov.l r8,@(OFF_SP,r15) ! save old sp
|
||||
mov r15,r8
|
||||
add #OFF_TRA + 4,r8
|
||||
mov.l r9,@-r8
|
||||
sts.l macl,@-r8
|
||||
sts.l mach,@-r8
|
||||
stc.l gbr,@-r8
|
||||
add #-4,r8
|
||||
sts.l pr,@-r8
|
||||
2:
|
||||
! dispatch exception / interrupt
|
||||
mov #64,r8
|
||||
cmp/hs r8,r9
|
||||
bt interrupt_entry ! vec >= 64 is interrupt
|
||||
mov #32,r8
|
||||
cmp/hs r8,r9
|
||||
bt trap_entry ! 64 > vec >= 32 is trap
|
||||
|
||||
mov.l 4f,r8
|
||||
mov r9,r4
|
||||
shll2 r9
|
||||
add r9,r8
|
||||
mov.l @r8,r8 ! exception handler address
|
||||
tst r8,r8
|
||||
bf 3f
|
||||
mov.l 8f,r8 ! unhandled exception
|
||||
3:
|
||||
mov.l 5f,r10
|
||||
jmp @r8
|
||||
lds r10,pr
|
||||
|
||||
interrupt_entry:
|
||||
mov r9,r4
|
||||
mov r15,r5
|
||||
mov.l 7f,r8
|
||||
mov.l 6f,r9
|
||||
jmp @r8
|
||||
lds r9,pr
|
||||
|
||||
.align 2
|
||||
4: .long exception_handling_table
|
||||
5: .long ret_from_exception
|
||||
6: .long ret_from_irq
|
||||
7: .long do_IRQ
|
||||
8: .long exception_error
|
||||
|
||||
trap_entry:
|
||||
mov #0x30,r8
|
||||
cmp/ge r8,r9 ! vector 0x20-0x2f is systemcall
|
||||
bt 1f
|
||||
add #-0x10,r9 ! convert SH2 to SH3/4 ABI
|
||||
1:
|
||||
shll2 r9 ! TRA
|
||||
bra system_call ! jump common systemcall entry
|
||||
mov r9,r8
|
||||
|
||||
#if defined(CONFIG_SH_STANDARD_BIOS)
|
||||
/* Unwind the stack and jmp to the debug entry */
|
||||
ENTRY(sh_bios_handler)
|
||||
mov r15,r0
|
||||
add #(22-4)*4-4,r0
|
||||
ldc.l @r0+,gbr
|
||||
lds.l @r0+,mach
|
||||
lds.l @r0+,macl
|
||||
mov r15,r0
|
||||
mov.l @(OFF_SP,r0),r1
|
||||
mov.l @(OFF_SR,r2),r3
|
||||
mov.l r3,@-r1
|
||||
mov.l @(OFF_SP,r2),r3
|
||||
mov.l r3,@-r1
|
||||
mov r15,r0
|
||||
add #(22-4)*4-8,r0
|
||||
mov.l 1f,r2
|
||||
mov.l @r2,r2
|
||||
stc sr,r3
|
||||
mov.l r2,@r0
|
||||
mov.l r3,@(4,r0)
|
||||
mov.l r1,@(8,r0)
|
||||
movml.l @r15+,r14
|
||||
add #8,r15
|
||||
lds.l @r15+, pr
|
||||
mov.l @r15+,r15
|
||||
rte
|
||||
nop
|
||||
.align 2
|
||||
1: .long gdb_vbr_vector
|
||||
#endif /* CONFIG_SH_STANDARD_BIOS */
|
||||
|
||||
ENTRY(address_error_trap_handler)
|
||||
mov r15,r4 ! regs
|
||||
mov.l @(OFF_PC,r15),r6 ! pc
|
||||
mov.l 1f,r0
|
||||
jmp @r0
|
||||
mov #0,r5 ! writeaccess is unknown
|
||||
|
||||
.align 2
|
||||
1: .long do_address_error
|
||||
|
||||
restore_all:
|
||||
stc sr,r0
|
||||
or #0xf0,r0
|
||||
ldc r0,sr ! all interrupt block (same BL = 1)
|
||||
! restore special register
|
||||
! overlap exception frame
|
||||
mov r15,r0
|
||||
add #17*4,r0
|
||||
lds.l @r0+,pr
|
||||
add #4,r0
|
||||
ldc.l @r0+,gbr
|
||||
lds.l @r0+,mach
|
||||
lds.l @r0+,macl
|
||||
mov r15,r0
|
||||
mov.l $cpu_mode,r2
|
||||
bld.b #6,@(OFF_SR,r15)
|
||||
bst.b #6,@(0,r2) ! save CPU mode
|
||||
mov.l @(OFF_SR,r0),r1
|
||||
shll2 r1
|
||||
shlr2 r1 ! clear MD bit
|
||||
mov.l @(OFF_SP,r0),r2
|
||||
add #-8,r2
|
||||
mov.l r2,@(OFF_SP,r0) ! point exception frame top
|
||||
mov.l r1,@(4,r2) ! set sr
|
||||
mov.l @(OFF_PC,r0),r1
|
||||
mov.l r1,@r2 ! set pc
|
||||
get_current_thread_info r0, r1
|
||||
mov.l $current_thread_info,r1
|
||||
mov.l r0,@r1
|
||||
movml.l @r15+,r14
|
||||
mov.l @r15,r15
|
||||
rte
|
||||
nop
|
||||
|
||||
.align 2
|
||||
$current_thread_info:
|
||||
.long __current_thread_info
|
||||
$cpu_mode:
|
||||
.long __cpu_mode
|
||||
|
||||
! common exception handler
|
||||
#include "../../entry-common.S"
|
||||
|
||||
.data
|
||||
! cpu operation mode
|
||||
! bit30 = MD (compatible SH3/4)
|
||||
__cpu_mode:
|
||||
.long 0x40000000
|
||||
|
||||
.section .bss
|
||||
__current_thread_info:
|
||||
.long 0
|
||||
|
||||
ENTRY(exception_handling_table)
|
||||
.space 4*32
|
||||
73
arch/sh/kernel/cpu/sh2a/ex.S
Normal file
73
arch/sh/kernel/cpu/sh2a/ex.S
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh2a/ex.S
|
||||
*
|
||||
* The SH-2A exception vector table
|
||||
*
|
||||
* Copyright (C) 2008 Yoshinori Sato
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
!
|
||||
! convert Exception Vector to Exception Number
|
||||
!
|
||||
|
||||
! exception no 0 to 255
|
||||
exception_entry0:
|
||||
no = 0
|
||||
.rept 256
|
||||
mov.l r1,@-sp
|
||||
bra exception_trampoline0
|
||||
mov #no,r1
|
||||
no = no + 1
|
||||
.endr
|
||||
exception_trampoline0:
|
||||
mov.l r0,@-sp
|
||||
mov.l 1f,r0
|
||||
extu.b r1,r1
|
||||
jmp @r0
|
||||
extu.w r1,r1
|
||||
|
||||
.align 2
|
||||
1: .long exception_handler
|
||||
|
||||
! exception no 256 to 511
|
||||
exception_entry1:
|
||||
no = 0
|
||||
.rept 256
|
||||
mov.l r1,@-sp
|
||||
bra exception_trampoline1
|
||||
mov #no,r1
|
||||
no = no + 1
|
||||
.endr
|
||||
exception_trampoline1:
|
||||
mov.l r0,@-sp
|
||||
extu.b r1,r1
|
||||
movi20 #0x100,r0
|
||||
add r0,r1
|
||||
mov.l 1f,r0
|
||||
jmp @r0
|
||||
extu.w r1,r1
|
||||
|
||||
.align 2
|
||||
1: .long exception_handler
|
||||
|
||||
!
|
||||
! Exception Vector Base
|
||||
!
|
||||
.align 2
|
||||
ENTRY(vbr_base)
|
||||
vector = 0
|
||||
.rept 256
|
||||
.long exception_entry0 + vector * 6
|
||||
vector = vector + 1
|
||||
.endr
|
||||
vector = 0
|
||||
.rept 256
|
||||
.long exception_entry1 + vector * 6
|
||||
vector = vector + 1
|
||||
.endr
|
||||
575
arch/sh/kernel/cpu/sh2a/fpu.c
Normal file
575
arch/sh/kernel/cpu/sh2a/fpu.c
Normal file
|
|
@ -0,0 +1,575 @@
|
|||
/*
|
||||
* Save/restore floating point context for signal handlers.
|
||||
*
|
||||
* Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* FIXME! These routines can be optimized in big endian case.
|
||||
*/
|
||||
#include <linux/sched.h>
|
||||
#include <linux/signal.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/fpu.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
/* The PR (precision) bit in the FP Status Register must be clear when
|
||||
* an frchg instruction is executed, otherwise the instruction is undefined.
|
||||
* Executing frchg with PR set causes a trap on some SH4 implementations.
|
||||
*/
|
||||
|
||||
#define FPSCR_RCHG 0x00000000
|
||||
|
||||
|
||||
/*
|
||||
* Save FPU registers onto task structure.
|
||||
*/
|
||||
void save_fpu(struct task_struct *tsk)
|
||||
{
|
||||
unsigned long dummy;
|
||||
|
||||
enable_fpu();
|
||||
asm volatile("sts.l fpul, @-%0\n\t"
|
||||
"sts.l fpscr, @-%0\n\t"
|
||||
"fmov.s fr15, @-%0\n\t"
|
||||
"fmov.s fr14, @-%0\n\t"
|
||||
"fmov.s fr13, @-%0\n\t"
|
||||
"fmov.s fr12, @-%0\n\t"
|
||||
"fmov.s fr11, @-%0\n\t"
|
||||
"fmov.s fr10, @-%0\n\t"
|
||||
"fmov.s fr9, @-%0\n\t"
|
||||
"fmov.s fr8, @-%0\n\t"
|
||||
"fmov.s fr7, @-%0\n\t"
|
||||
"fmov.s fr6, @-%0\n\t"
|
||||
"fmov.s fr5, @-%0\n\t"
|
||||
"fmov.s fr4, @-%0\n\t"
|
||||
"fmov.s fr3, @-%0\n\t"
|
||||
"fmov.s fr2, @-%0\n\t"
|
||||
"fmov.s fr1, @-%0\n\t"
|
||||
"fmov.s fr0, @-%0\n\t"
|
||||
"lds %3, fpscr\n\t"
|
||||
: "=r" (dummy)
|
||||
: "0" ((char *)(&tsk->thread.xstate->hardfpu.status)),
|
||||
"r" (FPSCR_RCHG),
|
||||
"r" (FPSCR_INIT)
|
||||
: "memory");
|
||||
|
||||
disable_fpu();
|
||||
}
|
||||
|
||||
void restore_fpu(struct task_struct *tsk)
|
||||
{
|
||||
unsigned long dummy;
|
||||
|
||||
enable_fpu();
|
||||
asm volatile("fmov.s @%0+, fr0\n\t"
|
||||
"fmov.s @%0+, fr1\n\t"
|
||||
"fmov.s @%0+, fr2\n\t"
|
||||
"fmov.s @%0+, fr3\n\t"
|
||||
"fmov.s @%0+, fr4\n\t"
|
||||
"fmov.s @%0+, fr5\n\t"
|
||||
"fmov.s @%0+, fr6\n\t"
|
||||
"fmov.s @%0+, fr7\n\t"
|
||||
"fmov.s @%0+, fr8\n\t"
|
||||
"fmov.s @%0+, fr9\n\t"
|
||||
"fmov.s @%0+, fr10\n\t"
|
||||
"fmov.s @%0+, fr11\n\t"
|
||||
"fmov.s @%0+, fr12\n\t"
|
||||
"fmov.s @%0+, fr13\n\t"
|
||||
"fmov.s @%0+, fr14\n\t"
|
||||
"fmov.s @%0+, fr15\n\t"
|
||||
"lds.l @%0+, fpscr\n\t"
|
||||
"lds.l @%0+, fpul\n\t"
|
||||
: "=r" (dummy)
|
||||
: "0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
|
||||
: "memory");
|
||||
disable_fpu();
|
||||
}
|
||||
|
||||
/*
|
||||
* Emulate arithmetic ops on denormalized number for some FPU insns.
|
||||
*/
|
||||
|
||||
/* denormalized float * float */
|
||||
static int denormal_mulf(int hx, int hy)
|
||||
{
|
||||
unsigned int ix, iy;
|
||||
unsigned long long m, n;
|
||||
int exp, w;
|
||||
|
||||
ix = hx & 0x7fffffff;
|
||||
iy = hy & 0x7fffffff;
|
||||
if (iy < 0x00800000 || ix == 0)
|
||||
return ((hx ^ hy) & 0x80000000);
|
||||
|
||||
exp = (iy & 0x7f800000) >> 23;
|
||||
ix &= 0x007fffff;
|
||||
iy = (iy & 0x007fffff) | 0x00800000;
|
||||
m = (unsigned long long)ix * iy;
|
||||
n = m;
|
||||
w = -1;
|
||||
while (n) { n >>= 1; w++; }
|
||||
|
||||
/* FIXME: use guard bits */
|
||||
exp += w - 126 - 46;
|
||||
if (exp > 0)
|
||||
ix = ((int) (m >> (w - 23)) & 0x007fffff) | (exp << 23);
|
||||
else if (exp + 22 >= 0)
|
||||
ix = (int) (m >> (w - 22 - exp)) & 0x007fffff;
|
||||
else
|
||||
ix = 0;
|
||||
|
||||
ix |= (hx ^ hy) & 0x80000000;
|
||||
return ix;
|
||||
}
|
||||
|
||||
/* denormalized double * double */
|
||||
static void mult64(unsigned long long x, unsigned long long y,
|
||||
unsigned long long *highp, unsigned long long *lowp)
|
||||
{
|
||||
unsigned long long sub0, sub1, sub2, sub3;
|
||||
unsigned long long high, low;
|
||||
|
||||
sub0 = (x >> 32) * (unsigned long) (y >> 32);
|
||||
sub1 = (x & 0xffffffffLL) * (unsigned long) (y >> 32);
|
||||
sub2 = (x >> 32) * (unsigned long) (y & 0xffffffffLL);
|
||||
sub3 = (x & 0xffffffffLL) * (unsigned long) (y & 0xffffffffLL);
|
||||
low = sub3;
|
||||
high = 0LL;
|
||||
sub3 += (sub1 << 32);
|
||||
if (low > sub3)
|
||||
high++;
|
||||
low = sub3;
|
||||
sub3 += (sub2 << 32);
|
||||
if (low > sub3)
|
||||
high++;
|
||||
low = sub3;
|
||||
high += (sub1 >> 32) + (sub2 >> 32);
|
||||
high += sub0;
|
||||
*lowp = low;
|
||||
*highp = high;
|
||||
}
|
||||
|
||||
static inline long long rshift64(unsigned long long mh,
|
||||
unsigned long long ml, int n)
|
||||
{
|
||||
if (n >= 64)
|
||||
return mh >> (n - 64);
|
||||
return (mh << (64 - n)) | (ml >> n);
|
||||
}
|
||||
|
||||
static long long denormal_muld(long long hx, long long hy)
|
||||
{
|
||||
unsigned long long ix, iy;
|
||||
unsigned long long mh, ml, nh, nl;
|
||||
int exp, w;
|
||||
|
||||
ix = hx & 0x7fffffffffffffffLL;
|
||||
iy = hy & 0x7fffffffffffffffLL;
|
||||
if (iy < 0x0010000000000000LL || ix == 0)
|
||||
return ((hx ^ hy) & 0x8000000000000000LL);
|
||||
|
||||
exp = (iy & 0x7ff0000000000000LL) >> 52;
|
||||
ix &= 0x000fffffffffffffLL;
|
||||
iy = (iy & 0x000fffffffffffffLL) | 0x0010000000000000LL;
|
||||
mult64(ix, iy, &mh, &ml);
|
||||
nh = mh;
|
||||
nl = ml;
|
||||
w = -1;
|
||||
if (nh) {
|
||||
while (nh) { nh >>= 1; w++;}
|
||||
w += 64;
|
||||
} else
|
||||
while (nl) { nl >>= 1; w++;}
|
||||
|
||||
/* FIXME: use guard bits */
|
||||
exp += w - 1022 - 52 * 2;
|
||||
if (exp > 0)
|
||||
ix = (rshift64(mh, ml, w - 52) & 0x000fffffffffffffLL)
|
||||
| ((long long)exp << 52);
|
||||
else if (exp + 51 >= 0)
|
||||
ix = rshift64(mh, ml, w - 51 - exp) & 0x000fffffffffffffLL;
|
||||
else
|
||||
ix = 0;
|
||||
|
||||
ix |= (hx ^ hy) & 0x8000000000000000LL;
|
||||
return ix;
|
||||
}
|
||||
|
||||
/* ix - iy where iy: denormal and ix, iy >= 0 */
|
||||
static int denormal_subf1(unsigned int ix, unsigned int iy)
|
||||
{
|
||||
int frac;
|
||||
int exp;
|
||||
|
||||
if (ix < 0x00800000)
|
||||
return ix - iy;
|
||||
|
||||
exp = (ix & 0x7f800000) >> 23;
|
||||
if (exp - 1 > 31)
|
||||
return ix;
|
||||
iy >>= exp - 1;
|
||||
if (iy == 0)
|
||||
return ix;
|
||||
|
||||
frac = (ix & 0x007fffff) | 0x00800000;
|
||||
frac -= iy;
|
||||
while (frac < 0x00800000) {
|
||||
if (--exp == 0)
|
||||
return frac;
|
||||
frac <<= 1;
|
||||
}
|
||||
|
||||
return (exp << 23) | (frac & 0x007fffff);
|
||||
}
|
||||
|
||||
/* ix + iy where iy: denormal and ix, iy >= 0 */
|
||||
static int denormal_addf1(unsigned int ix, unsigned int iy)
|
||||
{
|
||||
int frac;
|
||||
int exp;
|
||||
|
||||
if (ix < 0x00800000)
|
||||
return ix + iy;
|
||||
|
||||
exp = (ix & 0x7f800000) >> 23;
|
||||
if (exp - 1 > 31)
|
||||
return ix;
|
||||
iy >>= exp - 1;
|
||||
if (iy == 0)
|
||||
return ix;
|
||||
|
||||
frac = (ix & 0x007fffff) | 0x00800000;
|
||||
frac += iy;
|
||||
if (frac >= 0x01000000) {
|
||||
frac >>= 1;
|
||||
++exp;
|
||||
}
|
||||
|
||||
return (exp << 23) | (frac & 0x007fffff);
|
||||
}
|
||||
|
||||
static int denormal_addf(int hx, int hy)
|
||||
{
|
||||
unsigned int ix, iy;
|
||||
int sign;
|
||||
|
||||
if ((hx ^ hy) & 0x80000000) {
|
||||
sign = hx & 0x80000000;
|
||||
ix = hx & 0x7fffffff;
|
||||
iy = hy & 0x7fffffff;
|
||||
if (iy < 0x00800000) {
|
||||
ix = denormal_subf1(ix, iy);
|
||||
if ((int) ix < 0) {
|
||||
ix = -ix;
|
||||
sign ^= 0x80000000;
|
||||
}
|
||||
} else {
|
||||
ix = denormal_subf1(iy, ix);
|
||||
sign ^= 0x80000000;
|
||||
}
|
||||
} else {
|
||||
sign = hx & 0x80000000;
|
||||
ix = hx & 0x7fffffff;
|
||||
iy = hy & 0x7fffffff;
|
||||
if (iy < 0x00800000)
|
||||
ix = denormal_addf1(ix, iy);
|
||||
else
|
||||
ix = denormal_addf1(iy, ix);
|
||||
}
|
||||
|
||||
return sign | ix;
|
||||
}
|
||||
|
||||
/* ix - iy where iy: denormal and ix, iy >= 0 */
|
||||
static long long denormal_subd1(unsigned long long ix, unsigned long long iy)
|
||||
{
|
||||
long long frac;
|
||||
int exp;
|
||||
|
||||
if (ix < 0x0010000000000000LL)
|
||||
return ix - iy;
|
||||
|
||||
exp = (ix & 0x7ff0000000000000LL) >> 52;
|
||||
if (exp - 1 > 63)
|
||||
return ix;
|
||||
iy >>= exp - 1;
|
||||
if (iy == 0)
|
||||
return ix;
|
||||
|
||||
frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
|
||||
frac -= iy;
|
||||
while (frac < 0x0010000000000000LL) {
|
||||
if (--exp == 0)
|
||||
return frac;
|
||||
frac <<= 1;
|
||||
}
|
||||
|
||||
return ((long long)exp << 52) | (frac & 0x000fffffffffffffLL);
|
||||
}
|
||||
|
||||
/* ix + iy where iy: denormal and ix, iy >= 0 */
|
||||
static long long denormal_addd1(unsigned long long ix, unsigned long long iy)
|
||||
{
|
||||
long long frac;
|
||||
long long exp;
|
||||
|
||||
if (ix < 0x0010000000000000LL)
|
||||
return ix + iy;
|
||||
|
||||
exp = (ix & 0x7ff0000000000000LL) >> 52;
|
||||
if (exp - 1 > 63)
|
||||
return ix;
|
||||
iy >>= exp - 1;
|
||||
if (iy == 0)
|
||||
return ix;
|
||||
|
||||
frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
|
||||
frac += iy;
|
||||
if (frac >= 0x0020000000000000LL) {
|
||||
frac >>= 1;
|
||||
++exp;
|
||||
}
|
||||
|
||||
return (exp << 52) | (frac & 0x000fffffffffffffLL);
|
||||
}
|
||||
|
||||
static long long denormal_addd(long long hx, long long hy)
|
||||
{
|
||||
unsigned long long ix, iy;
|
||||
long long sign;
|
||||
|
||||
if ((hx ^ hy) & 0x8000000000000000LL) {
|
||||
sign = hx & 0x8000000000000000LL;
|
||||
ix = hx & 0x7fffffffffffffffLL;
|
||||
iy = hy & 0x7fffffffffffffffLL;
|
||||
if (iy < 0x0010000000000000LL) {
|
||||
ix = denormal_subd1(ix, iy);
|
||||
if ((int) ix < 0) {
|
||||
ix = -ix;
|
||||
sign ^= 0x8000000000000000LL;
|
||||
}
|
||||
} else {
|
||||
ix = denormal_subd1(iy, ix);
|
||||
sign ^= 0x8000000000000000LL;
|
||||
}
|
||||
} else {
|
||||
sign = hx & 0x8000000000000000LL;
|
||||
ix = hx & 0x7fffffffffffffffLL;
|
||||
iy = hy & 0x7fffffffffffffffLL;
|
||||
if (iy < 0x0010000000000000LL)
|
||||
ix = denormal_addd1(ix, iy);
|
||||
else
|
||||
ix = denormal_addd1(iy, ix);
|
||||
}
|
||||
|
||||
return sign | ix;
|
||||
}
|
||||
|
||||
/**
|
||||
* denormal_to_double - Given denormalized float number,
|
||||
* store double float
|
||||
*
|
||||
* @fpu: Pointer to sh_fpu_hard structure
|
||||
* @n: Index to FP register
|
||||
*/
|
||||
static void
|
||||
denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
|
||||
{
|
||||
unsigned long du, dl;
|
||||
unsigned long x = fpu->fpul;
|
||||
int exp = 1023 - 126;
|
||||
|
||||
if (x != 0 && (x & 0x7f800000) == 0) {
|
||||
du = (x & 0x80000000);
|
||||
while ((x & 0x00800000) == 0) {
|
||||
x <<= 1;
|
||||
exp--;
|
||||
}
|
||||
x &= 0x007fffff;
|
||||
du |= (exp << 20) | (x >> 3);
|
||||
dl = x << 29;
|
||||
|
||||
fpu->fp_regs[n] = du;
|
||||
fpu->fp_regs[n+1] = dl;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ieee_fpe_handler - Handle denormalized number exception
|
||||
*
|
||||
* @regs: Pointer to register structure
|
||||
*
|
||||
* Returns 1 when it's handled (should not cause exception).
|
||||
*/
|
||||
static int
|
||||
ieee_fpe_handler (struct pt_regs *regs)
|
||||
{
|
||||
unsigned short insn = *(unsigned short *) regs->pc;
|
||||
unsigned short finsn;
|
||||
unsigned long nextpc;
|
||||
int nib[4] = {
|
||||
(insn >> 12) & 0xf,
|
||||
(insn >> 8) & 0xf,
|
||||
(insn >> 4) & 0xf,
|
||||
insn & 0xf};
|
||||
|
||||
if (nib[0] == 0xb ||
|
||||
(nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
|
||||
regs->pr = regs->pc + 4;
|
||||
if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
|
||||
nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
else
|
||||
nextpc = regs->pc + 4;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4;
|
||||
else
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x4 && nib[3] == 0xb &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
|
||||
nextpc = regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x0 && nib[3] == 0x3 &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
|
||||
nextpc = regs->pc + 4 + regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (insn == 0x000b) { /* rts */
|
||||
nextpc = regs->pr;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else {
|
||||
nextpc = regs->pc + 2;
|
||||
finsn = insn;
|
||||
}
|
||||
|
||||
#define FPSCR_FPU_ERROR (1 << 17)
|
||||
|
||||
if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_FPU_ERROR)) {
|
||||
/* FPU error */
|
||||
denormal_to_double (&tsk->thread.xstate->hardfpu,
|
||||
(finsn >> 8) & 0xf);
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
} else if ((finsn & 0xf00f) == 0xf002) { /* fmul */
|
||||
struct task_struct *tsk = current;
|
||||
int fpscr;
|
||||
int n, m, prec;
|
||||
unsigned int hx, hy;
|
||||
|
||||
n = (finsn >> 8) & 0xf;
|
||||
m = (finsn >> 4) & 0xf;
|
||||
hx = tsk->thread.xstate->hardfpu.fp_regs[n];
|
||||
hy = tsk->thread.xstate->hardfpu.fp_regs[m];
|
||||
fpscr = tsk->thread.xstate->hardfpu.fpscr;
|
||||
prec = fpscr & (1 << 19);
|
||||
|
||||
if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
||||
|| (hy & 0x7fffffff) < 0x00100000))) {
|
||||
long long llx, lly;
|
||||
|
||||
/* FPU error because of denormal */
|
||||
llx = ((long long) hx << 32)
|
||||
| tsk->thread.xstate->hardfpu.fp_regs[n+1];
|
||||
lly = ((long long) hy << 32)
|
||||
| tsk->thread.xstate->hardfpu.fp_regs[m+1];
|
||||
if ((hx & 0x7fffffff) >= 0x00100000)
|
||||
llx = denormal_muld(lly, llx);
|
||||
else
|
||||
llx = denormal_muld(llx, lly);
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
||||
/* FPU error because of denormal */
|
||||
if ((hx & 0x7fffffff) >= 0x00800000)
|
||||
hx = denormal_mulf(hy, hx);
|
||||
else
|
||||
hx = denormal_mulf(hx, hy);
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
} else if ((finsn & 0xf00e) == 0xf000) { /* fadd, fsub */
|
||||
struct task_struct *tsk = current;
|
||||
int fpscr;
|
||||
int n, m, prec;
|
||||
unsigned int hx, hy;
|
||||
|
||||
n = (finsn >> 8) & 0xf;
|
||||
m = (finsn >> 4) & 0xf;
|
||||
hx = tsk->thread.xstate->hardfpu.fp_regs[n];
|
||||
hy = tsk->thread.xstate->hardfpu.fp_regs[m];
|
||||
fpscr = tsk->thread.xstate->hardfpu.fpscr;
|
||||
prec = fpscr & (1 << 19);
|
||||
|
||||
if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
||||
|| (hy & 0x7fffffff) < 0x00100000))) {
|
||||
long long llx, lly;
|
||||
|
||||
/* FPU error because of denormal */
|
||||
llx = ((long long) hx << 32)
|
||||
| tsk->thread.xstate->hardfpu.fp_regs[n+1];
|
||||
lly = ((long long) hy << 32)
|
||||
| tsk->thread.xstate->hardfpu.fp_regs[m+1];
|
||||
if ((finsn & 0xf00f) == 0xf000)
|
||||
llx = denormal_addd(llx, lly);
|
||||
else
|
||||
llx = denormal_addd(llx, lly ^ (1LL << 63));
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
||||
/* FPU error because of denormal */
|
||||
if ((finsn & 0xf00f) == 0xf000)
|
||||
hx = denormal_addf(hx, hy);
|
||||
else
|
||||
hx = denormal_addf(hx, hy ^ 0x80000000);
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
BUILD_TRAP_HANDLER(fpu_error)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
__unlazy_fpu(tsk, regs);
|
||||
if (ieee_fpe_handler(regs)) {
|
||||
tsk->thread.xstate->hardfpu.fpscr &=
|
||||
~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
|
||||
grab_fpu(regs);
|
||||
restore_fpu(tsk);
|
||||
task_thread_info(tsk)->status |= TS_USEDFPU;
|
||||
return;
|
||||
}
|
||||
|
||||
force_sig(SIGFPE, tsk);
|
||||
}
|
||||
54
arch/sh/kernel/cpu/sh2a/opcode_helper.c
Normal file
54
arch/sh/kernel/cpu/sh2a/opcode_helper.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh2a/opcode_helper.c
|
||||
*
|
||||
* Helper for the SH-2A 32-bit opcodes.
|
||||
*
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
||||
/*
|
||||
* Instructions on SH are generally fixed at 16-bits, however, SH-2A
|
||||
* introduces some 32-bit instructions. Since there are no real
|
||||
* constraints on their use (and they can be mixed and matched), we need
|
||||
* to check the instruction encoding to work out if it's a true 32-bit
|
||||
* instruction or not.
|
||||
*
|
||||
* Presently, 32-bit opcodes have only slight variations in what the
|
||||
* actual encoding looks like in the first-half of the instruction, which
|
||||
* makes it fairly straightforward to differentiate from the 16-bit ones.
|
||||
*
|
||||
* First 16-bits of encoding Used by
|
||||
*
|
||||
* 0011nnnnmmmm0001 mov.b, mov.w, mov.l, fmov.d,
|
||||
* fmov.s, movu.b, movu.w
|
||||
*
|
||||
* 0011nnnn0iii1001 bclr.b, bld.b, bset.b, bst.b, band.b,
|
||||
* bandnot.b, bldnot.b, bor.b, bornot.b,
|
||||
* bxor.b
|
||||
*
|
||||
* 0000nnnniiii0000 movi20
|
||||
* 0000nnnniiii0001 movi20s
|
||||
*/
|
||||
unsigned int instruction_size(unsigned int insn)
|
||||
{
|
||||
/* Look for the common cases */
|
||||
switch ((insn & 0xf00f)) {
|
||||
case 0x0000: /* movi20 */
|
||||
case 0x0001: /* movi20s */
|
||||
case 0x3001: /* 32-bit mov/fmov/movu variants */
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* And the special cases.. */
|
||||
switch ((insn & 0xf08f)) {
|
||||
case 0x3009: /* 32-bit b*.b bit operations */
|
||||
return 4;
|
||||
}
|
||||
|
||||
return 2;
|
||||
}
|
||||
30
arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
Normal file
30
arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* SH7203 Pinmux
|
||||
*
|
||||
* Copyright (C) 2008 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7203_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe3800,
|
||||
.end = 0xfffe3a9f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
|
||||
ARRAY_SIZE(sh7203_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
30
arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
Normal file
30
arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* SH7264 Pinmux
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Electronics Europe Ltd
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7264_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe3800,
|
||||
.end = 0xfffe393f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
|
||||
ARRAY_SIZE(sh7264_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
31
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
Normal file
31
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* SH7269 Pinmux
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Electronics Europe Ltd
|
||||
* Copyright (C) 2012 Phil Edworthy
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <cpu/pfc.h>
|
||||
|
||||
static struct resource sh7269_pfc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe3800,
|
||||
.end = 0xfffe391f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init plat_pinmux_setup(void)
|
||||
{
|
||||
return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
|
||||
ARRAY_SIZE(sh7269_pfc_resources));
|
||||
}
|
||||
arch_initcall(plat_pinmux_setup);
|
||||
60
arch/sh/kernel/cpu/sh2a/probe.c
Normal file
60
arch/sh/kernel/cpu/sh2a/probe.c
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh2a/probe.c
|
||||
*
|
||||
* CPU Subtype Probing for SH-2A.
|
||||
*
|
||||
* Copyright (C) 2004 - 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
void cpu_probe(void)
|
||||
{
|
||||
boot_cpu_data.family = CPU_FAMILY_SH2A;
|
||||
|
||||
/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
|
||||
boot_cpu_data.flags |= CPU_HAS_OP32;
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7201)
|
||||
boot_cpu_data.type = CPU_SH7201;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203)
|
||||
boot_cpu_data.type = CPU_SH7203;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7263)
|
||||
boot_cpu_data.type = CPU_SH7263;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7264)
|
||||
boot_cpu_data.type = CPU_SH7264;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7269)
|
||||
boot_cpu_data.type = CPU_SH7269;
|
||||
boot_cpu_data.flags |= CPU_HAS_FPU;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
boot_cpu_data.type = CPU_SH7206;
|
||||
boot_cpu_data.flags |= CPU_HAS_DSP;
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_MXG)
|
||||
boot_cpu_data.type = CPU_MXG;
|
||||
boot_cpu_data.flags |= CPU_HAS_DSP;
|
||||
#endif
|
||||
|
||||
boot_cpu_data.dcache.ways = 4;
|
||||
boot_cpu_data.dcache.way_incr = (1 << 11);
|
||||
boot_cpu_data.dcache.sets = 128;
|
||||
boot_cpu_data.dcache.entry_shift = 4;
|
||||
boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
|
||||
boot_cpu_data.dcache.flags = 0;
|
||||
|
||||
/*
|
||||
* The icache is the same as the dcache as far as this setup is
|
||||
* concerned. The only real difference in hardware is that the icache
|
||||
* lacks the U bit that the dcache has, none of this has any bearing
|
||||
* on the cache info.
|
||||
*/
|
||||
boot_cpu_data.icache = boot_cpu_data.dcache;
|
||||
}
|
||||
178
arch/sh/kernel/cpu/sh2a/setup-mxg.c
Normal file
178
arch/sh/kernel/cpu/sh2a/setup-mxg.c
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Renesas MX-G (R8A03022BG) Setup
|
||||
*
|
||||
* Copyright (C) 2008, 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
|
||||
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
|
||||
|
||||
SCIF0, SCIF1,
|
||||
|
||||
MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5,
|
||||
MTU2_TGI3B, MTU2_TGI3C,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
|
||||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
|
||||
INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
|
||||
INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
|
||||
INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
|
||||
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
|
||||
INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
|
||||
INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
|
||||
INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
|
||||
INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
|
||||
|
||||
INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221),
|
||||
INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223),
|
||||
INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225),
|
||||
INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227),
|
||||
|
||||
INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229),
|
||||
INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231),
|
||||
INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233),
|
||||
|
||||
INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235),
|
||||
INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237),
|
||||
INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239),
|
||||
|
||||
INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241),
|
||||
INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243),
|
||||
|
||||
INTC_IRQ(MTU2_TGI3B, 244),
|
||||
INTC_IRQ(MTU2_TGI3C, 245),
|
||||
|
||||
INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247),
|
||||
INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249),
|
||||
INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251),
|
||||
|
||||
INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253),
|
||||
INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
|
||||
{ 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
|
||||
{ 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
|
||||
{ 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
|
||||
{ 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
|
||||
{ 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
|
||||
{ 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
|
||||
{ 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
|
||||
{ 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
|
||||
{ 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
|
||||
{ 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
|
||||
{ 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
|
||||
{ 0xfffd9812, 0, 16, 4, /* IPR15 */
|
||||
{ SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
|
||||
{ 0xfffd9814, 0, 16, 4, /* IPR16 */
|
||||
{ MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffd9408, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct resource mtu2_resources[] = {
|
||||
DEFINE_RES_MEM(0xff801000, 0x400),
|
||||
DEFINE_RES_IRQ_NAMED(228, "tgi0a"),
|
||||
DEFINE_RES_IRQ_NAMED(234, "tgi1a"),
|
||||
DEFINE_RES_IRQ_NAMED(240, "tgi2a"),
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_device = {
|
||||
.name = "sh-mtu2",
|
||||
.id = -1,
|
||||
.resource = mtu2_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_resources),
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif0_resources[] = {
|
||||
DEFINE_RES_MEM(0xff804000, 0x100),
|
||||
DEFINE_RES_IRQ(220),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.resource = scif0_resources,
|
||||
.num_resources = ARRAY_SIZE(scif0_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *mxg_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
static int __init mxg_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(mxg_devices,
|
||||
ARRAY_SIZE(mxg_devices));
|
||||
}
|
||||
arch_initcall(mxg_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *mxg_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
early_platform_add_devices(mxg_early_devices,
|
||||
ARRAY_SIZE(mxg_early_devices));
|
||||
}
|
||||
428
arch/sh/kernel/cpu/sh2a/setup-sh7201.c
Normal file
428
arch/sh/kernel/cpu/sh2a/setup-sh7201.c
Normal file
|
|
@ -0,0 +1,428 @@
|
|||
/*
|
||||
* SH7201 setup
|
||||
*
|
||||
* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
|
||||
* Copyright (C) 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
|
||||
ADC_ADI,
|
||||
|
||||
MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
|
||||
MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
|
||||
|
||||
RTC, WDT,
|
||||
|
||||
IIC30, IIC31, IIC32,
|
||||
|
||||
DMAC0_DMINT0, DMAC1_DMINT1,
|
||||
DMAC2_DMINT2, DMAC3_DMINT3,
|
||||
|
||||
SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
|
||||
|
||||
DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
|
||||
DMAC7_DMINT7,
|
||||
|
||||
RCAN0, RCAN1,
|
||||
|
||||
SSI0_SSII, SSI1_SSII,
|
||||
|
||||
TMR0, TMR1,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
|
||||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
|
||||
INTC_IRQ(ADC_ADI, 92),
|
||||
|
||||
INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
|
||||
INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
|
||||
|
||||
INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
|
||||
INTC_IRQ(MTU20_VEF, 114),
|
||||
|
||||
INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
|
||||
INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
|
||||
|
||||
INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
|
||||
INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
|
||||
|
||||
INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
|
||||
INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
|
||||
|
||||
INTC_IRQ(MTU2_TCI3V, 136),
|
||||
|
||||
INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
|
||||
INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
|
||||
|
||||
INTC_IRQ(MTU2_TCI4V, 144),
|
||||
|
||||
INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
|
||||
INTC_IRQ(MTU25_UVW, 150),
|
||||
|
||||
INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
|
||||
INTC_IRQ(RTC, 154),
|
||||
|
||||
INTC_IRQ(WDT, 156),
|
||||
|
||||
INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
|
||||
INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
|
||||
INTC_IRQ(IIC30, 161),
|
||||
|
||||
INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
|
||||
INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
|
||||
INTC_IRQ(IIC31, 168),
|
||||
|
||||
INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
|
||||
INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
|
||||
INTC_IRQ(IIC32, 174),
|
||||
|
||||
INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
|
||||
INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
|
||||
|
||||
INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
|
||||
INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
|
||||
INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
|
||||
INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
|
||||
INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
|
||||
INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
|
||||
INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
|
||||
INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
|
||||
INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
|
||||
INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
|
||||
INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
|
||||
INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
|
||||
INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
|
||||
INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
|
||||
INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
|
||||
INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
|
||||
|
||||
INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
|
||||
INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
|
||||
INTC_IRQ(DMAC7_DMINT7, 219),
|
||||
|
||||
INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
|
||||
INTC_IRQ(RCAN0, 230),
|
||||
INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
|
||||
|
||||
INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
|
||||
INTC_IRQ(RCAN1, 236),
|
||||
INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
|
||||
|
||||
INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
|
||||
|
||||
INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
|
||||
INTC_IRQ(TMR0, 248),
|
||||
|
||||
INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
|
||||
INTC_IRQ(TMR1, 254),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
|
||||
{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
|
||||
{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
|
||||
{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
|
||||
|
||||
{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
|
||||
{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
|
||||
{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
|
||||
{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
|
||||
{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
|
||||
{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
|
||||
{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
|
||||
{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe9408, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif0_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8000, 0x100),
|
||||
DEFINE_RES_IRQ(180),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.resource = scif0_resources,
|
||||
.num_resources = ARRAY_SIZE(scif0_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif1_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8800, 0x100),
|
||||
DEFINE_RES_IRQ(184),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.resource = scif1_resources,
|
||||
.num_resources = ARRAY_SIZE(scif1_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9000, 0x100),
|
||||
DEFINE_RES_IRQ(188),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.resource = scif2_resources,
|
||||
.num_resources = ARRAY_SIZE(scif2_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif3_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9800, 0x100),
|
||||
DEFINE_RES_IRQ(192),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.resource = scif3_resources,
|
||||
.num_resources = ARRAY_SIZE(scif3_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif4_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif4_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffea000, 0x100),
|
||||
DEFINE_RES_IRQ(196),
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 4,
|
||||
.resource = scif4_resources,
|
||||
.num_resources = ARRAY_SIZE(scif4_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif4_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif5_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif5_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffea800, 0x100),
|
||||
DEFINE_RES_IRQ(200),
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 5,
|
||||
.resource = scif5_resources,
|
||||
.num_resources = ARRAY_SIZE(scif5_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif5_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif6_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif6_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffeb000, 0x100),
|
||||
DEFINE_RES_IRQ(204),
|
||||
};
|
||||
|
||||
static struct platform_device scif6_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 6,
|
||||
.resource = scif6_resources,
|
||||
.num_resources = ARRAY_SIZE(scif6_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif6_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif7_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif7_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffeb800, 0x100),
|
||||
DEFINE_RES_IRQ(208),
|
||||
};
|
||||
|
||||
static struct platform_device scif7_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 7,
|
||||
.resource = scif7_resources,
|
||||
.num_resources = ARRAY_SIZE(scif7_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif7_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffff0800,
|
||||
.end = 0xffff2000 + 0x58 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 152,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
static struct resource mtu2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe4000, 0x400),
|
||||
DEFINE_RES_IRQ_NAMED(108, "tgi0a"),
|
||||
DEFINE_RES_IRQ_NAMED(116, "tgi1a"),
|
||||
DEFINE_RES_IRQ_NAMED(124, "tgi1b"),
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_device = {
|
||||
.name = "sh-mtu2",
|
||||
.id = -1,
|
||||
.resource = mtu2_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *sh7201_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&rtc_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
static int __init sh7201_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7201_devices,
|
||||
ARRAY_SIZE(sh7201_devices));
|
||||
}
|
||||
arch_initcall(sh7201_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *sh7201_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
#define STBCR3 0xfffe0408
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
/* enable MTU2 clock */
|
||||
__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
|
||||
|
||||
early_platform_add_devices(sh7201_early_devices,
|
||||
ARRAY_SIZE(sh7201_early_devices));
|
||||
}
|
||||
365
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
Normal file
365
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
Normal file
|
|
@ -0,0 +1,365 @@
|
|||
/*
|
||||
* SH7203 and SH7263 Setup
|
||||
*
|
||||
* Copyright (C) 2007 - 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
USB, LCDC, CMT0, CMT1, BSC, WDT,
|
||||
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
|
||||
|
||||
ADC_ADI,
|
||||
|
||||
IIC30, IIC31, IIC32, IIC33,
|
||||
SCIF0, SCIF1, SCIF2, SCIF3,
|
||||
|
||||
SSU0, SSU1,
|
||||
|
||||
SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
|
||||
|
||||
/* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
|
||||
ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
|
||||
SRC, IEBI,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
|
||||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
|
||||
INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
|
||||
INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
|
||||
INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
|
||||
INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
|
||||
INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
|
||||
INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
|
||||
INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
|
||||
INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
|
||||
INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
|
||||
INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
|
||||
INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
|
||||
INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
|
||||
INTC_IRQ(MTU0_VEF, 150),
|
||||
INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
|
||||
INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
|
||||
INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
|
||||
INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
|
||||
INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
|
||||
INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
|
||||
INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
|
||||
INTC_IRQ(MTU2_TCI3V, 165),
|
||||
INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
|
||||
INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
|
||||
INTC_IRQ(MTU2_TCI4V, 170),
|
||||
INTC_IRQ(ADC_ADI, 171),
|
||||
INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
|
||||
INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
|
||||
INTC_IRQ(IIC30, 176),
|
||||
INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
|
||||
INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
|
||||
INTC_IRQ(IIC31, 181),
|
||||
INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
|
||||
INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
|
||||
INTC_IRQ(IIC32, 186),
|
||||
INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
|
||||
INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
|
||||
INTC_IRQ(IIC33, 191),
|
||||
INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
|
||||
INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
|
||||
INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
|
||||
INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
|
||||
INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
|
||||
INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
|
||||
INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
|
||||
INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
|
||||
INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
|
||||
INTC_IRQ(SSU0, 210),
|
||||
INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
|
||||
INTC_IRQ(SSU1, 213),
|
||||
INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
|
||||
INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
|
||||
INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
|
||||
INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
|
||||
INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
|
||||
INTC_IRQ(RTC, 233),
|
||||
INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
|
||||
INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
|
||||
INTC_IRQ(RCAN0, 238),
|
||||
INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
|
||||
INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
|
||||
INTC_IRQ(RCAN1, 243),
|
||||
|
||||
/* SH7263-specific trash */
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7263
|
||||
INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
|
||||
INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
|
||||
INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
|
||||
|
||||
INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
|
||||
INTC_IRQ(SDHI, 230),
|
||||
|
||||
INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
|
||||
INTC_IRQ(SRC, 246),
|
||||
|
||||
INTC_IRQ(IEBI, 247),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
|
||||
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
|
||||
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
|
||||
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
|
||||
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
|
||||
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
|
||||
MTU2_VU } },
|
||||
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
|
||||
MTU2_TCI4V } },
|
||||
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
|
||||
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
|
||||
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7203
|
||||
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
|
||||
SSI3_SSII, 0 } },
|
||||
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
|
||||
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
|
||||
#else
|
||||
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
|
||||
SSI3_SSII, ROMDEC } },
|
||||
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
|
||||
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe0808, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif0_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8000, 0x100),
|
||||
DEFINE_RES_IRQ(192),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.resource = scif0_resources,
|
||||
.num_resources = ARRAY_SIZE(scif0_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif1_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8800, 0x100),
|
||||
DEFINE_RES_IRQ(196),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.resource = scif1_resources,
|
||||
.num_resources = ARRAY_SIZE(scif1_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9000, 0x100),
|
||||
DEFINE_RES_IRQ(200),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.resource = scif2_resources,
|
||||
.num_resources = ARRAY_SIZE(scif2_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif3_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9800, 0x100),
|
||||
DEFINE_RES_IRQ(204),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.resource = scif3_resources,
|
||||
.num_resources = ARRAY_SIZE(scif3_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt_platform_data = {
|
||||
.channels_mask = 3,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffec000, 0x10),
|
||||
DEFINE_RES_IRQ(142),
|
||||
DEFINE_RES_IRQ(143),
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh-cmt-16",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct resource mtu2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe4000, 0x400),
|
||||
DEFINE_RES_IRQ_NAMED(146, "tgi0a"),
|
||||
DEFINE_RES_IRQ_NAMED(153, "tgi1a"),
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_device = {
|
||||
.name = "sh-mtu2",
|
||||
.id = -1,
|
||||
.resource = mtu2_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_resources),
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffff2000,
|
||||
.end = 0xffff2000 + 0x58 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 231,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7203_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
&rtc_device,
|
||||
};
|
||||
|
||||
static int __init sh7203_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7203_devices,
|
||||
ARRAY_SIZE(sh7203_devices));
|
||||
}
|
||||
arch_initcall(sh7203_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *sh7203_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
#define STBCR3 0xfffe0408
|
||||
#define STBCR4 0xfffe040c
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
/* enable CMT clock */
|
||||
__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
|
||||
|
||||
/* enable MTU2 clock */
|
||||
__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
|
||||
|
||||
early_platform_add_devices(sh7203_early_devices,
|
||||
ARRAY_SIZE(sh7203_early_devices));
|
||||
}
|
||||
297
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
Normal file
297
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
Normal file
|
|
@ -0,0 +1,297 @@
|
|||
/*
|
||||
* SH7206 Setup
|
||||
*
|
||||
* Copyright (C) 2006 Yoshinori Sato
|
||||
* Copyright (C) 2009 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
ADC_ADI0, ADC_ADI1,
|
||||
|
||||
DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
|
||||
IIC3,
|
||||
|
||||
CMT0, CMT1, BSC, WDT,
|
||||
|
||||
MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
|
||||
|
||||
POE2_OEI3,
|
||||
|
||||
SCIF0, SCIF1, SCIF2, SCIF3,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
|
||||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
|
||||
INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
|
||||
INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
|
||||
INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
|
||||
INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
|
||||
INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
|
||||
INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
|
||||
INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
|
||||
INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
|
||||
INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
|
||||
INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
|
||||
INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
|
||||
INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
|
||||
INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
|
||||
INTC_IRQ(MTU0_VEF, 162),
|
||||
INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
|
||||
INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
|
||||
INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
|
||||
INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
|
||||
INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
|
||||
INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
|
||||
INTC_IRQ(MTU2_TCI3V, 184),
|
||||
INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
|
||||
INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
|
||||
INTC_IRQ(MTU2_TCI4V, 192),
|
||||
INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
|
||||
INTC_IRQ(MTU5, 198),
|
||||
INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
|
||||
INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
|
||||
INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
|
||||
INTC_IRQ(MTU2S_TCI3V, 208),
|
||||
INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
|
||||
INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
|
||||
INTC_IRQ(MTU2S_TCI4V, 216),
|
||||
INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
|
||||
INTC_IRQ(MTU5S, 222),
|
||||
INTC_IRQ(POE2_OEI3, 224),
|
||||
INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
|
||||
INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
|
||||
INTC_IRQ(IIC3, 232),
|
||||
INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
|
||||
INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
|
||||
INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
|
||||
INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
|
||||
INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
|
||||
INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
|
||||
INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
|
||||
INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
|
||||
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
|
||||
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
|
||||
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
|
||||
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
|
||||
MTU1_AB, MTU1_VU } },
|
||||
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU2_TCI3V } },
|
||||
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
|
||||
MTU5, POE2_12 } },
|
||||
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
|
||||
MTU4S_ABCD, MTU2S_TCI4V } },
|
||||
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
|
||||
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe0808, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif0_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8000, 0x100),
|
||||
DEFINE_RES_IRQ(240),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.resource = scif0_resources,
|
||||
.num_resources = ARRAY_SIZE(scif0_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif1_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8800, 0x100),
|
||||
DEFINE_RES_IRQ(244),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.resource = scif1_resources,
|
||||
.num_resources = ARRAY_SIZE(scif1_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9000, 0x100),
|
||||
DEFINE_RES_IRQ(248),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.resource = scif2_resources,
|
||||
.num_resources = ARRAY_SIZE(scif2_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
|
||||
.type = PORT_SCIF,
|
||||
};
|
||||
|
||||
static struct resource scif3_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9800, 0x100),
|
||||
DEFINE_RES_IRQ(252),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.resource = scif3_resources,
|
||||
.num_resources = ARRAY_SIZE(scif3_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt_platform_data = {
|
||||
.channels_mask = 3,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffec000, 0x10),
|
||||
DEFINE_RES_IRQ(140),
|
||||
DEFINE_RES_IRQ(144),
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh-cmt-16",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct resource mtu2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe4000, 0x400),
|
||||
DEFINE_RES_IRQ_NAMED(156, "tgi0a"),
|
||||
DEFINE_RES_IRQ_NAMED(164, "tgi1a"),
|
||||
DEFINE_RES_IRQ_NAMED(180, "tgi2a"),
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_device = {
|
||||
.name = "sh-mtu2s",
|
||||
.id = -1,
|
||||
.resource = mtu2_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *sh7206_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
static int __init sh7206_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7206_devices,
|
||||
ARRAY_SIZE(sh7206_devices));
|
||||
}
|
||||
arch_initcall(sh7206_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *sh7206_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
#define STBCR3 0xfffe0408
|
||||
#define STBCR4 0xfffe040c
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
/* enable CMT clock */
|
||||
__raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
|
||||
|
||||
/* enable MTU2 clock */
|
||||
__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
|
||||
|
||||
early_platform_add_devices(sh7206_early_devices,
|
||||
ARRAY_SIZE(sh7206_early_devices));
|
||||
}
|
||||
570
arch/sh/kernel/cpu/sh2a/setup-sh7264.c
Normal file
570
arch/sh/kernel/cpu/sh2a/setup-sh7264.c
Normal file
|
|
@ -0,0 +1,570 @@
|
|||
/*
|
||||
* SH7264 Setup
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Electronics Europe Ltd
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/usb/r8a66597.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
|
||||
DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
|
||||
USB, VDC3, CMT0, CMT1, BSC, WDT,
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
|
||||
PWMT1, PWMT2, ADC_ADI,
|
||||
SSIF0, SSII1, SSII2, SSII3,
|
||||
RSPDIF,
|
||||
IIC30, IIC31, IIC32, IIC33,
|
||||
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
|
||||
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
|
||||
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
|
||||
SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
|
||||
SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
|
||||
SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
|
||||
SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
|
||||
SIO_FIFO, RSPIC0, RSPIC1,
|
||||
RCAN0, RCAN1, IEBC, CD_ROMD,
|
||||
NFMC, SDHI, RTC,
|
||||
SRCC0, SRCC1, DCOMU, OFFI, IFEI,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
|
||||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
|
||||
INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
|
||||
INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
|
||||
INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
|
||||
INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
|
||||
INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
|
||||
INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
|
||||
INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
|
||||
INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
|
||||
INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
|
||||
INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
|
||||
INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
|
||||
INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
|
||||
INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
|
||||
INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
|
||||
INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
|
||||
INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
|
||||
|
||||
INTC_IRQ(USB, 170),
|
||||
INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
|
||||
INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
|
||||
INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
|
||||
INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
|
||||
|
||||
INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
|
||||
INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
|
||||
INTC_IRQ(MTU0_VEF, 183),
|
||||
INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
|
||||
INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
|
||||
INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
|
||||
INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
|
||||
INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
|
||||
INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
|
||||
INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
|
||||
INTC_IRQ(MTU3_TCI3V, 198),
|
||||
INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
|
||||
INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
|
||||
INTC_IRQ(MTU4_TCI4V, 203),
|
||||
|
||||
INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
|
||||
|
||||
INTC_IRQ(ADC_ADI, 206),
|
||||
|
||||
INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
|
||||
INTC_IRQ(SSIF0, 209),
|
||||
INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
|
||||
INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
|
||||
INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
|
||||
|
||||
INTC_IRQ(RSPDIF, 216),
|
||||
|
||||
INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
|
||||
INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
|
||||
INTC_IRQ(IIC30, 221),
|
||||
INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
|
||||
INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
|
||||
INTC_IRQ(IIC31, 226),
|
||||
INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
|
||||
INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
|
||||
INTC_IRQ(IIC32, 231),
|
||||
|
||||
INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
|
||||
INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
|
||||
INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
|
||||
INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
|
||||
INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
|
||||
INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
|
||||
INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
|
||||
INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
|
||||
INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
|
||||
INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
|
||||
INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
|
||||
INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
|
||||
INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
|
||||
INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
|
||||
INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
|
||||
INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
|
||||
|
||||
INTC_IRQ(SIO_FIFO, 264),
|
||||
|
||||
INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
|
||||
INTC_IRQ(RSPIC0, 267),
|
||||
INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
|
||||
INTC_IRQ(RSPIC1, 270),
|
||||
|
||||
INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
|
||||
INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
|
||||
INTC_IRQ(RCAN0, 275),
|
||||
INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
|
||||
INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
|
||||
INTC_IRQ(RCAN1, 280),
|
||||
|
||||
INTC_IRQ(IEBC, 281),
|
||||
|
||||
INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
|
||||
INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
|
||||
INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
|
||||
|
||||
INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
|
||||
INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
|
||||
|
||||
INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
|
||||
INTC_IRQ(SDHI, 294),
|
||||
|
||||
INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
|
||||
INTC_IRQ(RTC, 298),
|
||||
|
||||
INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
|
||||
INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
|
||||
INTC_IRQ(SRCC0, 303),
|
||||
INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
|
||||
INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
|
||||
INTC_IRQ(SRCC1, 308),
|
||||
|
||||
INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
|
||||
INTC_IRQ(DCOMU, 312),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
|
||||
INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
|
||||
INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
|
||||
INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
|
||||
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
|
||||
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
|
||||
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
|
||||
DMAC10, DMAC11 } },
|
||||
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
|
||||
DMAC14, DMAC15 } },
|
||||
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
|
||||
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
|
||||
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
|
||||
MTU2_AB, MTU2_VU } },
|
||||
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
|
||||
MTU4_ABCD, MTU4_TCI4V } },
|
||||
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
|
||||
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
|
||||
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
|
||||
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
|
||||
{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
|
||||
{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
|
||||
{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
|
||||
{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
|
||||
{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe0808, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif0_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8000, 0x100),
|
||||
DEFINE_RES_IRQ(233),
|
||||
DEFINE_RES_IRQ(234),
|
||||
DEFINE_RES_IRQ(235),
|
||||
DEFINE_RES_IRQ(232),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.resource = scif0_resources,
|
||||
.num_resources = ARRAY_SIZE(scif0_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif1_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe8800, 0x100),
|
||||
DEFINE_RES_IRQ(237),
|
||||
DEFINE_RES_IRQ(238),
|
||||
DEFINE_RES_IRQ(239),
|
||||
DEFINE_RES_IRQ(236),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.resource = scif1_resources,
|
||||
.num_resources = ARRAY_SIZE(scif1_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9000, 0x100),
|
||||
DEFINE_RES_IRQ(241),
|
||||
DEFINE_RES_IRQ(242),
|
||||
DEFINE_RES_IRQ(243),
|
||||
DEFINE_RES_IRQ(240),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.resource = scif2_resources,
|
||||
.num_resources = ARRAY_SIZE(scif2_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif3_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe9800, 0x100),
|
||||
DEFINE_RES_IRQ(245),
|
||||
DEFINE_RES_IRQ(246),
|
||||
DEFINE_RES_IRQ(247),
|
||||
DEFINE_RES_IRQ(244),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.resource = scif3_resources,
|
||||
.num_resources = ARRAY_SIZE(scif3_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif4_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif4_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffea000, 0x100),
|
||||
DEFINE_RES_IRQ(249),
|
||||
DEFINE_RES_IRQ(250),
|
||||
DEFINE_RES_IRQ(251),
|
||||
DEFINE_RES_IRQ(248),
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 4,
|
||||
.resource = scif4_resources,
|
||||
.num_resources = ARRAY_SIZE(scif4_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif4_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif5_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif5_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffea800, 0x100),
|
||||
DEFINE_RES_IRQ(253),
|
||||
DEFINE_RES_IRQ(254),
|
||||
DEFINE_RES_IRQ(255),
|
||||
DEFINE_RES_IRQ(252),
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 5,
|
||||
.resource = scif5_resources,
|
||||
.num_resources = ARRAY_SIZE(scif5_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif5_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif6_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif6_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffeb000, 0x100),
|
||||
DEFINE_RES_IRQ(257),
|
||||
DEFINE_RES_IRQ(258),
|
||||
DEFINE_RES_IRQ(259),
|
||||
DEFINE_RES_IRQ(256),
|
||||
};
|
||||
|
||||
static struct platform_device scif6_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 6,
|
||||
.resource = scif6_resources,
|
||||
.num_resources = ARRAY_SIZE(scif6_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif6_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif7_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif7_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffeb800, 0x100),
|
||||
DEFINE_RES_IRQ(261),
|
||||
DEFINE_RES_IRQ(262),
|
||||
DEFINE_RES_IRQ(263),
|
||||
DEFINE_RES_IRQ(260),
|
||||
};
|
||||
|
||||
static struct platform_device scif7_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 7,
|
||||
.resource = scif7_resources,
|
||||
.num_resources = ARRAY_SIZE(scif7_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif7_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt_platform_data = {
|
||||
.channels_mask = 3,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffec000, 0x10),
|
||||
DEFINE_RES_IRQ(175),
|
||||
DEFINE_RES_IRQ(176),
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh-cmt-16",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct resource mtu2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe4000, 0x400),
|
||||
DEFINE_RES_IRQ_NAMED(179, "tgi0a"),
|
||||
DEFINE_RES_IRQ_NAMED(186, "tgi1a"),
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_device = {
|
||||
.name = "sh-mtu2",
|
||||
.id = -1,
|
||||
.resource = mtu2_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_resources),
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe6000,
|
||||
.end = 0xfffe6000 + 0x30 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 296,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
/* USB Host */
|
||||
static void usb_port_power(int port, int power)
|
||||
{
|
||||
__raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
|
||||
}
|
||||
|
||||
static struct r8a66597_platdata r8a66597_data = {
|
||||
.on_chip = 1,
|
||||
.endian = 1,
|
||||
.port_power = usb_port_power,
|
||||
};
|
||||
|
||||
static struct resource r8a66597_usb_host_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffffc000,
|
||||
.end = 0xffffc0e4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 170,
|
||||
.end = 170,
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device r8a66597_usb_host_device = {
|
||||
.name = "r8a66597_hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = NULL, /* not use dma */
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &r8a66597_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
|
||||
.resource = r8a66597_usb_host_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7264_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
&rtc_device,
|
||||
&r8a66597_usb_host_device,
|
||||
};
|
||||
|
||||
static int __init sh7264_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7264_devices,
|
||||
ARRAY_SIZE(sh7264_devices));
|
||||
}
|
||||
arch_initcall(sh7264_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *sh7264_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
early_platform_add_devices(sh7264_early_devices,
|
||||
ARRAY_SIZE(sh7264_early_devices));
|
||||
}
|
||||
586
arch/sh/kernel/cpu/sh2a/setup-sh7269.c
Normal file
586
arch/sh/kernel/cpu/sh2a/setup-sh7269.c
Normal file
|
|
@ -0,0 +1,586 @@
|
|||
/*
|
||||
* SH7269 Setup
|
||||
*
|
||||
* Copyright (C) 2012 Renesas Electronics Europe Ltd
|
||||
* Copyright (C) 2012 Phil Edworthy
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/usb/r8a66597.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
enum {
|
||||
UNUSED = 0,
|
||||
|
||||
/* interrupt sources */
|
||||
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
||||
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
|
||||
|
||||
DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
|
||||
DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
|
||||
USB, VDC4, CMT0, CMT1, BSC, WDT,
|
||||
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
|
||||
PWMT1, PWMT2, ADC_ADI,
|
||||
SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
|
||||
RSPDIF,
|
||||
IIC30, IIC31, IIC32, IIC33,
|
||||
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
|
||||
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
|
||||
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
|
||||
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
|
||||
SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
|
||||
SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
|
||||
SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
|
||||
SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
|
||||
RCAN0, RCAN1, RCAN2,
|
||||
RSPIC0, RSPIC1,
|
||||
IEBC, CD_ROMD,
|
||||
NFMC,
|
||||
SDHI0, SDHI1,
|
||||
RTC,
|
||||
SRCC0, SRCC1, SRCC2,
|
||||
|
||||
/* interrupt groups */
|
||||
PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
|
||||
};
|
||||
|
||||
static struct intc_vect vectors[] __initdata = {
|
||||
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
|
||||
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
|
||||
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
|
||||
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
|
||||
|
||||
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
|
||||
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
|
||||
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
|
||||
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
|
||||
|
||||
INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
|
||||
INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
|
||||
INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
|
||||
INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
|
||||
INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
|
||||
INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
|
||||
INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
|
||||
INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
|
||||
INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
|
||||
INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
|
||||
INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
|
||||
INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
|
||||
INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
|
||||
INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
|
||||
INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
|
||||
INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
|
||||
|
||||
INTC_IRQ(USB, 170),
|
||||
|
||||
INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
|
||||
INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
|
||||
INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
|
||||
INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
|
||||
|
||||
INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
|
||||
|
||||
INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
|
||||
|
||||
INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
|
||||
INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
|
||||
INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
|
||||
INTC_IRQ(MTU0_VEF, 198),
|
||||
INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
|
||||
INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
|
||||
INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
|
||||
INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
|
||||
INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
|
||||
INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
|
||||
INTC_IRQ(MTU3_TCI3V, 211),
|
||||
INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
|
||||
INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
|
||||
INTC_IRQ(MTU4_TCI4V, 216),
|
||||
|
||||
INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
|
||||
|
||||
INTC_IRQ(ADC_ADI, 223),
|
||||
|
||||
INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
|
||||
INTC_IRQ(SSIF0, 226),
|
||||
INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
|
||||
INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
|
||||
INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
|
||||
INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
|
||||
INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
|
||||
|
||||
INTC_IRQ(RSPDIF, 237),
|
||||
|
||||
INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
|
||||
INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
|
||||
INTC_IRQ(IIC30, 242),
|
||||
INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
|
||||
INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
|
||||
INTC_IRQ(IIC31, 247),
|
||||
INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
|
||||
INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
|
||||
INTC_IRQ(IIC32, 252),
|
||||
INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
|
||||
INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
|
||||
INTC_IRQ(IIC33, 257),
|
||||
|
||||
INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
|
||||
INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
|
||||
INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
|
||||
INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
|
||||
INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
|
||||
INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
|
||||
INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
|
||||
INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
|
||||
INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
|
||||
INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
|
||||
INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
|
||||
INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
|
||||
INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
|
||||
INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
|
||||
INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
|
||||
INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
|
||||
|
||||
INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
|
||||
INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
|
||||
INTC_IRQ(RCAN0, 295),
|
||||
INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
|
||||
INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
|
||||
INTC_IRQ(RCAN1, 300),
|
||||
INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
|
||||
INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
|
||||
INTC_IRQ(RCAN2, 305),
|
||||
|
||||
INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
|
||||
INTC_IRQ(RSPIC0, 308),
|
||||
INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
|
||||
INTC_IRQ(RSPIC1, 311),
|
||||
|
||||
INTC_IRQ(IEBC, 318),
|
||||
|
||||
INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
|
||||
INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
|
||||
INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
|
||||
|
||||
INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
|
||||
INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
|
||||
|
||||
INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
|
||||
INTC_IRQ(SDHI0, 334),
|
||||
INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
|
||||
INTC_IRQ(SDHI1, 337),
|
||||
|
||||
INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
|
||||
INTC_IRQ(RTC, 340),
|
||||
|
||||
INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
|
||||
INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
|
||||
INTC_IRQ(SRCC0, 345),
|
||||
INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
|
||||
INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
|
||||
INTC_IRQ(SRCC1, 350),
|
||||
INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
|
||||
INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
|
||||
INTC_IRQ(SRCC2, 355),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
|
||||
PINT4, PINT5, PINT6, PINT7),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
|
||||
INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
|
||||
INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
|
||||
INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
|
||||
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
|
||||
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
|
||||
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
|
||||
DMAC10, DMAC11 } },
|
||||
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
|
||||
DMAC14, DMAC15 } },
|
||||
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
|
||||
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
|
||||
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
|
||||
MTU1_AB, MTU1_VU } },
|
||||
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
|
||||
MTU3_ABCD, MTU3_TCI3V } },
|
||||
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
|
||||
PWMT1, PWMT2 } },
|
||||
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
|
||||
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
|
||||
{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} },
|
||||
{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
|
||||
{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
|
||||
{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
|
||||
{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
|
||||
{ 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
|
||||
{ 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
|
||||
{ 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
|
||||
{ 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe0808, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe8007000, 0x100),
|
||||
DEFINE_RES_IRQ(259),
|
||||
DEFINE_RES_IRQ(260),
|
||||
DEFINE_RES_IRQ(261),
|
||||
DEFINE_RES_IRQ(258),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.resource = scif0_resources,
|
||||
.num_resources = ARRAY_SIZE(scif0_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif1_resources[] = {
|
||||
DEFINE_RES_MEM(0xe8007800, 0x100),
|
||||
DEFINE_RES_IRQ(263),
|
||||
DEFINE_RES_IRQ(264),
|
||||
DEFINE_RES_IRQ(265),
|
||||
DEFINE_RES_IRQ(262),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.resource = scif1_resources,
|
||||
.num_resources = ARRAY_SIZE(scif1_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif2_resources[] = {
|
||||
DEFINE_RES_MEM(0xe8008000, 0x100),
|
||||
DEFINE_RES_IRQ(267),
|
||||
DEFINE_RES_IRQ(268),
|
||||
DEFINE_RES_IRQ(269),
|
||||
DEFINE_RES_IRQ(266),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.resource = scif2_resources,
|
||||
.num_resources = ARRAY_SIZE(scif2_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif3_resources[] = {
|
||||
DEFINE_RES_MEM(0xe8008800, 0x100),
|
||||
DEFINE_RES_IRQ(271),
|
||||
DEFINE_RES_IRQ(272),
|
||||
DEFINE_RES_IRQ(273),
|
||||
DEFINE_RES_IRQ(270),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.resource = scif3_resources,
|
||||
.num_resources = ARRAY_SIZE(scif3_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif4_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif4_resources[] = {
|
||||
DEFINE_RES_MEM(0xe8009000, 0x100),
|
||||
DEFINE_RES_IRQ(275),
|
||||
DEFINE_RES_IRQ(276),
|
||||
DEFINE_RES_IRQ(277),
|
||||
DEFINE_RES_IRQ(274),
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 4,
|
||||
.resource = scif4_resources,
|
||||
.num_resources = ARRAY_SIZE(scif4_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif4_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif5_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif5_resources[] = {
|
||||
DEFINE_RES_MEM(0xe8009800, 0x100),
|
||||
DEFINE_RES_IRQ(279),
|
||||
DEFINE_RES_IRQ(280),
|
||||
DEFINE_RES_IRQ(281),
|
||||
DEFINE_RES_IRQ(278),
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 5,
|
||||
.resource = scif5_resources,
|
||||
.num_resources = ARRAY_SIZE(scif5_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif5_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif6_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif6_resources[] = {
|
||||
DEFINE_RES_MEM(0xe800a000, 0x100),
|
||||
DEFINE_RES_IRQ(283),
|
||||
DEFINE_RES_IRQ(284),
|
||||
DEFINE_RES_IRQ(285),
|
||||
DEFINE_RES_IRQ(282),
|
||||
};
|
||||
|
||||
static struct platform_device scif6_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 6,
|
||||
.resource = scif6_resources,
|
||||
.num_resources = ARRAY_SIZE(scif6_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif6_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif7_platform_data = {
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||||
SCSCR_REIE | SCSCR_TOIE,
|
||||
.type = PORT_SCIF,
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||||
};
|
||||
|
||||
static struct resource scif7_resources[] = {
|
||||
DEFINE_RES_MEM(0xe800a800, 0x100),
|
||||
DEFINE_RES_IRQ(287),
|
||||
DEFINE_RES_IRQ(288),
|
||||
DEFINE_RES_IRQ(289),
|
||||
DEFINE_RES_IRQ(286),
|
||||
};
|
||||
|
||||
static struct platform_device scif7_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 7,
|
||||
.resource = scif7_resources,
|
||||
.num_resources = ARRAY_SIZE(scif7_resources),
|
||||
.dev = {
|
||||
.platform_data = &scif7_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_timer_config cmt_platform_data = {
|
||||
.channels_mask = 3,
|
||||
};
|
||||
|
||||
static struct resource cmt_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffec000, 0x10),
|
||||
DEFINE_RES_IRQ(188),
|
||||
DEFINE_RES_IRQ(189),
|
||||
};
|
||||
|
||||
static struct platform_device cmt_device = {
|
||||
.name = "sh-cmt-16",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &cmt_platform_data,
|
||||
},
|
||||
.resource = cmt_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt_resources),
|
||||
};
|
||||
|
||||
static struct resource mtu2_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffe4000, 0x400),
|
||||
DEFINE_RES_IRQ_NAMED(192, "tgi0a"),
|
||||
DEFINE_RES_IRQ_NAMED(203, "tgi1a"),
|
||||
};
|
||||
|
||||
static struct platform_device mtu2_device = {
|
||||
.name = "sh-mtu2",
|
||||
.id = -1,
|
||||
.resource = mtu2_resources,
|
||||
.num_resources = ARRAY_SIZE(mtu2_resources),
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfffe6000,
|
||||
.end = 0xfffe6000 + 0x30 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 338,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
/* USB Host */
|
||||
static struct r8a66597_platdata r8a66597_data = {
|
||||
.on_chip = 1,
|
||||
.endian = 1,
|
||||
};
|
||||
|
||||
static struct resource r8a66597_usb_host_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xe8010000,
|
||||
.end = 0xe80100e4,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 170,
|
||||
.end = 170,
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device r8a66597_usb_host_device = {
|
||||
.name = "r8a66597_hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = NULL, /* not use dma */
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &r8a66597_data,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
|
||||
.resource = r8a66597_usb_host_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7269_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
&rtc_device,
|
||||
&r8a66597_usb_host_device,
|
||||
};
|
||||
|
||||
static int __init sh7269_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7269_devices,
|
||||
ARRAY_SIZE(sh7269_devices));
|
||||
}
|
||||
arch_initcall(sh7269_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
static struct platform_device *sh7269_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&cmt_device,
|
||||
&mtu2_device,
|
||||
};
|
||||
|
||||
void __init plat_early_device_setup(void)
|
||||
{
|
||||
early_platform_add_devices(sh7269_early_devices,
|
||||
ARRAY_SIZE(sh7269_early_devices));
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue