mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 23:58:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
429
arch/sh/kernel/cpu/sh4/fpu.c
Normal file
429
arch/sh/kernel/cpu/sh4/fpu.c
Normal file
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@ -0,0 +1,429 @@
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/*
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* Save/restore floating point context for signal handlers.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
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* Copyright (C) 2006 ST Microelectronics Ltd. (denorm support)
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*
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* FIXME! These routines have not been tested for big endian case.
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*/
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/io.h>
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#include <cpu/fpu.h>
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#include <asm/processor.h>
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#include <asm/fpu.h>
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#include <asm/traps.h>
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/* The PR (precision) bit in the FP Status Register must be clear when
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* an frchg instruction is executed, otherwise the instruction is undefined.
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* Executing frchg with PR set causes a trap on some SH4 implementations.
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*/
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#define FPSCR_RCHG 0x00000000
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extern unsigned long long float64_div(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_div(unsigned long int a, unsigned long int b);
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extern unsigned long long float64_mul(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_mul(unsigned long int a, unsigned long int b);
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extern unsigned long long float64_add(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_add(unsigned long int a, unsigned long int b);
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extern unsigned long long float64_sub(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_sub(unsigned long int a, unsigned long int b);
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extern unsigned long int float64_to_float32(unsigned long long a);
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static unsigned int fpu_exception_flags;
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/*
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* Save FPU registers onto task structure.
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*/
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void save_fpu(struct task_struct *tsk)
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{
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unsigned long dummy;
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enable_fpu();
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asm volatile ("sts.l fpul, @-%0\n\t"
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"sts.l fpscr, @-%0\n\t"
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"lds %2, fpscr\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"lds %3, fpscr\n\t":"=r" (dummy)
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:"0"((char *)(&tsk->thread.xstate->hardfpu.status)),
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"r"(FPSCR_RCHG), "r"(FPSCR_INIT)
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:"memory");
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disable_fpu();
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}
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void restore_fpu(struct task_struct *tsk)
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{
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unsigned long dummy;
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enable_fpu();
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asm volatile ("lds %2, fpscr\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"lds.l @%0+, fpscr\n\t"
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"lds.l @%0+, fpul\n\t"
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:"=r" (dummy)
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:"0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
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:"memory");
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disable_fpu();
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}
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/**
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* denormal_to_double - Given denormalized float number,
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* store double float
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*
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* @fpu: Pointer to sh_fpu_hard structure
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* @n: Index to FP register
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*/
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static void denormal_to_double(struct sh_fpu_hard_struct *fpu, int n)
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{
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unsigned long du, dl;
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unsigned long x = fpu->fpul;
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int exp = 1023 - 126;
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if (x != 0 && (x & 0x7f800000) == 0) {
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du = (x & 0x80000000);
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while ((x & 0x00800000) == 0) {
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x <<= 1;
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exp--;
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}
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x &= 0x007fffff;
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du |= (exp << 20) | (x >> 3);
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dl = x << 29;
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fpu->fp_regs[n] = du;
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fpu->fp_regs[n + 1] = dl;
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}
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}
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/**
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* ieee_fpe_handler - Handle denormalized number exception
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*
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* @regs: Pointer to register structure
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*
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* Returns 1 when it's handled (should not cause exception).
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*/
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static int ieee_fpe_handler(struct pt_regs *regs)
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{
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unsigned short insn = *(unsigned short *)regs->pc;
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unsigned short finsn;
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unsigned long nextpc;
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int nib[4] = {
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(insn >> 12) & 0xf,
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(insn >> 8) & 0xf,
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(insn >> 4) & 0xf,
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insn & 0xf
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};
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if (nib[0] == 0xb || (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb))
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regs->pr = regs->pc + 4; /* bsr & jsr */
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if (nib[0] == 0xa || nib[0] == 0xb) {
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/* bra & bsr */
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nextpc = regs->pc + 4 + ((short)((insn & 0xfff) << 4) >> 3);
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finsn = *(unsigned short *)(regs->pc + 2);
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} else if (nib[0] == 0x8 && nib[1] == 0xd) {
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/* bt/s */
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if (regs->sr & 1)
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nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1);
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else
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nextpc = regs->pc + 4;
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finsn = *(unsigned short *)(regs->pc + 2);
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} else if (nib[0] == 0x8 && nib[1] == 0xf) {
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/* bf/s */
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if (regs->sr & 1)
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nextpc = regs->pc + 4;
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else
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nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1);
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finsn = *(unsigned short *)(regs->pc + 2);
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} else if (nib[0] == 0x4 && nib[3] == 0xb &&
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(nib[2] == 0x0 || nib[2] == 0x2)) {
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/* jmp & jsr */
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nextpc = regs->regs[nib[1]];
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finsn = *(unsigned short *)(regs->pc + 2);
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} else if (nib[0] == 0x0 && nib[3] == 0x3 &&
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(nib[2] == 0x0 || nib[2] == 0x2)) {
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/* braf & bsrf */
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nextpc = regs->pc + 4 + regs->regs[nib[1]];
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finsn = *(unsigned short *)(regs->pc + 2);
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} else if (insn == 0x000b) {
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/* rts */
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nextpc = regs->pr;
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finsn = *(unsigned short *)(regs->pc + 2);
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} else {
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nextpc = regs->pc + instruction_size(insn);
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finsn = insn;
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}
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if ((finsn & 0xf1ff) == 0xf0ad) {
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/* fcnvsd */
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struct task_struct *tsk = current;
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if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR))
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/* FPU error */
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denormal_to_double(&tsk->thread.xstate->hardfpu,
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(finsn >> 8) & 0xf);
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else
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return 0;
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regs->pc = nextpc;
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return 1;
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} else if ((finsn & 0xf00f) == 0xf002) {
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/* fmul */
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struct task_struct *tsk = current;
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int fpscr;
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int n, m, prec;
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unsigned int hx, hy;
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n = (finsn >> 8) & 0xf;
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m = (finsn >> 4) & 0xf;
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hx = tsk->thread.xstate->hardfpu.fp_regs[n];
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hy = tsk->thread.xstate->hardfpu.fp_regs[m];
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fpscr = tsk->thread.xstate->hardfpu.fpscr;
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prec = fpscr & FPSCR_DBL_PRECISION;
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if ((fpscr & FPSCR_CAUSE_ERROR)
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&& (prec && ((hx & 0x7fffffff) < 0x00100000
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|| (hy & 0x7fffffff) < 0x00100000))) {
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long long llx, lly;
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/* FPU error because of denormal (doubles) */
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llx = ((long long)hx << 32)
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| tsk->thread.xstate->hardfpu.fp_regs[n + 1];
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lly = ((long long)hy << 32)
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| tsk->thread.xstate->hardfpu.fp_regs[m + 1];
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llx = float64_mul(llx, lly);
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tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
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tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
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} else if ((fpscr & FPSCR_CAUSE_ERROR)
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&& (!prec && ((hx & 0x7fffffff) < 0x00800000
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|| (hy & 0x7fffffff) < 0x00800000))) {
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/* FPU error because of denormal (floats) */
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hx = float32_mul(hx, hy);
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tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
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} else
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return 0;
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regs->pc = nextpc;
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return 1;
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} else if ((finsn & 0xf00e) == 0xf000) {
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/* fadd, fsub */
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struct task_struct *tsk = current;
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int fpscr;
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int n, m, prec;
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unsigned int hx, hy;
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n = (finsn >> 8) & 0xf;
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m = (finsn >> 4) & 0xf;
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hx = tsk->thread.xstate->hardfpu.fp_regs[n];
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hy = tsk->thread.xstate->hardfpu.fp_regs[m];
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fpscr = tsk->thread.xstate->hardfpu.fpscr;
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prec = fpscr & FPSCR_DBL_PRECISION;
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if ((fpscr & FPSCR_CAUSE_ERROR)
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&& (prec && ((hx & 0x7fffffff) < 0x00100000
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|| (hy & 0x7fffffff) < 0x00100000))) {
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long long llx, lly;
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/* FPU error because of denormal (doubles) */
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llx = ((long long)hx << 32)
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| tsk->thread.xstate->hardfpu.fp_regs[n + 1];
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lly = ((long long)hy << 32)
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| tsk->thread.xstate->hardfpu.fp_regs[m + 1];
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if ((finsn & 0xf00f) == 0xf000)
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llx = float64_add(llx, lly);
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else
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llx = float64_sub(llx, lly);
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tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
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tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
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} else if ((fpscr & FPSCR_CAUSE_ERROR)
|
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&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
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|| (hy & 0x7fffffff) < 0x00800000))) {
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/* FPU error because of denormal (floats) */
|
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if ((finsn & 0xf00f) == 0xf000)
|
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hx = float32_add(hx, hy);
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else
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hx = float32_sub(hx, hy);
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tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
|
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} else
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return 0;
|
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regs->pc = nextpc;
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return 1;
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} else if ((finsn & 0xf003) == 0xf003) {
|
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/* fdiv */
|
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struct task_struct *tsk = current;
|
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int fpscr;
|
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int n, m, prec;
|
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unsigned int hx, hy;
|
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|
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n = (finsn >> 8) & 0xf;
|
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m = (finsn >> 4) & 0xf;
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hx = tsk->thread.xstate->hardfpu.fp_regs[n];
|
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hy = tsk->thread.xstate->hardfpu.fp_regs[m];
|
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fpscr = tsk->thread.xstate->hardfpu.fpscr;
|
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prec = fpscr & FPSCR_DBL_PRECISION;
|
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|
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if ((fpscr & FPSCR_CAUSE_ERROR)
|
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&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
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|| (hy & 0x7fffffff) < 0x00100000))) {
|
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long long llx, lly;
|
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|
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/* FPU error because of denormal (doubles) */
|
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llx = ((long long)hx << 32)
|
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| tsk->thread.xstate->hardfpu.fp_regs[n + 1];
|
||||
lly = ((long long)hy << 32)
|
||||
| tsk->thread.xstate->hardfpu.fp_regs[m + 1];
|
||||
|
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llx = float64_div(llx, lly);
|
||||
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_CAUSE_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
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/* FPU error because of denormal (floats) */
|
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hx = float32_div(hx, hy);
|
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tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
|
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} else
|
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return 0;
|
||||
|
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regs->pc = nextpc;
|
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return 1;
|
||||
} else if ((finsn & 0xf0bd) == 0xf0bd) {
|
||||
/* fcnvds - double to single precision convert */
|
||||
struct task_struct *tsk = current;
|
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int m;
|
||||
unsigned int hx;
|
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|
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m = (finsn >> 8) & 0x7;
|
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hx = tsk->thread.xstate->hardfpu.fp_regs[m];
|
||||
|
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if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR)
|
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&& ((hx & 0x7fffffff) < 0x00100000)) {
|
||||
/* subnormal double to float conversion */
|
||||
long long llx;
|
||||
|
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llx = ((long long)tsk->thread.xstate->hardfpu.fp_regs[m] << 32)
|
||||
| tsk->thread.xstate->hardfpu.fp_regs[m + 1];
|
||||
|
||||
tsk->thread.xstate->hardfpu.fpul = float64_to_float32(llx);
|
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} else
|
||||
return 0;
|
||||
|
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regs->pc = nextpc;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void float_raise(unsigned int flags)
|
||||
{
|
||||
fpu_exception_flags |= flags;
|
||||
}
|
||||
|
||||
int float_rounding_mode(void)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.xstate->hardfpu.fpscr);
|
||||
return roundingMode;
|
||||
}
|
||||
|
||||
BUILD_TRAP_HANDLER(fpu_error)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
__unlazy_fpu(tsk, regs);
|
||||
fpu_exception_flags = 0;
|
||||
if (ieee_fpe_handler(regs)) {
|
||||
tsk->thread.xstate->hardfpu.fpscr &=
|
||||
~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
|
||||
tsk->thread.xstate->hardfpu.fpscr |= fpu_exception_flags;
|
||||
/* Set the FPSCR flag as well as cause bits - simply
|
||||
* replicate the cause */
|
||||
tsk->thread.xstate->hardfpu.fpscr |= (fpu_exception_flags >> 10);
|
||||
grab_fpu(regs);
|
||||
restore_fpu(tsk);
|
||||
task_thread_info(tsk)->status |= TS_USEDFPU;
|
||||
if ((((tsk->thread.xstate->hardfpu.fpscr & FPSCR_ENABLE_MASK) >> 7) &
|
||||
(fpu_exception_flags >> 2)) == 0) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
force_sig(SIGFPE, tsk);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue