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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 23:58:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
298
arch/sh/kernel/cpu/sh4/setup-sh7760.c
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298
arch/sh/kernel/cpu/sh4/setup-sh7760.c
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/*
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* SH7760 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/sh_timer.h>
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#include <linux/sh_intc.h>
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#include <linux/serial_sci.h>
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#include <linux/io.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL0, IRL1, IRL2, IRL3,
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HUDI, GPIOI, DMAC,
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IRQ4, IRQ5, IRQ6, IRQ7,
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HCAN20, HCAN21,
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SSI0, SSI1,
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HAC0, HAC1,
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I2C0, I2C1,
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USB, LCDC,
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DMABRG0, DMABRG1, DMABRG2,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
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SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
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HSPI,
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MMCIF0, MMCIF1, MMCIF2, MMCIF3,
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MFI, ADC, CMT,
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TMU0, TMU1, TMU2,
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WDT, REF,
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/* interrupt groups */
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DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
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INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
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INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
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INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
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INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
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INTC_VECT(DMAC, 0x6c0),
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INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
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INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
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INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
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INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
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INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
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INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
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INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
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INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
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INTC_VECT(DMABRG2, 0xac0),
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INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
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INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
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INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
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INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
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INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
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INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
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INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
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INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
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INTC_VECT(HSPI, 0xc80),
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INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
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INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
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INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
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INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
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INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
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INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
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{ IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
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SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
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0, DMABRG0, DMABRG1, DMABRG2,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
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{ 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
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HSPI, MMCIF0, MMCIF1, MMCIF2,
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MMCIF3, 0, 0, 0, 0, 0, 0, 0,
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0, MFI, 0, 0, 0, 0, ADC, CMT, } },
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
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{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
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{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
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{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
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{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
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HAC0, HAC1, I2C0, I2C1 } },
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{ 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
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SCIF1, SCIF2, SIM, HSPI } },
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{ 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
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MFI, 0, ADC, CMT } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct intc_vect vectors_irq[] __initdata = {
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INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
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INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
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};
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static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
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mask_registers, prio_registers, NULL);
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static struct plat_sci_port scif0_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif0_resources[] = {
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DEFINE_RES_MEM(0xfe600000, 0x100),
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DEFINE_RES_IRQ(evt2irq(0x880)),
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DEFINE_RES_IRQ(evt2irq(0x8a0)),
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DEFINE_RES_IRQ(evt2irq(0x8e0)),
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DEFINE_RES_IRQ(evt2irq(0x8c0)),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.resource = scif0_resources,
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.num_resources = ARRAY_SIZE(scif0_resources),
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif1_resources[] = {
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DEFINE_RES_MEM(0xfe610000, 0x100),
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DEFINE_RES_IRQ(evt2irq(0xb00)),
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DEFINE_RES_IRQ(evt2irq(0xb20)),
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DEFINE_RES_IRQ(evt2irq(0xb60)),
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DEFINE_RES_IRQ(evt2irq(0xb40)),
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.resource = scif1_resources,
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.num_resources = ARRAY_SIZE(scif1_resources),
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct plat_sci_port scif2_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif2_resources[] = {
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DEFINE_RES_MEM(0xfe620000, 0x100),
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DEFINE_RES_IRQ(evt2irq(0xb80)),
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DEFINE_RES_IRQ(evt2irq(0xba0)),
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DEFINE_RES_IRQ(evt2irq(0xbe0)),
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DEFINE_RES_IRQ(evt2irq(0xbc0)),
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.resource = scif2_resources,
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.num_resources = ARRAY_SIZE(scif2_resources),
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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static struct plat_sci_port scif3_platform_data = {
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
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.type = PORT_SCI,
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.regshift = 2,
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};
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static struct resource scif3_resources[] = {
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DEFINE_RES_MEM(0xfe480000, 0x100),
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DEFINE_RES_IRQ(evt2irq(0xc00)),
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DEFINE_RES_IRQ(evt2irq(0xc20)),
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DEFINE_RES_IRQ(evt2irq(0xc40)),
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.resource = scif3_resources,
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.num_resources = ARRAY_SIZE(scif3_resources),
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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static struct sh_timer_config tmu0_platform_data = {
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.channels_mask = 7,
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};
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static struct resource tmu0_resources[] = {
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DEFINE_RES_MEM(0xffd80000, 0x30),
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DEFINE_RES_IRQ(evt2irq(0x400)),
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DEFINE_RES_IRQ(evt2irq(0x420)),
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DEFINE_RES_IRQ(evt2irq(0x440)),
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};
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static struct platform_device tmu0_device = {
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.name = "sh-tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct platform_device *sh7760_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&tmu0_device,
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};
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static int __init sh7760_devices_setup(void)
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{
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return platform_add_devices(sh7760_devices,
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ARRAY_SIZE(sh7760_devices));
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}
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arch_initcall(sh7760_devices_setup);
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static struct platform_device *sh7760_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&tmu0_device,
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};
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void __init plat_early_device_setup(void)
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{
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early_platform_add_devices(sh7760_early_devices,
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ARRAY_SIZE(sh7760_early_devices));
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}
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#define INTC_ICR 0xffd00000UL
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#define INTC_ICR_IRLM (1 << 7)
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void __init plat_irq_setup_pins(int mode)
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{
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switch (mode) {
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case IRQ_MODE_IRQ:
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__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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register_intc_controller(&intc_desc_irq);
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break;
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default:
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BUG();
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}
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}
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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