mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
543
arch/sparc/kernel/cpu.c
Normal file
543
arch/sparc/kernel/cpu.c
Normal file
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@ -0,0 +1,543 @@
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/* cpu.c: Dinky routines to look for the kind of Sparc cpu
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* we are on.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <linux/seq_file.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <asm/spitfire.h>
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#include <asm/pgtable.h>
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#include <asm/oplib.h>
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/head.h>
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#include <asm/psr.h>
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#include <asm/mbus.h>
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#include <asm/cpudata.h>
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#include "kernel.h"
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#include "entry.h"
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DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
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EXPORT_PER_CPU_SYMBOL(__cpu_data);
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int ncpus_probed;
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unsigned int fsr_storage;
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struct cpu_info {
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int psr_vers;
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const char *name;
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const char *pmu_name;
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};
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struct fpu_info {
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int fp_vers;
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const char *name;
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};
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#define NOCPU 8
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#define NOFPU 8
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struct manufacturer_info {
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int psr_impl;
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struct cpu_info cpu_info[NOCPU];
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struct fpu_info fpu_info[NOFPU];
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};
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#define CPU(ver, _name) \
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{ .psr_vers = ver, .name = _name }
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#define CPU_PMU(ver, _name, _pmu_name) \
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{ .psr_vers = ver, .name = _name, .pmu_name = _pmu_name }
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#define FPU(ver, _name) \
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{ .fp_vers = ver, .name = _name }
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static const struct manufacturer_info __initconst manufacturer_info[] = {
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{
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0,
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/* Sun4/100, 4/200, SLC */
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.cpu_info = {
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CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
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/* borned STP1012PGA */
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CPU(4, "Fujitsu MB86904"),
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CPU(5, "Fujitsu TurboSparc MB86907"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"),
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FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"),
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FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"),
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/* SparcStation SLC, SparcStation1 */
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FPU(3, "Weitek WTL3170/2"),
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/* SPARCstation-5 */
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FPU(4, "Lsi Logic/Meiko L64804 or compatible"),
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FPU(-1, NULL)
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}
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},{
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1,
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.cpu_info = {
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/* SparcStation2, SparcServer 490 & 690 */
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CPU(0, "LSI Logic Corporation - L64811"),
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/* SparcStation2 */
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CPU(1, "Cypress/ROSS CY7C601"),
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/* Embedded controller */
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CPU(3, "Cypress/ROSS CY7C611"),
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/* Ross Technologies HyperSparc */
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CPU(0xf, "ROSS HyperSparc RT620"),
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CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0, "ROSS HyperSparc combined IU/FPU"),
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FPU(1, "Lsi Logic L64814"),
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FPU(2, "Texas Instruments TMS390-C602A"),
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FPU(3, "Cypress CY7C602 FPU"),
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FPU(-1, NULL)
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}
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},{
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2,
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.cpu_info = {
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/* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */
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/* Someone please write the code to support this beast! ;) */
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CPU(0, "Bipolar Integrated Technology - B5010"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(-1, NULL)
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}
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},{
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3,
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.cpu_info = {
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CPU(0, "LSI Logic Corporation - unknown-type"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(-1, NULL)
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}
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},{
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PSR_IMPL_TI,
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.cpu_info = {
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CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"),
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/* SparcClassic -- borned STP1010TAB-50*/
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CPU(1, "Texas Instruments, Inc. - MicroSparc"),
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CPU(2, "Texas Instruments, Inc. - MicroSparc II"),
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CPU(3, "Texas Instruments, Inc. - SuperSparc 51"),
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CPU(4, "Texas Instruments, Inc. - SuperSparc 61"),
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CPU(5, "Texas Instruments, Inc. - unknown"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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/* SuperSparc 50 module */
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FPU(0, "SuperSparc on-chip FPU"),
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/* SparcClassic */
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FPU(4, "TI MicroSparc on chip FPU"),
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FPU(-1, NULL)
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}
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},{
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5,
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.cpu_info = {
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CPU(0, "Matsushita - MN10501"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0, "Matsushita MN10501"),
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FPU(-1, NULL)
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}
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},{
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6,
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.cpu_info = {
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CPU(0, "Philips Corporation - unknown"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(-1, NULL)
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}
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},{
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7,
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.cpu_info = {
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CPU(0, "Harvest VLSI Design Center, Inc. - unknown"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(-1, NULL)
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}
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},{
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8,
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.cpu_info = {
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CPU(0, "Systems and Processes Engineering Corporation (SPEC)"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(-1, NULL)
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}
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},{
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9,
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.cpu_info = {
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/* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */
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CPU(0, "Fujitsu or Weitek Power-UP"),
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CPU(1, "Fujitsu or Weitek Power-UP"),
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CPU(2, "Fujitsu or Weitek Power-UP"),
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CPU(3, "Fujitsu or Weitek Power-UP"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(3, "Fujitsu or Weitek on-chip FPU"),
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FPU(-1, NULL)
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}
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},{
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PSR_IMPL_LEON, /* Aeroflex Gaisler */
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.cpu_info = {
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CPU(3, "LEON"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(2, "GRFPU"),
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FPU(3, "GRFPU-Lite"),
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FPU(-1, NULL)
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}
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},{
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0x17,
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.cpu_info = {
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CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
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CPU_PMU(0x11, "TI UltraSparc II (BlackBird)", "ultra12"),
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CPU_PMU(0x12, "TI UltraSparc IIi (Sabre)", "ultra12"),
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CPU_PMU(0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0x10, "UltraSparc I integrated FPU"),
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FPU(0x11, "UltraSparc II integrated FPU"),
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FPU(0x12, "UltraSparc IIi integrated FPU"),
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FPU(0x13, "UltraSparc IIe integrated FPU"),
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FPU(-1, NULL)
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}
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},{
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0x22,
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.cpu_info = {
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CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0x10, "UltraSparc I integrated FPU"),
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FPU(-1, NULL)
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}
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},{
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0x3e,
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.cpu_info = {
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CPU_PMU(0x14, "TI UltraSparc III (Cheetah)", "ultra3"),
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CPU_PMU(0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"),
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CPU_PMU(0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"),
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CPU_PMU(0x18, "TI UltraSparc IV (Jaguar)", "ultra3+"),
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CPU_PMU(0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"),
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CPU_PMU(0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3i"),
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CPU(-1, NULL)
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},
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.fpu_info = {
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FPU(0x14, "UltraSparc III integrated FPU"),
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FPU(0x15, "UltraSparc III+ integrated FPU"),
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FPU(0x16, "UltraSparc IIIi integrated FPU"),
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FPU(0x18, "UltraSparc IV integrated FPU"),
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FPU(0x19, "UltraSparc IV+ integrated FPU"),
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FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
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FPU(-1, NULL)
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}
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}};
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/* In order to get the fpu type correct, you need to take the IDPROM's
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* machine type value into consideration too. I will fix this.
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*/
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static const char *sparc_cpu_type;
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static const char *sparc_fpu_type;
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const char *sparc_pmu_type;
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static void __init set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers)
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{
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const struct manufacturer_info *manuf;
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int i;
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sparc_cpu_type = NULL;
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sparc_fpu_type = NULL;
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sparc_pmu_type = NULL;
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manuf = NULL;
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for (i = 0; i < ARRAY_SIZE(manufacturer_info); i++)
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{
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if (psr_impl == manufacturer_info[i].psr_impl) {
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manuf = &manufacturer_info[i];
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break;
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}
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}
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if (manuf != NULL)
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{
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const struct cpu_info *cpu;
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const struct fpu_info *fpu;
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cpu = &manuf->cpu_info[0];
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while (cpu->psr_vers != -1)
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{
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if (cpu->psr_vers == psr_vers) {
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sparc_cpu_type = cpu->name;
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sparc_pmu_type = cpu->pmu_name;
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sparc_fpu_type = "No FPU";
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break;
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}
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cpu++;
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}
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fpu = &manuf->fpu_info[0];
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while (fpu->fp_vers != -1)
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{
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if (fpu->fp_vers == fpu_vers) {
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sparc_fpu_type = fpu->name;
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break;
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}
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fpu++;
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}
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}
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if (sparc_cpu_type == NULL)
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{
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printk(KERN_ERR "CPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
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psr_impl, psr_vers);
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sparc_cpu_type = "Unknown CPU";
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}
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if (sparc_fpu_type == NULL)
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{
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printk(KERN_ERR "FPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
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psr_impl, fpu_vers);
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sparc_fpu_type = "Unknown FPU";
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}
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if (sparc_pmu_type == NULL)
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sparc_pmu_type = "Unknown PMU";
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}
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|
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#ifdef CONFIG_SPARC32
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static int show_cpuinfo(struct seq_file *m, void *__unused)
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{
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seq_printf(m,
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"cpu\t\t: %s\n"
|
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"fpu\t\t: %s\n"
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"promlib\t\t: Version %d Revision %d\n"
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"prom\t\t: %d.%d\n"
|
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"type\t\t: %s\n"
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"ncpus probed\t: %d\n"
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"ncpus active\t: %d\n"
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#ifndef CONFIG_SMP
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"CPU0Bogo\t: %lu.%02lu\n"
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"CPU0ClkTck\t: %ld\n"
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#endif
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,
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sparc_cpu_type,
|
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sparc_fpu_type ,
|
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romvec->pv_romvers,
|
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prom_rev,
|
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romvec->pv_printrev >> 16,
|
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romvec->pv_printrev & 0xffff,
|
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&cputypval[0],
|
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ncpus_probed,
|
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num_online_cpus()
|
||||
#ifndef CONFIG_SMP
|
||||
, cpu_data(0).udelay_val/(500000/HZ),
|
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(cpu_data(0).udelay_val/(5000/HZ)) % 100,
|
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cpu_data(0).clock_tick
|
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#endif
|
||||
);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_bogo(m);
|
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#endif
|
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mmu_info(m);
|
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#ifdef CONFIG_SMP
|
||||
smp_info(m);
|
||||
#endif
|
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return 0;
|
||||
}
|
||||
#endif /* CONFIG_SPARC32 */
|
||||
|
||||
#ifdef CONFIG_SPARC64
|
||||
unsigned int dcache_parity_tl1_occurred;
|
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unsigned int icache_parity_tl1_occurred;
|
||||
|
||||
|
||||
static int show_cpuinfo(struct seq_file *m, void *__unused)
|
||||
{
|
||||
seq_printf(m,
|
||||
"cpu\t\t: %s\n"
|
||||
"fpu\t\t: %s\n"
|
||||
"pmu\t\t: %s\n"
|
||||
"prom\t\t: %s\n"
|
||||
"type\t\t: %s\n"
|
||||
"ncpus probed\t: %d\n"
|
||||
"ncpus active\t: %d\n"
|
||||
"D$ parity tl1\t: %u\n"
|
||||
"I$ parity tl1\t: %u\n"
|
||||
#ifndef CONFIG_SMP
|
||||
"Cpu0ClkTck\t: %016lx\n"
|
||||
#endif
|
||||
,
|
||||
sparc_cpu_type,
|
||||
sparc_fpu_type,
|
||||
sparc_pmu_type,
|
||||
prom_version,
|
||||
((tlb_type == hypervisor) ?
|
||||
"sun4v" :
|
||||
"sun4u"),
|
||||
ncpus_probed,
|
||||
num_online_cpus(),
|
||||
dcache_parity_tl1_occurred,
|
||||
icache_parity_tl1_occurred
|
||||
#ifndef CONFIG_SMP
|
||||
, cpu_data(0).clock_tick
|
||||
#endif
|
||||
);
|
||||
cpucap_info(m);
|
||||
#ifdef CONFIG_SMP
|
||||
smp_bogo(m);
|
||||
#endif
|
||||
mmu_info(m);
|
||||
#ifdef CONFIG_SMP
|
||||
smp_info(m);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SPARC64 */
|
||||
|
||||
static void *c_start(struct seq_file *m, loff_t *pos)
|
||||
{
|
||||
/* The pointer we are returning is arbitrary,
|
||||
* it just has to be non-NULL and not IS_ERR
|
||||
* in the success case.
|
||||
*/
|
||||
return *pos == 0 ? &c_start : NULL;
|
||||
}
|
||||
|
||||
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
||||
{
|
||||
++*pos;
|
||||
return c_start(m, pos);
|
||||
}
|
||||
|
||||
static void c_stop(struct seq_file *m, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
const struct seq_operations cpuinfo_op = {
|
||||
.start =c_start,
|
||||
.next = c_next,
|
||||
.stop = c_stop,
|
||||
.show = show_cpuinfo,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SPARC32
|
||||
static int __init cpu_type_probe(void)
|
||||
{
|
||||
int psr_impl, psr_vers, fpu_vers;
|
||||
int psr;
|
||||
|
||||
psr_impl = ((get_psr() >> PSR_IMPL_SHIFT) & PSR_IMPL_SHIFTED_MASK);
|
||||
psr_vers = ((get_psr() >> PSR_VERS_SHIFT) & PSR_VERS_SHIFTED_MASK);
|
||||
|
||||
psr = get_psr();
|
||||
put_psr(psr | PSR_EF);
|
||||
|
||||
if (psr_impl == PSR_IMPL_LEON)
|
||||
fpu_vers = get_psr() & PSR_EF ? ((get_fsr() >> 17) & 0x7) : 7;
|
||||
else
|
||||
fpu_vers = ((get_fsr() >> 17) & 0x7);
|
||||
|
||||
put_psr(psr);
|
||||
|
||||
set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SPARC32 */
|
||||
|
||||
#ifdef CONFIG_SPARC64
|
||||
static void __init sun4v_cpu_probe(void)
|
||||
{
|
||||
switch (sun4v_chip_type) {
|
||||
case SUN4V_CHIP_NIAGARA1:
|
||||
sparc_cpu_type = "UltraSparc T1 (Niagara)";
|
||||
sparc_fpu_type = "UltraSparc T1 integrated FPU";
|
||||
sparc_pmu_type = "niagara";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA2:
|
||||
sparc_cpu_type = "UltraSparc T2 (Niagara2)";
|
||||
sparc_fpu_type = "UltraSparc T2 integrated FPU";
|
||||
sparc_pmu_type = "niagara2";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA3:
|
||||
sparc_cpu_type = "UltraSparc T3 (Niagara3)";
|
||||
sparc_fpu_type = "UltraSparc T3 integrated FPU";
|
||||
sparc_pmu_type = "niagara3";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA4:
|
||||
sparc_cpu_type = "UltraSparc T4 (Niagara4)";
|
||||
sparc_fpu_type = "UltraSparc T4 integrated FPU";
|
||||
sparc_pmu_type = "niagara4";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA5:
|
||||
sparc_cpu_type = "UltraSparc T5 (Niagara5)";
|
||||
sparc_fpu_type = "UltraSparc T5 integrated FPU";
|
||||
sparc_pmu_type = "niagara5";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_SPARC_M6:
|
||||
sparc_cpu_type = "SPARC-M6";
|
||||
sparc_fpu_type = "SPARC-M6 integrated FPU";
|
||||
sparc_pmu_type = "sparc-m6";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_SPARC_M7:
|
||||
sparc_cpu_type = "SPARC-M7";
|
||||
sparc_fpu_type = "SPARC-M7 integrated FPU";
|
||||
sparc_pmu_type = "sparc-m7";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_SPARC64X:
|
||||
sparc_cpu_type = "SPARC64-X";
|
||||
sparc_fpu_type = "SPARC64-X integrated FPU";
|
||||
sparc_pmu_type = "sparc64-x";
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
|
||||
prom_cpu_compatible);
|
||||
sparc_cpu_type = "Unknown SUN4V CPU";
|
||||
sparc_fpu_type = "Unknown SUN4V FPU";
|
||||
sparc_pmu_type = "Unknown SUN4V PMU";
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init cpu_type_probe(void)
|
||||
{
|
||||
if (tlb_type == hypervisor) {
|
||||
sun4v_cpu_probe();
|
||||
} else {
|
||||
unsigned long ver;
|
||||
int manuf, impl;
|
||||
|
||||
__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
|
||||
|
||||
manuf = ((ver >> 48) & 0xffff);
|
||||
impl = ((ver >> 32) & 0xffff);
|
||||
set_cpu_and_fpu(manuf, impl, impl);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SPARC64 */
|
||||
|
||||
early_initcall(cpu_type_probe);
|
||||
Loading…
Add table
Add a link
Reference in a new issue