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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
256
arch/sparc/kernel/ebus.c
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256
arch/sparc/kernel/ebus.c
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/* ebus.c: EBUS DMA library code.
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*
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* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <asm/ebus_dma.h>
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#include <asm/io.h>
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#define EBDMA_CSR 0x00UL /* Control/Status */
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#define EBDMA_ADDR 0x04UL /* DMA Address */
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#define EBDMA_COUNT 0x08UL /* DMA Count */
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#define EBDMA_CSR_INT_PEND 0x00000001
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#define EBDMA_CSR_ERR_PEND 0x00000002
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#define EBDMA_CSR_DRAIN 0x00000004
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#define EBDMA_CSR_INT_EN 0x00000010
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#define EBDMA_CSR_RESET 0x00000080
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#define EBDMA_CSR_WRITE 0x00000100
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#define EBDMA_CSR_EN_DMA 0x00000200
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#define EBDMA_CSR_CYC_PEND 0x00000400
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#define EBDMA_CSR_DIAG_RD_DONE 0x00000800
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#define EBDMA_CSR_DIAG_WR_DONE 0x00001000
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#define EBDMA_CSR_EN_CNT 0x00002000
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#define EBDMA_CSR_TC 0x00004000
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#define EBDMA_CSR_DIS_CSR_DRN 0x00010000
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#define EBDMA_CSR_BURST_SZ_MASK 0x000c0000
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#define EBDMA_CSR_BURST_SZ_1 0x00080000
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#define EBDMA_CSR_BURST_SZ_4 0x00000000
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#define EBDMA_CSR_BURST_SZ_8 0x00040000
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#define EBDMA_CSR_BURST_SZ_16 0x000c0000
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#define EBDMA_CSR_DIAG_EN 0x00100000
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#define EBDMA_CSR_DIS_ERR_PEND 0x00400000
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#define EBDMA_CSR_TCI_DIS 0x00800000
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#define EBDMA_CSR_EN_NEXT 0x01000000
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#define EBDMA_CSR_DMA_ON 0x02000000
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#define EBDMA_CSR_A_LOADED 0x04000000
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#define EBDMA_CSR_NA_LOADED 0x08000000
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#define EBDMA_CSR_DEV_ID_MASK 0xf0000000
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#define EBUS_DMA_RESET_TIMEOUT 10000
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static void __ebus_dma_reset(struct ebus_dma_info *p, int no_drain)
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{
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int i;
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u32 val = 0;
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writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR);
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udelay(1);
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if (no_drain)
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return;
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for (i = EBUS_DMA_RESET_TIMEOUT; i > 0; i--) {
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val = readl(p->regs + EBDMA_CSR);
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if (!(val & (EBDMA_CSR_DRAIN | EBDMA_CSR_CYC_PEND)))
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break;
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udelay(10);
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}
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}
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static irqreturn_t ebus_dma_irq(int irq, void *dev_id)
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{
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struct ebus_dma_info *p = dev_id;
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unsigned long flags;
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u32 csr = 0;
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spin_lock_irqsave(&p->lock, flags);
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csr = readl(p->regs + EBDMA_CSR);
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writel(csr, p->regs + EBDMA_CSR);
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spin_unlock_irqrestore(&p->lock, flags);
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if (csr & EBDMA_CSR_ERR_PEND) {
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printk(KERN_CRIT "ebus_dma(%s): DMA error!\n", p->name);
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p->callback(p, EBUS_DMA_EVENT_ERROR, p->client_cookie);
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return IRQ_HANDLED;
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} else if (csr & EBDMA_CSR_INT_PEND) {
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p->callback(p,
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(csr & EBDMA_CSR_TC) ?
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EBUS_DMA_EVENT_DMA : EBUS_DMA_EVENT_DEVICE,
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p->client_cookie);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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int ebus_dma_register(struct ebus_dma_info *p)
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{
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u32 csr;
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if (!p->regs)
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return -EINVAL;
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if (p->flags & ~(EBUS_DMA_FLAG_USE_EBDMA_HANDLER |
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EBUS_DMA_FLAG_TCI_DISABLE))
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return -EINVAL;
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if ((p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) && !p->callback)
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return -EINVAL;
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if (!strlen(p->name))
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return -EINVAL;
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__ebus_dma_reset(p, 1);
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csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT;
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if (p->flags & EBUS_DMA_FLAG_TCI_DISABLE)
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csr |= EBDMA_CSR_TCI_DIS;
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writel(csr, p->regs + EBDMA_CSR);
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return 0;
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}
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EXPORT_SYMBOL(ebus_dma_register);
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int ebus_dma_irq_enable(struct ebus_dma_info *p, int on)
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{
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unsigned long flags;
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u32 csr;
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if (on) {
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if (p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) {
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if (request_irq(p->irq, ebus_dma_irq, IRQF_SHARED, p->name, p))
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return -EBUSY;
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}
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spin_lock_irqsave(&p->lock, flags);
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csr = readl(p->regs + EBDMA_CSR);
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csr |= EBDMA_CSR_INT_EN;
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writel(csr, p->regs + EBDMA_CSR);
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spin_unlock_irqrestore(&p->lock, flags);
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} else {
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spin_lock_irqsave(&p->lock, flags);
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csr = readl(p->regs + EBDMA_CSR);
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csr &= ~EBDMA_CSR_INT_EN;
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writel(csr, p->regs + EBDMA_CSR);
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spin_unlock_irqrestore(&p->lock, flags);
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if (p->flags & EBUS_DMA_FLAG_USE_EBDMA_HANDLER) {
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free_irq(p->irq, p);
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}
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}
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return 0;
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}
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EXPORT_SYMBOL(ebus_dma_irq_enable);
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void ebus_dma_unregister(struct ebus_dma_info *p)
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{
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unsigned long flags;
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u32 csr;
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int irq_on = 0;
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spin_lock_irqsave(&p->lock, flags);
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csr = readl(p->regs + EBDMA_CSR);
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if (csr & EBDMA_CSR_INT_EN) {
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csr &= ~EBDMA_CSR_INT_EN;
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writel(csr, p->regs + EBDMA_CSR);
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irq_on = 1;
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}
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spin_unlock_irqrestore(&p->lock, flags);
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if (irq_on)
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free_irq(p->irq, p);
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}
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EXPORT_SYMBOL(ebus_dma_unregister);
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int ebus_dma_request(struct ebus_dma_info *p, dma_addr_t bus_addr, size_t len)
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{
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unsigned long flags;
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u32 csr;
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int err;
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if (len >= (1 << 24))
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return -EINVAL;
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spin_lock_irqsave(&p->lock, flags);
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csr = readl(p->regs + EBDMA_CSR);
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err = -EINVAL;
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if (!(csr & EBDMA_CSR_EN_DMA))
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goto out;
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err = -EBUSY;
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if (csr & EBDMA_CSR_NA_LOADED)
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goto out;
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writel(len, p->regs + EBDMA_COUNT);
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writel(bus_addr, p->regs + EBDMA_ADDR);
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err = 0;
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out:
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spin_unlock_irqrestore(&p->lock, flags);
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return err;
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}
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EXPORT_SYMBOL(ebus_dma_request);
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void ebus_dma_prepare(struct ebus_dma_info *p, int write)
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{
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unsigned long flags;
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u32 csr;
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spin_lock_irqsave(&p->lock, flags);
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__ebus_dma_reset(p, 0);
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csr = (EBDMA_CSR_INT_EN |
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EBDMA_CSR_EN_CNT |
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EBDMA_CSR_BURST_SZ_16 |
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EBDMA_CSR_EN_NEXT);
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if (write)
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csr |= EBDMA_CSR_WRITE;
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if (p->flags & EBUS_DMA_FLAG_TCI_DISABLE)
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csr |= EBDMA_CSR_TCI_DIS;
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writel(csr, p->regs + EBDMA_CSR);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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EXPORT_SYMBOL(ebus_dma_prepare);
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unsigned int ebus_dma_residue(struct ebus_dma_info *p)
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{
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return readl(p->regs + EBDMA_COUNT);
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}
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EXPORT_SYMBOL(ebus_dma_residue);
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unsigned int ebus_dma_addr(struct ebus_dma_info *p)
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{
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return readl(p->regs + EBDMA_ADDR);
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}
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EXPORT_SYMBOL(ebus_dma_addr);
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void ebus_dma_enable(struct ebus_dma_info *p, int on)
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{
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unsigned long flags;
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u32 orig_csr, csr;
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spin_lock_irqsave(&p->lock, flags);
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orig_csr = csr = readl(p->regs + EBDMA_CSR);
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if (on)
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csr |= EBDMA_CSR_EN_DMA;
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else
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csr &= ~EBDMA_CSR_EN_DMA;
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if ((orig_csr & EBDMA_CSR_EN_DMA) !=
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(csr & EBDMA_CSR_EN_DMA))
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writel(csr, p->regs + EBDMA_CSR);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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EXPORT_SYMBOL(ebus_dma_enable);
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