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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
362
arch/sparc/kernel/irq_32.c
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362
arch/sparc/kernel/irq_32.c
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/*
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* Interrupt request handling routines. On the
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* Sparc the IRQs are basically 'cast in stone'
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* and you are supposed to probe the prom's device
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* node trees to find out who's got which IRQ.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1995,2002 Pete A. Zaitcev (zaitcev@yahoo.com)
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* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
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* Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
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*/
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#include <linux/kernel_stat.h>
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#include <linux/seq_file.h>
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#include <linux/export.h>
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#include <asm/cacheflush.h>
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#include <asm/cpudata.h>
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#include <asm/setup.h>
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#include <asm/pcic.h>
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#include <asm/leon.h>
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#include "kernel.h"
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#include "irq.h"
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/* platform specific irq setup */
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struct sparc_config sparc_config;
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unsigned long arch_local_irq_save(void)
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{
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unsigned long retval;
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unsigned long tmp;
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__asm__ __volatile__(
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"rd %%psr, %0\n\t"
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"or %0, %2, %1\n\t"
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"wr %1, 0, %%psr\n\t"
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"nop; nop; nop\n"
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: "=&r" (retval), "=r" (tmp)
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: "i" (PSR_PIL)
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: "memory");
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return retval;
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}
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EXPORT_SYMBOL(arch_local_irq_save);
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void arch_local_irq_enable(void)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"rd %%psr, %0\n\t"
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"andn %0, %1, %0\n\t"
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"wr %0, 0, %%psr\n\t"
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"nop; nop; nop\n"
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: "=&r" (tmp)
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: "i" (PSR_PIL)
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: "memory");
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}
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EXPORT_SYMBOL(arch_local_irq_enable);
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void arch_local_irq_restore(unsigned long old_psr)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"rd %%psr, %0\n\t"
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"and %2, %1, %2\n\t"
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"andn %0, %1, %0\n\t"
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"wr %0, %2, %%psr\n\t"
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"nop; nop; nop\n"
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: "=&r" (tmp)
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: "i" (PSR_PIL), "r" (old_psr)
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: "memory");
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}
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EXPORT_SYMBOL(arch_local_irq_restore);
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/*
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* Dave Redman (djhr@tadpole.co.uk)
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*
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* IRQ numbers.. These are no longer restricted to 15..
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*
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* this is done to enable SBUS cards and onboard IO to be masked
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* correctly. using the interrupt level isn't good enough.
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*
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* For example:
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* A device interrupting at sbus level6 and the Floppy both come in
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* at IRQ11, but enabling and disabling them requires writing to
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* different bits in the SLAVIO/SEC.
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*
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* As a result of these changes sun4m machines could now support
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* directed CPU interrupts using the existing enable/disable irq code
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* with tweaks.
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*
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* Sun4d complicates things even further. IRQ numbers are arbitrary
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* 32-bit values in that case. Since this is similar to sparc64,
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* we adopt a virtual IRQ numbering scheme as is done there.
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* Virutal interrupt numbers are allocated by build_irq(). So NR_IRQS
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* just becomes a limit of how many interrupt sources we can handle in
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* a single system. Even fully loaded SS2000 machines top off at
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* about 32 interrupt sources or so, therefore a NR_IRQS value of 64
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* is more than enough.
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*
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* We keep a map of per-PIL enable interrupts. These get wired
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* up via the irq_chip->startup() method which gets invoked by
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* the generic IRQ layer during request_irq().
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*/
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/* Table of allocated irqs. Unused entries has irq == 0 */
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static struct irq_bucket irq_table[NR_IRQS];
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/* Protect access to irq_table */
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static DEFINE_SPINLOCK(irq_table_lock);
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/* Map between the irq identifier used in hw to the irq_bucket. */
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struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
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/* Protect access to irq_map */
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static DEFINE_SPINLOCK(irq_map_lock);
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/* Allocate a new irq from the irq_table */
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unsigned int irq_alloc(unsigned int real_irq, unsigned int pil)
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{
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unsigned long flags;
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unsigned int i;
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spin_lock_irqsave(&irq_table_lock, flags);
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for (i = 1; i < NR_IRQS; i++) {
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if (irq_table[i].real_irq == real_irq && irq_table[i].pil == pil)
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goto found;
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}
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for (i = 1; i < NR_IRQS; i++) {
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if (!irq_table[i].irq)
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break;
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}
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if (i < NR_IRQS) {
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irq_table[i].real_irq = real_irq;
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irq_table[i].irq = i;
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irq_table[i].pil = pil;
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} else {
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printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
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i = 0;
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}
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found:
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spin_unlock_irqrestore(&irq_table_lock, flags);
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return i;
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}
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/* Based on a single pil handler_irq may need to call several
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* interrupt handlers. Use irq_map as entry to irq_table,
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* and let each entry in irq_table point to the next entry.
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*/
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void irq_link(unsigned int irq)
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{
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struct irq_bucket *p;
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unsigned long flags;
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unsigned int pil;
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BUG_ON(irq >= NR_IRQS);
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spin_lock_irqsave(&irq_map_lock, flags);
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p = &irq_table[irq];
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pil = p->pil;
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BUG_ON(pil > SUN4D_MAX_IRQ);
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p->next = irq_map[pil];
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irq_map[pil] = p;
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spin_unlock_irqrestore(&irq_map_lock, flags);
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}
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void irq_unlink(unsigned int irq)
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{
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struct irq_bucket *p, **pnext;
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unsigned long flags;
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BUG_ON(irq >= NR_IRQS);
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spin_lock_irqsave(&irq_map_lock, flags);
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p = &irq_table[irq];
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BUG_ON(p->pil > SUN4D_MAX_IRQ);
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pnext = &irq_map[p->pil];
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while (*pnext != p)
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pnext = &(*pnext)->next;
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*pnext = p->next;
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spin_unlock_irqrestore(&irq_map_lock, flags);
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}
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/* /proc/interrupts printing */
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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int j;
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#ifdef CONFIG_SMP
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seq_printf(p, "RES: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", cpu_data(j).irq_resched_count);
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seq_printf(p, " IPI rescheduling interrupts\n");
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seq_printf(p, "CAL: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", cpu_data(j).irq_call_count);
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seq_printf(p, " IPI function call interrupts\n");
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#endif
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seq_printf(p, "NMI: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", cpu_data(j).counter);
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seq_printf(p, " Non-maskable interrupts\n");
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return 0;
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}
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void handler_irq(unsigned int pil, struct pt_regs *regs)
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{
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struct pt_regs *old_regs;
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struct irq_bucket *p;
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BUG_ON(pil > 15);
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old_regs = set_irq_regs(regs);
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irq_enter();
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p = irq_map[pil];
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while (p) {
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struct irq_bucket *next = p->next;
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generic_handle_irq(p->irq);
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p = next;
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}
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irq_exit();
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set_irq_regs(old_regs);
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}
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#if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
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static unsigned int floppy_irq;
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int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler)
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{
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unsigned int cpu_irq;
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int err;
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err = request_irq(irq, irq_handler, 0, "floppy", NULL);
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if (err)
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return -1;
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/* Save for later use in floppy interrupt handler */
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floppy_irq = irq;
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cpu_irq = (irq & (NR_IRQS - 1));
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/* Dork with trap table if we get this far. */
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#define INSTANTIATE(table) \
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table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_one = SPARC_RD_PSR_L0; \
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table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two = \
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SPARC_BRANCH((unsigned long) floppy_hardint, \
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(unsigned long) &table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two);\
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table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_three = SPARC_RD_WIM_L3; \
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table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP;
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INSTANTIATE(sparc_ttable)
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#if defined CONFIG_SMP
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if (sparc_cpu_model != sparc_leon) {
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struct tt_entry *trap_table;
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trap_table = &trapbase_cpu1;
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INSTANTIATE(trap_table)
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trap_table = &trapbase_cpu2;
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INSTANTIATE(trap_table)
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trap_table = &trapbase_cpu3;
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INSTANTIATE(trap_table)
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}
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#endif
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#undef INSTANTIATE
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/*
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* XXX Correct thing whould be to flush only I- and D-cache lines
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* which contain the handler in question. But as of time of the
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* writing we have no CPU-neutral interface to fine-grained flushes.
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*/
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flush_cache_all();
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return 0;
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}
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EXPORT_SYMBOL(sparc_floppy_request_irq);
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/*
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* These variables are used to access state from the assembler
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* interrupt handler, floppy_hardint, so we cannot put these in
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* the floppy driver image because that would not work in the
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* modular case.
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*/
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volatile unsigned char *fdc_status;
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EXPORT_SYMBOL(fdc_status);
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char *pdma_vaddr;
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EXPORT_SYMBOL(pdma_vaddr);
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unsigned long pdma_size;
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EXPORT_SYMBOL(pdma_size);
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volatile int doing_pdma;
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EXPORT_SYMBOL(doing_pdma);
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char *pdma_base;
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EXPORT_SYMBOL(pdma_base);
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unsigned long pdma_areasize;
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EXPORT_SYMBOL(pdma_areasize);
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/* Use the generic irq support to call floppy_interrupt
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* which was setup using request_irq() in sparc_floppy_request_irq().
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* We only have one floppy interrupt so we do not need to check
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* for additional handlers being wired up by irq_link()
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*/
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void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs)
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{
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struct pt_regs *old_regs;
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old_regs = set_irq_regs(regs);
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irq_enter();
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generic_handle_irq(floppy_irq);
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irq_exit();
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set_irq_regs(old_regs);
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}
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#endif
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/* djhr
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* This could probably be made indirect too and assigned in the CPU
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* bits of the code. That would be much nicer I think and would also
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* fit in with the idea of being able to tune your kernel for your machine
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* by removing unrequired machine and device support.
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*
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*/
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void __init init_IRQ(void)
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{
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switch (sparc_cpu_model) {
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case sun4m:
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pcic_probe();
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if (pcic_present())
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sun4m_pci_init_IRQ();
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else
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sun4m_init_IRQ();
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break;
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case sun4d:
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sun4d_init_IRQ();
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break;
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case sparc_leon:
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leon_init_IRQ();
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break;
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default:
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prom_printf("Cannot initialize IRQs on this Sun machine...");
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break;
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}
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}
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