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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
245
arch/sparc/kernel/spiterrs.S
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245
arch/sparc/kernel/spiterrs.S
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/* We need to carefully read the error status, ACK the errors,
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* prevent recursive traps, and pass the information on to C
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* code for logging.
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*
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* We pass the AFAR in as-is, and we encode the status
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* information as described in asm-sparc64/sfafsr.h
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*/
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.type __spitfire_access_error,#function
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__spitfire_access_error:
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/* Disable ESTATE error reporting so that we do not take
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* recursive traps and RED state the processor.
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*/
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stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
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membar #Sync
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mov UDBE_UE, %g1
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ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
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/* __spitfire_cee_trap branches here with AFSR in %g4 and
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* UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the ESTATE
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* Error Enable register.
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*/
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__spitfire_cee_trap_continue:
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ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
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rdpr %tt, %g3
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and %g3, 0x1ff, %g3 ! Paranoia
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sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
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or %g4, %g3, %g4
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rdpr %tl, %g3
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cmp %g3, 1
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mov 1, %g3
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bleu %xcc, 1f
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sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
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or %g4, %g3, %g4
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/* Read in the UDB error register state, clearing the sticky
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* error bits as-needed. We only clear them if the UE bit is
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* set. Likewise, __spitfire_cee_trap below will only do so
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* if the CE bit is set.
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*
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* NOTE: UltraSparc-I/II have high and low UDB error
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* registers, corresponding to the two UDB units
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* present on those chips. UltraSparc-IIi only
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* has a single UDB, called "SDB" in the manual.
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* For IIi the upper UDB register always reads
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* as zero so for our purposes things will just
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* work with the checks below.
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*/
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1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
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and %g3, 0x3ff, %g7 ! Paranoia
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sllx %g7, SFSTAT_UDBH_SHIFT, %g7
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or %g4, %g7, %g4
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andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
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be,pn %xcc, 1f
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nop
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stxa %g3, [%g0] ASI_UDB_ERROR_W
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membar #Sync
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1: mov 0x18, %g3
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ldxa [%g3] ASI_UDBL_ERROR_R, %g3
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and %g3, 0x3ff, %g7 ! Paranoia
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sllx %g7, SFSTAT_UDBL_SHIFT, %g7
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or %g4, %g7, %g4
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andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
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be,pn %xcc, 1f
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nop
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mov 0x18, %g7
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stxa %g3, [%g7] ASI_UDB_ERROR_W
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membar #Sync
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1: /* Ok, now that we've latched the error state, clear the
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* sticky bits in the AFSR.
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*/
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stxa %g4, [%g0] ASI_AFSR
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membar #Sync
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rdpr %tl, %g2
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cmp %g2, 1
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rdpr %pil, %g2
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bleu,pt %xcc, 1f
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wrpr %g0, PIL_NORMAL_MAX, %pil
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ba,pt %xcc, etraptl1
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rd %pc, %g7
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ba,pt %xcc, 2f
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nop
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1: ba,pt %xcc, etrap_irq
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rd %pc, %g7
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2:
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#ifdef CONFIG_TRACE_IRQFLAGS
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call trace_hardirqs_off
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nop
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#endif
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mov %l4, %o1
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mov %l5, %o2
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call spitfire_access_error
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop
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.size __spitfire_access_error,.-__spitfire_access_error
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/* This is the trap handler entry point for ECC correctable
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* errors. They are corrected, but we listen for the trap so
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* that the event can be logged.
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*
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* Disrupting errors are either:
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* 1) single-bit ECC errors during UDB reads to system
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* memory
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* 2) data parity errors during write-back events
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*
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* As far as I can make out from the manual, the CEE trap is
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* only for correctable errors during memory read accesses by
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* the front-end of the processor.
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*
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* The code below is only for trap level 1 CEE events, as it
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* is the only situation where we can safely record and log.
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* For trap level >1 we just clear the CE bit in the AFSR and
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* return.
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*
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* This is just like __spiftire_access_error above, but it
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* specifically handles correctable errors. If an
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* uncorrectable error is indicated in the AFSR we will branch
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* directly above to __spitfire_access_error to handle it
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* instead. Uncorrectable therefore takes priority over
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* correctable, and the error logging C code will notice this
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* case by inspecting the trap type.
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*/
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.type __spitfire_cee_trap,#function
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__spitfire_cee_trap:
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ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
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mov 1, %g3
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sllx %g3, SFAFSR_UE_SHIFT, %g3
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andcc %g4, %g3, %g0 ! Check for UE
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bne,pn %xcc, __spitfire_access_error
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nop
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/* Ok, in this case we only have a correctable error.
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* Indicate we only wish to capture that state in register
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* %g1, and we only disable CE error reporting unlike UE
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* handling which disables all errors.
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*/
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ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
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andn %g3, ESTATE_ERR_CE, %g3
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stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
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membar #Sync
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/* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
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ba,pt %xcc, __spitfire_cee_trap_continue
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mov UDBE_CE, %g1
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.size __spitfire_cee_trap,.-__spitfire_cee_trap
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.type __spitfire_data_access_exception_tl1,#function
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__spitfire_data_access_exception_tl1:
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rdpr %pstate, %g4
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wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
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mov TLB_SFSR, %g3
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mov DMMU_SFAR, %g5
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ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
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ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
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stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
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membar #Sync
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rdpr %tt, %g3
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cmp %g3, 0x80 ! first win spill/fill trap
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blu,pn %xcc, 1f
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cmp %g3, 0xff ! last win spill/fill trap
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bgu,pn %xcc, 1f
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nop
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ba,pt %xcc, winfix_dax
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rdpr %tpc, %g3
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1: sethi %hi(109f), %g7
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ba,pt %xcc, etraptl1
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109: or %g7, %lo(109b), %g7
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mov %l4, %o1
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mov %l5, %o2
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call spitfire_data_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop
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.size __spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1
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.type __spitfire_data_access_exception,#function
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__spitfire_data_access_exception:
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rdpr %pstate, %g4
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wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
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mov TLB_SFSR, %g3
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mov DMMU_SFAR, %g5
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ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
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ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
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stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
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membar #Sync
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sethi %hi(109f), %g7
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ba,pt %xcc, etrap
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109: or %g7, %lo(109b), %g7
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mov %l4, %o1
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mov %l5, %o2
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call spitfire_data_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop
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.size __spitfire_data_access_exception,.-__spitfire_data_access_exception
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.type __spitfire_insn_access_exception_tl1,#function
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__spitfire_insn_access_exception_tl1:
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rdpr %pstate, %g4
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wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
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mov TLB_SFSR, %g3
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ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
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rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
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stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
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membar #Sync
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sethi %hi(109f), %g7
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ba,pt %xcc, etraptl1
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109: or %g7, %lo(109b), %g7
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mov %l4, %o1
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mov %l5, %o2
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call spitfire_insn_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop
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.size __spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1
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.type __spitfire_insn_access_exception,#function
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__spitfire_insn_access_exception:
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rdpr %pstate, %g4
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wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
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mov TLB_SFSR, %g3
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ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
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rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
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stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
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membar #Sync
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sethi %hi(109f), %g7
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ba,pt %xcc, etrap
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109: or %g7, %lo(109b), %g7
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mov %l4, %o1
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mov %l5, %o2
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call spitfire_insn_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop
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.size __spitfire_insn_access_exception,.-__spitfire_insn_access_exception
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