mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
451
arch/sparc/mm/iommu.c
Normal file
451
arch/sparc/mm/iommu.c
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@ -0,0 +1,451 @@
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/*
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* iommu.c: IOMMU specific routines for memory management.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
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* Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/highmem.h> /* pte_offset_map => kmap_atomic */
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#include <linux/scatterlist.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/io.h>
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#include <asm/mxcc.h>
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#include <asm/mbus.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/bitext.h>
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#include <asm/iommu.h>
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#include <asm/dma.h>
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#include "mm_32.h"
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/*
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* This can be sized dynamically, but we will do this
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* only when we have a guidance about actual I/O pressures.
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*/
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#define IOMMU_RNGE IOMMU_RNGE_256MB
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#define IOMMU_START 0xF0000000
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#define IOMMU_WINSIZE (256*1024*1024U)
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#define IOMMU_NPTES (IOMMU_WINSIZE/PAGE_SIZE) /* 64K PTEs, 256KB */
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#define IOMMU_ORDER 6 /* 4096 * (1<<6) */
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static int viking_flush;
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/* viking.S */
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extern void viking_flush_page(unsigned long page);
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extern void viking_mxcc_flush_page(unsigned long page);
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/*
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* Values precomputed according to CPU type.
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*/
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static unsigned int ioperm_noc; /* Consistent mapping iopte flags */
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static pgprot_t dvma_prot; /* Consistent mapping pte flags */
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#define IOPERM (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
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#define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
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static void __init sbus_iommu_init(struct platform_device *op)
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{
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struct iommu_struct *iommu;
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unsigned int impl, vers;
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unsigned long *bitmap;
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unsigned long control;
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unsigned long base;
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unsigned long tmp;
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iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
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if (!iommu) {
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prom_printf("Unable to allocate iommu structure\n");
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prom_halt();
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}
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iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
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"iommu_regs");
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if (!iommu->regs) {
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prom_printf("Cannot map IOMMU registers\n");
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prom_halt();
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}
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control = sbus_readl(&iommu->regs->control);
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impl = (control & IOMMU_CTRL_IMPL) >> 28;
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vers = (control & IOMMU_CTRL_VERS) >> 24;
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control &= ~(IOMMU_CTRL_RNGE);
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control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
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sbus_writel(control, &iommu->regs->control);
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iommu_invalidate(iommu->regs);
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iommu->start = IOMMU_START;
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iommu->end = 0xffffffff;
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/* Allocate IOMMU page table */
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/* Stupid alignment constraints give me a headache.
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We need 256K or 512K or 1M or 2M area aligned to
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its size and current gfp will fortunately give
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it to us. */
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tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
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if (!tmp) {
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prom_printf("Unable to allocate iommu table [0x%lx]\n",
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IOMMU_NPTES * sizeof(iopte_t));
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prom_halt();
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}
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iommu->page_table = (iopte_t *)tmp;
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/* Initialize new table. */
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memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
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flush_cache_all();
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flush_tlb_all();
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base = __pa((unsigned long)iommu->page_table) >> 4;
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sbus_writel(base, &iommu->regs->base);
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iommu_invalidate(iommu->regs);
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bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
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if (!bitmap) {
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prom_printf("Unable to allocate iommu bitmap [%d]\n",
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(int)(IOMMU_NPTES>>3));
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prom_halt();
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}
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bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
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/* To be coherent on HyperSparc, the page color of DVMA
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* and physical addresses must match.
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*/
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if (srmmu_modtype == HyperSparc)
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iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
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else
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iommu->usemap.num_colors = 1;
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printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
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impl, vers, iommu->page_table,
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(int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
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op->dev.archdata.iommu = iommu;
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}
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static int __init iommu_init(void)
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{
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struct device_node *dp;
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for_each_node_by_name(dp, "iommu") {
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struct platform_device *op = of_find_device_by_node(dp);
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sbus_iommu_init(op);
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of_propagate_archdata(op);
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}
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return 0;
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}
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subsys_initcall(iommu_init);
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/* Flush the iotlb entries to ram. */
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/* This could be better if we didn't have to flush whole pages. */
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static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
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{
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unsigned long start;
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unsigned long end;
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start = (unsigned long)iopte;
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end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
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start &= PAGE_MASK;
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if (viking_mxcc_present) {
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while(start < end) {
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viking_mxcc_flush_page(start);
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start += PAGE_SIZE;
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}
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} else if (viking_flush) {
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while(start < end) {
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viking_flush_page(start);
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start += PAGE_SIZE;
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}
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} else {
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while(start < end) {
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__flush_page_to_ram(start);
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start += PAGE_SIZE;
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}
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}
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}
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static u32 iommu_get_one(struct device *dev, struct page *page, int npages)
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{
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struct iommu_struct *iommu = dev->archdata.iommu;
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int ioptex;
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iopte_t *iopte, *iopte0;
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unsigned int busa, busa0;
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int i;
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/* page color = pfn of page */
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ioptex = bit_map_string_get(&iommu->usemap, npages, page_to_pfn(page));
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if (ioptex < 0)
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panic("iommu out");
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busa0 = iommu->start + (ioptex << PAGE_SHIFT);
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iopte0 = &iommu->page_table[ioptex];
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busa = busa0;
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iopte = iopte0;
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for (i = 0; i < npages; i++) {
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iopte_val(*iopte) = MKIOPTE(page_to_pfn(page), IOPERM);
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iommu_invalidate_page(iommu->regs, busa);
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busa += PAGE_SIZE;
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iopte++;
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page++;
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}
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iommu_flush_iotlb(iopte0, npages);
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return busa0;
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}
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static u32 iommu_get_scsi_one(struct device *dev, char *vaddr, unsigned int len)
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{
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unsigned long off;
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int npages;
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struct page *page;
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u32 busa;
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off = (unsigned long)vaddr & ~PAGE_MASK;
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npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
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page = virt_to_page((unsigned long)vaddr & PAGE_MASK);
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busa = iommu_get_one(dev, page, npages);
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return busa + off;
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}
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static __u32 iommu_get_scsi_one_gflush(struct device *dev, char *vaddr, unsigned long len)
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{
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flush_page_for_dma(0);
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return iommu_get_scsi_one(dev, vaddr, len);
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}
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static __u32 iommu_get_scsi_one_pflush(struct device *dev, char *vaddr, unsigned long len)
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{
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unsigned long page = ((unsigned long) vaddr) & PAGE_MASK;
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while(page < ((unsigned long)(vaddr + len))) {
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flush_page_for_dma(page);
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page += PAGE_SIZE;
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}
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return iommu_get_scsi_one(dev, vaddr, len);
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}
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static void iommu_get_scsi_sgl_gflush(struct device *dev, struct scatterlist *sg, int sz)
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{
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int n;
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flush_page_for_dma(0);
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while (sz != 0) {
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--sz;
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n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
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sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
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sg->dma_length = sg->length;
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sg = sg_next(sg);
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}
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}
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static void iommu_get_scsi_sgl_pflush(struct device *dev, struct scatterlist *sg, int sz)
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{
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unsigned long page, oldpage = 0;
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int n, i;
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while(sz != 0) {
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--sz;
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n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
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/*
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* We expect unmapped highmem pages to be not in the cache.
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* XXX Is this a good assumption?
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* XXX What if someone else unmaps it here and races us?
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*/
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if ((page = (unsigned long) page_address(sg_page(sg))) != 0) {
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for (i = 0; i < n; i++) {
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if (page != oldpage) { /* Already flushed? */
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flush_page_for_dma(page);
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oldpage = page;
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}
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page += PAGE_SIZE;
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}
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}
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sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
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sg->dma_length = sg->length;
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sg = sg_next(sg);
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}
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}
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static void iommu_release_one(struct device *dev, u32 busa, int npages)
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{
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struct iommu_struct *iommu = dev->archdata.iommu;
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int ioptex;
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int i;
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BUG_ON(busa < iommu->start);
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ioptex = (busa - iommu->start) >> PAGE_SHIFT;
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for (i = 0; i < npages; i++) {
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iopte_val(iommu->page_table[ioptex + i]) = 0;
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iommu_invalidate_page(iommu->regs, busa);
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busa += PAGE_SIZE;
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}
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bit_map_clear(&iommu->usemap, ioptex, npages);
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}
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static void iommu_release_scsi_one(struct device *dev, __u32 vaddr, unsigned long len)
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{
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unsigned long off;
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int npages;
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off = vaddr & ~PAGE_MASK;
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npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
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iommu_release_one(dev, vaddr & PAGE_MASK, npages);
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}
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static void iommu_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
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{
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int n;
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while(sz != 0) {
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--sz;
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n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
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iommu_release_one(dev, sg->dma_address & PAGE_MASK, n);
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sg->dma_address = 0x21212121;
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sg = sg_next(sg);
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}
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}
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#ifdef CONFIG_SBUS
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static int iommu_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va,
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unsigned long addr, int len)
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{
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struct iommu_struct *iommu = dev->archdata.iommu;
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unsigned long page, end;
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iopte_t *iopte = iommu->page_table;
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iopte_t *first;
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int ioptex;
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BUG_ON((va & ~PAGE_MASK) != 0);
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BUG_ON((addr & ~PAGE_MASK) != 0);
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BUG_ON((len & ~PAGE_MASK) != 0);
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/* page color = physical address */
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ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
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addr >> PAGE_SHIFT);
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if (ioptex < 0)
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panic("iommu out");
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iopte += ioptex;
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first = iopte;
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end = addr + len;
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while(addr < end) {
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page = va;
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{
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pgd_t *pgdp;
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pmd_t *pmdp;
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pte_t *ptep;
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if (viking_mxcc_present)
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viking_mxcc_flush_page(page);
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else if (viking_flush)
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viking_flush_page(page);
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else
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__flush_page_to_ram(page);
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pgdp = pgd_offset(&init_mm, addr);
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pmdp = pmd_offset(pgdp, addr);
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ptep = pte_offset_map(pmdp, addr);
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set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
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}
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iopte_val(*iopte++) =
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MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
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addr += PAGE_SIZE;
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va += PAGE_SIZE;
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}
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/* P3: why do we need this?
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*
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* DAVEM: Because there are several aspects, none of which
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* are handled by a single interface. Some cpus are
|
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* completely not I/O DMA coherent, and some have
|
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* virtually indexed caches. The driver DMA flushing
|
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* methods handle the former case, but here during
|
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* IOMMU page table modifications, and usage of non-cacheable
|
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* cpu mappings of pages potentially in the cpu caches, we have
|
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* to handle the latter case as well.
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*/
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flush_cache_all();
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iommu_flush_iotlb(first, len >> PAGE_SHIFT);
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flush_tlb_all();
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iommu_invalidate(iommu->regs);
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*pba = iommu->start + (ioptex << PAGE_SHIFT);
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return 0;
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}
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|
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static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len)
|
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{
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struct iommu_struct *iommu = dev->archdata.iommu;
|
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iopte_t *iopte = iommu->page_table;
|
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unsigned long end;
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int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
|
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|
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BUG_ON((busa & ~PAGE_MASK) != 0);
|
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BUG_ON((len & ~PAGE_MASK) != 0);
|
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|
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iopte += ioptex;
|
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end = busa + len;
|
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while (busa < end) {
|
||||
iopte_val(*iopte++) = 0;
|
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busa += PAGE_SIZE;
|
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}
|
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flush_tlb_all();
|
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iommu_invalidate(iommu->regs);
|
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bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
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}
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#endif
|
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static const struct sparc32_dma_ops iommu_dma_gflush_ops = {
|
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.get_scsi_one = iommu_get_scsi_one_gflush,
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.get_scsi_sgl = iommu_get_scsi_sgl_gflush,
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.release_scsi_one = iommu_release_scsi_one,
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.release_scsi_sgl = iommu_release_scsi_sgl,
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#ifdef CONFIG_SBUS
|
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.map_dma_area = iommu_map_dma_area,
|
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.unmap_dma_area = iommu_unmap_dma_area,
|
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#endif
|
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};
|
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|
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static const struct sparc32_dma_ops iommu_dma_pflush_ops = {
|
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.get_scsi_one = iommu_get_scsi_one_pflush,
|
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.get_scsi_sgl = iommu_get_scsi_sgl_pflush,
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.release_scsi_one = iommu_release_scsi_one,
|
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.release_scsi_sgl = iommu_release_scsi_sgl,
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#ifdef CONFIG_SBUS
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.map_dma_area = iommu_map_dma_area,
|
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.unmap_dma_area = iommu_unmap_dma_area,
|
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#endif
|
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};
|
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|
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void __init ld_mmu_iommu(void)
|
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{
|
||||
if (flush_page_for_dma_global) {
|
||||
/* flush_page_for_dma flushes everything, no matter of what page is it */
|
||||
sparc32_dma_ops = &iommu_dma_gflush_ops;
|
||||
} else {
|
||||
sparc32_dma_ops = &iommu_dma_pflush_ops;
|
||||
}
|
||||
|
||||
if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
|
||||
dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
|
||||
ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
|
||||
} else {
|
||||
dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
|
||||
ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue