mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-29 15:28:50 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
40
arch/tile/include/gxio/common.h
Normal file
40
arch/tile/include/gxio/common.h
Normal file
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@ -0,0 +1,40 @@
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/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
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#ifndef _GXIO_COMMON_H_
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#define _GXIO_COMMON_H_
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/*
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* Routines shared between the various GXIO device components.
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*/
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#include <hv/iorpc.h>
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#include <linux/types.h>
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#include <linux/compiler.h>
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#include <linux/io.h>
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/* Define the standard gxio MMIO functions using kernel functions. */
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#define __gxio_mmio_read8(addr) readb(addr)
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#define __gxio_mmio_read16(addr) readw(addr)
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#define __gxio_mmio_read32(addr) readl(addr)
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#define __gxio_mmio_read64(addr) readq(addr)
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#define __gxio_mmio_write8(addr, val) writeb((val), (addr))
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#define __gxio_mmio_write16(addr, val) writew((val), (addr))
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#define __gxio_mmio_write32(addr, val) writel((val), (addr))
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#define __gxio_mmio_write64(addr, val) writeq((val), (addr))
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#define __gxio_mmio_read(addr) __gxio_mmio_read64(addr)
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#define __gxio_mmio_write(addr, val) __gxio_mmio_write64((addr), (val))
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#endif /* !_GXIO_COMMON_H_ */
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161
arch/tile/include/gxio/dma_queue.h
Normal file
161
arch/tile/include/gxio/dma_queue.h
Normal file
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@ -0,0 +1,161 @@
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/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
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*/
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#ifndef _GXIO_DMA_QUEUE_H_
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#define _GXIO_DMA_QUEUE_H_
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/*
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* DMA queue management APIs shared between TRIO and mPIPE.
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*/
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#include <gxio/common.h>
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/* The credit counter lives in the high 32 bits. */
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#define DMA_QUEUE_CREDIT_SHIFT 32
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/*
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* State object that tracks a DMA queue's head and tail indices, as
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* well as the number of commands posted and completed. The
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* structure is accessed via a thread-safe, lock-free algorithm.
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*/
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typedef struct {
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/*
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* Address of a MPIPE_EDMA_POST_REGION_VAL_t,
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* TRIO_PUSH_DMA_REGION_VAL_t, or TRIO_PULL_DMA_REGION_VAL_t
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* register. These register have identical encodings and provide
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* information about how many commands have been processed.
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*/
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void *post_region_addr;
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/*
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* A lazily-updated count of how many edescs the hardware has
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* completed.
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*/
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uint64_t hw_complete_count __attribute__ ((aligned(64)));
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/*
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* High 32 bits are a count of available egress command credits,
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* low 24 bits are the next egress "slot".
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*/
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int64_t credits_and_next_index;
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} __gxio_dma_queue_t;
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/* Initialize a dma queue. */
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extern void __gxio_dma_queue_init(__gxio_dma_queue_t *dma_queue,
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void *post_region_addr,
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unsigned int num_entries);
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/*
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* Update the "credits_and_next_index" and "hw_complete_count" fields
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* based on pending hardware completions. Note that some other thread
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* may have already done this and, importantly, may still be in the
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* process of updating "credits_and_next_index".
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*/
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extern void __gxio_dma_queue_update_credits(__gxio_dma_queue_t *dma_queue);
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/* Wait for credits to become available. */
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extern int64_t __gxio_dma_queue_wait_for_credits(__gxio_dma_queue_t *dma_queue,
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int64_t modifier);
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/* Reserve slots in the queue, optionally waiting for slots to become
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* available, and optionally returning a "completion_slot" suitable for
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* direct comparison to "hw_complete_count".
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*/
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static inline int64_t __gxio_dma_queue_reserve(__gxio_dma_queue_t *dma_queue,
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unsigned int num, bool wait,
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bool completion)
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{
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uint64_t slot;
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/*
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* Try to reserve 'num' egress command slots. We do this by
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* constructing a constant that subtracts N credits and adds N to
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* the index, and using fetchaddgez to only apply it if the credits
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* count doesn't go negative.
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*/
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int64_t modifier = (((int64_t)(-num)) << DMA_QUEUE_CREDIT_SHIFT) | num;
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int64_t old =
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__insn_fetchaddgez(&dma_queue->credits_and_next_index,
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modifier);
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if (unlikely(old + modifier < 0)) {
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/*
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* We're out of credits. Try once to get more by checking for
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* completed egress commands. If that fails, wait or fail.
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*/
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__gxio_dma_queue_update_credits(dma_queue);
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old = __insn_fetchaddgez(&dma_queue->credits_and_next_index,
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modifier);
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if (old + modifier < 0) {
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if (wait)
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old = __gxio_dma_queue_wait_for_credits
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(dma_queue, modifier);
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else
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return GXIO_ERR_DMA_CREDITS;
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}
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}
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/* The bottom 24 bits of old encode the "slot". */
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slot = (old & 0xffffff);
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if (completion) {
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/*
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* A "completion_slot" is a "slot" which can be compared to
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* "hw_complete_count" at any time in the future. To convert
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* "slot" into a "completion_slot", we access "hw_complete_count"
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* once (knowing that we have reserved a slot, and thus, it will
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* be "basically" accurate), and combine its high 40 bits with
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* the 24 bit "slot", and handle "wrapping" by adding "1 << 24"
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* if the result is LESS than "hw_complete_count".
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*/
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uint64_t complete;
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complete = ACCESS_ONCE(dma_queue->hw_complete_count);
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slot |= (complete & 0xffffffffff000000);
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if (slot < complete)
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slot += 0x1000000;
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}
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/*
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* If any of our slots mod 256 were equivalent to 0, go ahead and
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* collect some egress credits, and update "hw_complete_count", and
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* make sure the index doesn't overflow into the credits.
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*/
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if (unlikely(((old + num) & 0xff) < num)) {
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__gxio_dma_queue_update_credits(dma_queue);
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/* Make sure the index doesn't overflow into the credits. */
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#ifdef __BIG_ENDIAN__
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*(((uint8_t *)&dma_queue->credits_and_next_index) + 4) = 0;
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#else
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*(((uint8_t *)&dma_queue->credits_and_next_index) + 3) = 0;
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#endif
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}
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return slot;
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}
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/* Non-inlinable "__gxio_dma_queue_reserve(..., true)". */
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extern int64_t __gxio_dma_queue_reserve_aux(__gxio_dma_queue_t *dma_queue,
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unsigned int num, int wait);
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/* Check whether a particular "completion slot" has completed.
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*
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* Note that this function requires a "completion slot", and thus
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* cannot be used with the result of any "reserve_fast" function.
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*/
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extern int __gxio_dma_queue_is_complete(__gxio_dma_queue_t *dma_queue,
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int64_t completion_slot, int update);
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#endif /* !_GXIO_DMA_QUEUE_H_ */
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38
arch/tile/include/gxio/iorpc_globals.h
Normal file
38
arch/tile/include/gxio/iorpc_globals.h
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
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||||
*
|
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* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
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/* This file is machine-generated; DO NOT EDIT! */
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#ifndef __IORPC_LINUX_RPC_H__
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#define __IORPC_LINUX_RPC_H__
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#include <hv/iorpc.h>
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#include <linux/string.h>
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#include <linux/module.h>
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#include <asm/pgtable.h>
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#define IORPC_OP_ARM_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9000)
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#define IORPC_OP_CLOSE_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9001)
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#define IORPC_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
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#define IORPC_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
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int __iorpc_arm_pollfd(int fd, int pollfd_cookie);
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int __iorpc_close_pollfd(int fd, int pollfd_cookie);
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int __iorpc_get_mmio_base(int fd, HV_PTE *base);
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int __iorpc_check_mmio_offset(int fd, unsigned long offset, unsigned long size);
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#endif /* !__IORPC_LINUX_RPC_H__ */
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144
arch/tile/include/gxio/iorpc_mpipe.h
Normal file
144
arch/tile/include/gxio/iorpc_mpipe.h
Normal file
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@ -0,0 +1,144 @@
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/*
|
||||
* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
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||||
*/
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/* This file is machine-generated; DO NOT EDIT! */
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#ifndef __GXIO_MPIPE_LINUX_RPC_H__
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#define __GXIO_MPIPE_LINUX_RPC_H__
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#include <hv/iorpc.h>
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#include <hv/drv_mpipe_intf.h>
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#include <asm/page.h>
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#include <gxio/kiorpc.h>
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#include <gxio/mpipe.h>
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#include <linux/string.h>
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#include <linux/module.h>
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#include <asm/pgtable.h>
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#define GXIO_MPIPE_OP_ALLOC_BUFFER_STACKS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1200)
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#define GXIO_MPIPE_OP_INIT_BUFFER_STACK_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x1201)
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#define GXIO_MPIPE_OP_ALLOC_NOTIF_RINGS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1203)
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#define GXIO_MPIPE_OP_INIT_NOTIF_RING_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x1204)
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#define GXIO_MPIPE_OP_REQUEST_NOTIF_RING_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1205)
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#define GXIO_MPIPE_OP_ENABLE_NOTIF_RING_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1206)
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#define GXIO_MPIPE_OP_ALLOC_NOTIF_GROUPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1207)
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#define GXIO_MPIPE_OP_INIT_NOTIF_GROUP IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1208)
|
||||
#define GXIO_MPIPE_OP_ALLOC_BUCKETS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1209)
|
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#define GXIO_MPIPE_OP_INIT_BUCKET IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120a)
|
||||
#define GXIO_MPIPE_OP_ALLOC_EDMA_RINGS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120b)
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#define GXIO_MPIPE_OP_INIT_EDMA_RING_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x120c)
|
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|
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#define GXIO_MPIPE_OP_COMMIT_RULES IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120f)
|
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#define GXIO_MPIPE_OP_REGISTER_CLIENT_MEMORY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1210)
|
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#define GXIO_MPIPE_OP_LINK_OPEN_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1211)
|
||||
#define GXIO_MPIPE_OP_LINK_CLOSE_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1212)
|
||||
#define GXIO_MPIPE_OP_LINK_SET_ATTR_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1213)
|
||||
|
||||
#define GXIO_MPIPE_OP_GET_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x121e)
|
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#define GXIO_MPIPE_OP_SET_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x121f)
|
||||
#define GXIO_MPIPE_OP_ADJUST_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1220)
|
||||
#define GXIO_MPIPE_OP_CONFIG_EDMA_RING_BLKS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1221)
|
||||
#define GXIO_MPIPE_OP_ADJUST_TIMESTAMP_FREQ IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1222)
|
||||
#define GXIO_MPIPE_OP_ARM_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9000)
|
||||
#define GXIO_MPIPE_OP_CLOSE_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9001)
|
||||
#define GXIO_MPIPE_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
|
||||
#define GXIO_MPIPE_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
|
||||
|
||||
int gxio_mpipe_alloc_buffer_stacks(gxio_mpipe_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
int gxio_mpipe_init_buffer_stack_aux(gxio_mpipe_context_t *context,
|
||||
void *mem_va, size_t mem_size,
|
||||
unsigned int mem_flags, unsigned int stack,
|
||||
unsigned int buffer_size_enum);
|
||||
|
||||
|
||||
int gxio_mpipe_alloc_notif_rings(gxio_mpipe_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
int gxio_mpipe_init_notif_ring_aux(gxio_mpipe_context_t *context, void *mem_va,
|
||||
size_t mem_size, unsigned int mem_flags,
|
||||
unsigned int ring);
|
||||
|
||||
int gxio_mpipe_request_notif_ring_interrupt(gxio_mpipe_context_t *context,
|
||||
int inter_x, int inter_y,
|
||||
int inter_ipi, int inter_event,
|
||||
unsigned int ring);
|
||||
|
||||
int gxio_mpipe_enable_notif_ring_interrupt(gxio_mpipe_context_t *context,
|
||||
unsigned int ring);
|
||||
|
||||
int gxio_mpipe_alloc_notif_groups(gxio_mpipe_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
int gxio_mpipe_init_notif_group(gxio_mpipe_context_t *context,
|
||||
unsigned int group,
|
||||
gxio_mpipe_notif_group_bits_t bits);
|
||||
|
||||
int gxio_mpipe_alloc_buckets(gxio_mpipe_context_t *context, unsigned int count,
|
||||
unsigned int first, unsigned int flags);
|
||||
|
||||
int gxio_mpipe_init_bucket(gxio_mpipe_context_t *context, unsigned int bucket,
|
||||
MPIPE_LBL_INIT_DAT_BSTS_TBL_t bucket_info);
|
||||
|
||||
int gxio_mpipe_alloc_edma_rings(gxio_mpipe_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
int gxio_mpipe_init_edma_ring_aux(gxio_mpipe_context_t *context, void *mem_va,
|
||||
size_t mem_size, unsigned int mem_flags,
|
||||
unsigned int ring, unsigned int channel);
|
||||
|
||||
|
||||
int gxio_mpipe_commit_rules(gxio_mpipe_context_t *context, const void *blob,
|
||||
size_t blob_size);
|
||||
|
||||
int gxio_mpipe_register_client_memory(gxio_mpipe_context_t *context,
|
||||
unsigned int iotlb, HV_PTE pte,
|
||||
unsigned int flags);
|
||||
|
||||
int gxio_mpipe_link_open_aux(gxio_mpipe_context_t *context,
|
||||
_gxio_mpipe_link_name_t name, unsigned int flags);
|
||||
|
||||
int gxio_mpipe_link_close_aux(gxio_mpipe_context_t *context, int mac);
|
||||
|
||||
int gxio_mpipe_link_set_attr_aux(gxio_mpipe_context_t *context, int mac,
|
||||
uint32_t attr, int64_t val);
|
||||
|
||||
int gxio_mpipe_get_timestamp_aux(gxio_mpipe_context_t *context, uint64_t *sec,
|
||||
uint64_t *nsec, uint64_t *cycles);
|
||||
|
||||
int gxio_mpipe_set_timestamp_aux(gxio_mpipe_context_t *context, uint64_t sec,
|
||||
uint64_t nsec, uint64_t cycles);
|
||||
|
||||
int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t *context,
|
||||
int64_t nsec);
|
||||
|
||||
int gxio_mpipe_adjust_timestamp_freq(gxio_mpipe_context_t *context,
|
||||
int32_t ppb);
|
||||
|
||||
int gxio_mpipe_arm_pollfd(gxio_mpipe_context_t *context, int pollfd_cookie);
|
||||
|
||||
int gxio_mpipe_close_pollfd(gxio_mpipe_context_t *context, int pollfd_cookie);
|
||||
|
||||
int gxio_mpipe_get_mmio_base(gxio_mpipe_context_t *context, HV_PTE *base);
|
||||
|
||||
int gxio_mpipe_check_mmio_offset(gxio_mpipe_context_t *context,
|
||||
unsigned long offset, unsigned long size);
|
||||
|
||||
#endif /* !__GXIO_MPIPE_LINUX_RPC_H__ */
|
||||
50
arch/tile/include/gxio/iorpc_mpipe_info.h
Normal file
50
arch/tile/include/gxio/iorpc_mpipe_info.h
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/* This file is machine-generated; DO NOT EDIT! */
|
||||
#ifndef __GXIO_MPIPE_INFO_LINUX_RPC_H__
|
||||
#define __GXIO_MPIPE_INFO_LINUX_RPC_H__
|
||||
|
||||
#include <hv/iorpc.h>
|
||||
|
||||
#include <hv/drv_mpipe_intf.h>
|
||||
#include <asm/page.h>
|
||||
#include <gxio/kiorpc.h>
|
||||
#include <gxio/mpipe.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
|
||||
#define GXIO_MPIPE_INFO_OP_INSTANCE_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1250)
|
||||
#define GXIO_MPIPE_INFO_OP_ENUMERATE_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1251)
|
||||
#define GXIO_MPIPE_INFO_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
|
||||
#define GXIO_MPIPE_INFO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
|
||||
|
||||
|
||||
int gxio_mpipe_info_instance_aux(gxio_mpipe_info_context_t *context,
|
||||
_gxio_mpipe_link_name_t name);
|
||||
|
||||
int gxio_mpipe_info_enumerate_aux(gxio_mpipe_info_context_t *context,
|
||||
unsigned int idx,
|
||||
_gxio_mpipe_link_name_t *name,
|
||||
_gxio_mpipe_link_mac_t *mac);
|
||||
|
||||
int gxio_mpipe_info_get_mmio_base(gxio_mpipe_info_context_t *context,
|
||||
HV_PTE *base);
|
||||
|
||||
int gxio_mpipe_info_check_mmio_offset(gxio_mpipe_info_context_t *context,
|
||||
unsigned long offset, unsigned long size);
|
||||
|
||||
#endif /* !__GXIO_MPIPE_INFO_LINUX_RPC_H__ */
|
||||
104
arch/tile/include/gxio/iorpc_trio.h
Normal file
104
arch/tile/include/gxio/iorpc_trio.h
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/* This file is machine-generated; DO NOT EDIT! */
|
||||
#ifndef __GXIO_TRIO_LINUX_RPC_H__
|
||||
#define __GXIO_TRIO_LINUX_RPC_H__
|
||||
|
||||
#include <hv/iorpc.h>
|
||||
|
||||
#include <hv/drv_trio_intf.h>
|
||||
#include <gxio/trio.h>
|
||||
#include <gxio/kiorpc.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
#define GXIO_TRIO_OP_DEALLOC_ASID IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1400)
|
||||
#define GXIO_TRIO_OP_ALLOC_ASIDS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1401)
|
||||
|
||||
#define GXIO_TRIO_OP_ALLOC_MEMORY_MAPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1404)
|
||||
|
||||
#define GXIO_TRIO_OP_ALLOC_SCATTER_QUEUES IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140e)
|
||||
#define GXIO_TRIO_OP_ALLOC_PIO_REGIONS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1412)
|
||||
|
||||
#define GXIO_TRIO_OP_INIT_PIO_REGION_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1414)
|
||||
|
||||
#define GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141e)
|
||||
#define GXIO_TRIO_OP_GET_PORT_PROPERTY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141f)
|
||||
#define GXIO_TRIO_OP_CONFIG_LEGACY_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1420)
|
||||
#define GXIO_TRIO_OP_CONFIG_MSI_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1421)
|
||||
|
||||
#define GXIO_TRIO_OP_SET_MPS_MRS IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1423)
|
||||
#define GXIO_TRIO_OP_FORCE_RC_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1424)
|
||||
#define GXIO_TRIO_OP_FORCE_EP_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1425)
|
||||
#define GXIO_TRIO_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
|
||||
#define GXIO_TRIO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
|
||||
|
||||
int gxio_trio_alloc_asids(gxio_trio_context_t *context, unsigned int count,
|
||||
unsigned int first, unsigned int flags);
|
||||
|
||||
|
||||
int gxio_trio_alloc_memory_maps(gxio_trio_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
|
||||
int gxio_trio_alloc_scatter_queues(gxio_trio_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
int gxio_trio_alloc_pio_regions(gxio_trio_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
int gxio_trio_init_pio_region_aux(gxio_trio_context_t *context,
|
||||
unsigned int pio_region, unsigned int mac,
|
||||
uint32_t bus_address_hi, unsigned int flags);
|
||||
|
||||
|
||||
int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t *context,
|
||||
unsigned int map, unsigned long va,
|
||||
uint64_t size, unsigned int asid,
|
||||
unsigned int mac, uint64_t bus_address,
|
||||
unsigned int node,
|
||||
unsigned int order_mode);
|
||||
|
||||
int gxio_trio_get_port_property(gxio_trio_context_t *context,
|
||||
struct pcie_trio_ports_property *trio_ports);
|
||||
|
||||
int gxio_trio_config_legacy_intr(gxio_trio_context_t *context, int inter_x,
|
||||
int inter_y, int inter_ipi, int inter_event,
|
||||
unsigned int mac, unsigned int intx);
|
||||
|
||||
int gxio_trio_config_msi_intr(gxio_trio_context_t *context, int inter_x,
|
||||
int inter_y, int inter_ipi, int inter_event,
|
||||
unsigned int mac, unsigned int mem_map,
|
||||
uint64_t mem_map_base, uint64_t mem_map_limit,
|
||||
unsigned int asid);
|
||||
|
||||
|
||||
int gxio_trio_set_mps_mrs(gxio_trio_context_t *context, uint16_t mps,
|
||||
uint16_t mrs, unsigned int mac);
|
||||
|
||||
int gxio_trio_force_rc_link_up(gxio_trio_context_t *context, unsigned int mac);
|
||||
|
||||
int gxio_trio_force_ep_link_up(gxio_trio_context_t *context, unsigned int mac);
|
||||
|
||||
int gxio_trio_get_mmio_base(gxio_trio_context_t *context, HV_PTE *base);
|
||||
|
||||
int gxio_trio_check_mmio_offset(gxio_trio_context_t *context,
|
||||
unsigned long offset, unsigned long size);
|
||||
|
||||
#endif /* !__GXIO_TRIO_LINUX_RPC_H__ */
|
||||
40
arch/tile/include/gxio/iorpc_uart.h
Normal file
40
arch/tile/include/gxio/iorpc_uart.h
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright 2013 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/* This file is machine-generated; DO NOT EDIT! */
|
||||
#ifndef __GXIO_UART_LINUX_RPC_H__
|
||||
#define __GXIO_UART_LINUX_RPC_H__
|
||||
|
||||
#include <hv/iorpc.h>
|
||||
|
||||
#include <hv/drv_uart_intf.h>
|
||||
#include <gxio/uart.h>
|
||||
#include <gxio/kiorpc.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
#define GXIO_UART_OP_CFG_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1900)
|
||||
#define GXIO_UART_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
|
||||
#define GXIO_UART_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
|
||||
|
||||
int gxio_uart_cfg_interrupt(gxio_uart_context_t *context, int inter_x,
|
||||
int inter_y, int inter_ipi, int inter_event);
|
||||
|
||||
int gxio_uart_get_mmio_base(gxio_uart_context_t *context, HV_PTE *base);
|
||||
|
||||
int gxio_uart_check_mmio_offset(gxio_uart_context_t *context,
|
||||
unsigned long offset, unsigned long size);
|
||||
|
||||
#endif /* !__GXIO_UART_LINUX_RPC_H__ */
|
||||
46
arch/tile/include/gxio/iorpc_usb_host.h
Normal file
46
arch/tile/include/gxio/iorpc_usb_host.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/* This file is machine-generated; DO NOT EDIT! */
|
||||
#ifndef __GXIO_USB_HOST_LINUX_RPC_H__
|
||||
#define __GXIO_USB_HOST_LINUX_RPC_H__
|
||||
|
||||
#include <hv/iorpc.h>
|
||||
|
||||
#include <hv/drv_usb_host_intf.h>
|
||||
#include <asm/page.h>
|
||||
#include <gxio/kiorpc.h>
|
||||
#include <gxio/usb_host.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
||||
#define GXIO_USB_HOST_OP_CFG_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1800)
|
||||
#define GXIO_USB_HOST_OP_REGISTER_CLIENT_MEMORY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1801)
|
||||
#define GXIO_USB_HOST_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
|
||||
#define GXIO_USB_HOST_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
|
||||
|
||||
int gxio_usb_host_cfg_interrupt(gxio_usb_host_context_t *context, int inter_x,
|
||||
int inter_y, int inter_ipi, int inter_event);
|
||||
|
||||
int gxio_usb_host_register_client_memory(gxio_usb_host_context_t *context,
|
||||
HV_PTE pte, unsigned int flags);
|
||||
|
||||
int gxio_usb_host_get_mmio_base(gxio_usb_host_context_t *context,
|
||||
HV_PTE *base);
|
||||
|
||||
int gxio_usb_host_check_mmio_offset(gxio_usb_host_context_t *context,
|
||||
unsigned long offset, unsigned long size);
|
||||
|
||||
#endif /* !__GXIO_USB_HOST_LINUX_RPC_H__ */
|
||||
29
arch/tile/include/gxio/kiorpc.h
Normal file
29
arch/tile/include/gxio/kiorpc.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* Support routines for kernel IORPC drivers.
|
||||
*/
|
||||
|
||||
#ifndef _GXIO_KIORPC_H
|
||||
#define _GXIO_KIORPC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/page.h>
|
||||
#include <arch/chip.h>
|
||||
|
||||
#if CHIP_HAS_MMIO()
|
||||
void __iomem *iorpc_ioremap(int hv_fd, resource_size_t offset,
|
||||
unsigned long size);
|
||||
#endif
|
||||
|
||||
#endif /* _GXIO_KIORPC_H */
|
||||
1871
arch/tile/include/gxio/mpipe.h
Normal file
1871
arch/tile/include/gxio/mpipe.h
Normal file
File diff suppressed because it is too large
Load diff
298
arch/tile/include/gxio/trio.h
Normal file
298
arch/tile/include/gxio/trio.h
Normal file
|
|
@ -0,0 +1,298 @@
|
|||
/*
|
||||
* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* An API for allocating, configuring, and manipulating TRIO hardware
|
||||
* resources
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* The TILE-Gx TRIO shim provides connections to external devices via
|
||||
* PCIe or other transaction IO standards. The gxio_trio_ API,
|
||||
* declared in <gxio/trio.h>, allows applications to allocate and
|
||||
* configure TRIO IO resources like DMA command rings, memory map
|
||||
* windows, and device interrupts. The following sections introduce
|
||||
* the various components of the API. We strongly recommend reading
|
||||
* the TRIO section of the IO Device Guide (UG404) before working with
|
||||
* this API.
|
||||
*
|
||||
* @section trio__ingress TRIO Ingress Hardware Resources
|
||||
*
|
||||
* The TRIO ingress hardware is responsible for examining incoming
|
||||
* PCIe or StreamIO packets and choosing a processing mechanism based
|
||||
* on the packets' bus address. The gxio_trio_ API can be used to
|
||||
* configure different handlers for different ranges of bus address
|
||||
* space. The user can configure "mapped memory" and "scatter queue"
|
||||
* regions to match incoming packets within 4kB-aligned ranges of bus
|
||||
* addresses. Each range specifies a different set of mapping
|
||||
* parameters to be applied when handling the ingress packet. The
|
||||
* following sections describe how to work with MapMem and scatter
|
||||
* queue regions.
|
||||
*
|
||||
* @subsection trio__mapmem TRIO MapMem Regions
|
||||
*
|
||||
* TRIO mapped memory (or MapMem) regions allow the user to map
|
||||
* incoming read and write requests directly to the application's
|
||||
* memory space. MapMem regions are allocated via
|
||||
* gxio_trio_alloc_memory_maps(). Given an integer MapMem number,
|
||||
* applications can use gxio_trio_init_memory_map() to specify the
|
||||
* range of bus addresses that will match the region and the range of
|
||||
* virtual addresses to which those packets will be applied.
|
||||
*
|
||||
* As with many other gxio APIs, the programmer must be sure to
|
||||
* register memory pages that will be used with MapMem regions. Pages
|
||||
* can be registered with TRIO by allocating an ASID (address space
|
||||
* identifier) and then using gxio_trio_register_page() to register up to
|
||||
* 16 pages with the hardware. The initialization functions for
|
||||
* resources that require registered memory (MapMem, scatter queues,
|
||||
* push DMA, and pull DMA) then take an 'asid' parameter in order to
|
||||
* configure which set of registered pages is used by each resource.
|
||||
*
|
||||
* @subsection trio__scatter_queue TRIO Scatter Queues
|
||||
*
|
||||
* The TRIO shim's scatter queue regions allow users to dynamically
|
||||
* map buffers from a large address space into a small range of bus
|
||||
* addresses. This is particularly helpful for PCIe endpoint devices,
|
||||
* where the host generally limits the size of BARs to tens of
|
||||
* megabytes.
|
||||
*
|
||||
* Each scatter queue consists of a memory map region, a queue of
|
||||
* tile-side buffer VAs to be mapped to that region, and a bus-mapped
|
||||
* "doorbell" register that the remote endpoint can write to trigger a
|
||||
* dequeue of the current buffer VA, thus swapping in a new buffer.
|
||||
* The VAs pushed onto a scatter queue must be 4kB aligned, so
|
||||
* applications may need to use higher-level protocols to inform
|
||||
* remote entities that they should apply some additional, sub-4kB
|
||||
* offset when reading or writing the scatter queue region. For more
|
||||
* information, see the IO Device Guide (UG404).
|
||||
*
|
||||
* @section trio__egress TRIO Egress Hardware Resources
|
||||
*
|
||||
* The TRIO shim supports two mechanisms for egress packet generation:
|
||||
* programmed IO (PIO) and push/pull DMA. PIO allows applications to
|
||||
* create MMIO mappings for PCIe or StreamIO address space, such that
|
||||
* the application can generate word-sized read or write transactions
|
||||
* by issuing load or store instructions. Push and pull DMA are tuned
|
||||
* for larger transactions; they use specialized hardware engines to
|
||||
* transfer large blocks of data at line rate.
|
||||
*
|
||||
* @subsection trio__pio TRIO Programmed IO
|
||||
*
|
||||
* Programmed IO allows applications to create MMIO mappings for PCIe
|
||||
* or StreamIO address space. The hardware PIO regions support access
|
||||
* to PCIe configuration, IO, and memory space, but the gxio_trio API
|
||||
* only supports memory space accesses. PIO regions are allocated
|
||||
* with gxio_trio_alloc_pio_regions() and initialized via
|
||||
* gxio_trio_init_pio_region(). Once a region is bound to a range of
|
||||
* bus address via the initialization function, the application can
|
||||
* use gxio_trio_map_pio_region() to create MMIO mappings from its VA
|
||||
* space onto the range of bus addresses supported by the PIO region.
|
||||
*
|
||||
* @subsection trio_dma TRIO Push and Pull DMA
|
||||
*
|
||||
* The TRIO push and pull DMA engines allow users to copy blocks of
|
||||
* data between application memory and the bus. Push DMA generates
|
||||
* write packets that copy from application memory to the bus and pull
|
||||
* DMA generates read packets that copy from the bus into application
|
||||
* memory. The DMA engines are managed via an API that is very
|
||||
* similar to the mPIPE eDMA interface. For a detailed explanation of
|
||||
* the eDMA queue API, see @ref gxio_mpipe_wrappers.
|
||||
*
|
||||
* Push and pull DMA queues are allocated via
|
||||
* gxio_trio_alloc_push_dma_ring() / gxio_trio_alloc_pull_dma_ring().
|
||||
* Once allocated, users generally use a ::gxio_trio_dma_queue_t
|
||||
* object to manage the queue, providing easy wrappers for reserving
|
||||
* command slots in the DMA command ring, filling those slots, and
|
||||
* waiting for commands to complete. DMA queues can be initialized
|
||||
* via gxio_trio_init_push_dma_queue() or
|
||||
* gxio_trio_init_pull_dma_queue().
|
||||
*
|
||||
* See @ref trio/push_dma/app.c for an example of how to use push DMA.
|
||||
*
|
||||
* @section trio_shortcomings Plans for Future API Revisions
|
||||
*
|
||||
* The simulation framework is incomplete. Future features include:
|
||||
*
|
||||
* - Support for reset and deallocation of resources.
|
||||
*
|
||||
* - Support for pull DMA.
|
||||
*
|
||||
* - Support for interrupt regions and user-space interrupt delivery.
|
||||
*
|
||||
* - Support for getting BAR mappings and reserving regions of BAR
|
||||
* address space.
|
||||
*/
|
||||
#ifndef _GXIO_TRIO_H_
|
||||
#define _GXIO_TRIO_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <gxio/common.h>
|
||||
#include <gxio/dma_queue.h>
|
||||
|
||||
#include <arch/trio_constants.h>
|
||||
#include <arch/trio.h>
|
||||
#include <arch/trio_pcie_intfc.h>
|
||||
#include <arch/trio_pcie_rc.h>
|
||||
#include <arch/trio_shm.h>
|
||||
#include <hv/drv_trio_intf.h>
|
||||
#include <hv/iorpc.h>
|
||||
|
||||
/* A context object used to manage TRIO hardware resources. */
|
||||
typedef struct {
|
||||
|
||||
/* File descriptor for calling up to Linux (and thus the HV). */
|
||||
int fd;
|
||||
|
||||
/* The VA at which the MAC MMIO registers are mapped. */
|
||||
char *mmio_base_mac;
|
||||
|
||||
/* The VA at which the PIO config space are mapped for each PCIe MAC.
|
||||
Gx36 has max 3 PCIe MACs per TRIO shim. */
|
||||
char *mmio_base_pio_cfg[TILEGX_TRIO_PCIES];
|
||||
|
||||
#ifdef USE_SHARED_PCIE_CONFIG_REGION
|
||||
/* Index of the shared PIO region for PCI config access. */
|
||||
int pio_cfg_index;
|
||||
#else
|
||||
/* Index of the PIO region for PCI config access per MAC. */
|
||||
int pio_cfg_index[TILEGX_TRIO_PCIES];
|
||||
#endif
|
||||
|
||||
/* The VA at which the push DMA MMIO registers are mapped. */
|
||||
char *mmio_push_dma[TRIO_NUM_PUSH_DMA_RINGS];
|
||||
|
||||
/* The VA at which the pull DMA MMIO registers are mapped. */
|
||||
char *mmio_pull_dma[TRIO_NUM_PUSH_DMA_RINGS];
|
||||
|
||||
/* Application space ID. */
|
||||
unsigned int asid;
|
||||
|
||||
} gxio_trio_context_t;
|
||||
|
||||
/* Command descriptor for push or pull DMA. */
|
||||
typedef TRIO_DMA_DESC_t gxio_trio_dma_desc_t;
|
||||
|
||||
/* A convenient, thread-safe interface to an eDMA ring. */
|
||||
typedef struct {
|
||||
|
||||
/* State object for tracking head and tail pointers. */
|
||||
__gxio_dma_queue_t dma_queue;
|
||||
|
||||
/* The ring entries. */
|
||||
gxio_trio_dma_desc_t *dma_descs;
|
||||
|
||||
/* The number of entries minus one. */
|
||||
unsigned long mask_num_entries;
|
||||
|
||||
/* The log2() of the number of entries. */
|
||||
unsigned int log2_num_entries;
|
||||
|
||||
} gxio_trio_dma_queue_t;
|
||||
|
||||
/* Initialize a TRIO context.
|
||||
*
|
||||
* This function allocates a TRIO "service domain" and maps the MMIO
|
||||
* registers into the the caller's VA space.
|
||||
*
|
||||
* @param trio_index Which TRIO shim; Gx36 must pass 0.
|
||||
* @param context Context object to be initialized.
|
||||
*/
|
||||
extern int gxio_trio_init(gxio_trio_context_t *context,
|
||||
unsigned int trio_index);
|
||||
|
||||
/* This indicates that an ASID hasn't been allocated. */
|
||||
#define GXIO_ASID_NULL -1
|
||||
|
||||
/* Ordering modes for map memory regions and scatter queue regions. */
|
||||
typedef enum gxio_trio_order_mode_e {
|
||||
/* Writes are not ordered. Reads always wait for previous writes. */
|
||||
GXIO_TRIO_ORDER_MODE_UNORDERED =
|
||||
TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED,
|
||||
/* Both writes and reads wait for previous transactions to complete. */
|
||||
GXIO_TRIO_ORDER_MODE_STRICT =
|
||||
TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT,
|
||||
/* Writes are ordered unless the incoming packet has the
|
||||
relaxed-ordering attributes set. */
|
||||
GXIO_TRIO_ORDER_MODE_OBEY_PACKET =
|
||||
TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD
|
||||
} gxio_trio_order_mode_t;
|
||||
|
||||
/* Initialize a memory mapping region.
|
||||
*
|
||||
* @param context An initialized TRIO context.
|
||||
* @param map A Memory map region allocated by gxio_trio_alloc_memory_map().
|
||||
* @param target_mem VA of backing memory, should be registered via
|
||||
* gxio_trio_register_page() and aligned to 4kB.
|
||||
* @param target_size Length of the memory mapping, must be a multiple
|
||||
* of 4kB.
|
||||
* @param asid ASID to be used for Tile-side address translation.
|
||||
* @param mac MAC number.
|
||||
* @param bus_address Bus address at which the mapping starts.
|
||||
* @param order_mode Memory ordering mode for this mapping.
|
||||
* @return Zero on success, else ::GXIO_TRIO_ERR_BAD_MEMORY_MAP,
|
||||
* GXIO_TRIO_ERR_BAD_ASID, or ::GXIO_TRIO_ERR_BAD_BUS_RANGE.
|
||||
*/
|
||||
extern int gxio_trio_init_memory_map(gxio_trio_context_t *context,
|
||||
unsigned int map, void *target_mem,
|
||||
size_t target_size, unsigned int asid,
|
||||
unsigned int mac, uint64_t bus_address,
|
||||
gxio_trio_order_mode_t order_mode);
|
||||
|
||||
/* Flags that can be passed to resource allocation functions. */
|
||||
enum gxio_trio_alloc_flags_e {
|
||||
GXIO_TRIO_ALLOC_FIXED = HV_TRIO_ALLOC_FIXED,
|
||||
};
|
||||
|
||||
/* Flags that can be passed to memory registration functions. */
|
||||
enum gxio_trio_mem_flags_e {
|
||||
/* Do not fill L3 when writing, and invalidate lines upon egress. */
|
||||
GXIO_TRIO_MEM_FLAG_NT_HINT = IORPC_MEM_BUFFER_FLAG_NT_HINT,
|
||||
|
||||
/* L3 cache fills should only populate IO cache ways. */
|
||||
GXIO_TRIO_MEM_FLAG_IO_PIN = IORPC_MEM_BUFFER_FLAG_IO_PIN,
|
||||
};
|
||||
|
||||
/* Flag indicating a request generator uses a special traffic
|
||||
class. */
|
||||
#define GXIO_TRIO_FLAG_TRAFFIC_CLASS(N) HV_TRIO_FLAG_TC(N)
|
||||
|
||||
/* Flag indicating a request generator uses a virtual function
|
||||
number. */
|
||||
#define GXIO_TRIO_FLAG_VFUNC(N) HV_TRIO_FLAG_VFUNC(N)
|
||||
|
||||
/*****************************************************************
|
||||
* Memory Registration *
|
||||
******************************************************************/
|
||||
|
||||
/* Allocate Application Space Identifiers (ASIDs). Each ASID can
|
||||
* register up to 16 page translations. ASIDs are used by memory map
|
||||
* regions, scatter queues, and DMA queues to translate application
|
||||
* VAs into memory system PAs.
|
||||
*
|
||||
* @param context An initialized TRIO context.
|
||||
* @param count Number of ASIDs required.
|
||||
* @param first Index of first ASID if ::GXIO_TRIO_ALLOC_FIXED flag
|
||||
* is set, otherwise ignored.
|
||||
* @param flags Flag bits, including bits from ::gxio_trio_alloc_flags_e.
|
||||
* @return Index of first ASID, or ::GXIO_TRIO_ERR_NO_ASID if allocation
|
||||
* failed.
|
||||
*/
|
||||
extern int gxio_trio_alloc_asids(gxio_trio_context_t *context,
|
||||
unsigned int count, unsigned int first,
|
||||
unsigned int flags);
|
||||
|
||||
#endif /* ! _GXIO_TRIO_H_ */
|
||||
105
arch/tile/include/gxio/uart.h
Normal file
105
arch/tile/include/gxio/uart.h
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Copyright 2013 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _GXIO_UART_H_
|
||||
#define _GXIO_UART_H_
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#include <hv/drv_uart_intf.h>
|
||||
#include <hv/iorpc.h>
|
||||
|
||||
/*
|
||||
*
|
||||
* An API for manipulating UART interface.
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* The Rshim allows access to the processor's UART interface.
|
||||
*/
|
||||
|
||||
/* A context object used to manage UART resources. */
|
||||
typedef struct {
|
||||
|
||||
/* File descriptor for calling up to the hypervisor. */
|
||||
int fd;
|
||||
|
||||
/* The VA at which our MMIO registers are mapped. */
|
||||
char *mmio_base;
|
||||
|
||||
} gxio_uart_context_t;
|
||||
|
||||
/* Request UART interrupts.
|
||||
*
|
||||
* Request that interrupts be delivered to a tile when the UART's
|
||||
* Receive FIFO is written, or the Write FIFO is read.
|
||||
*
|
||||
* @param context Pointer to a properly initialized gxio_uart_context_t.
|
||||
* @param bind_cpu_x X coordinate of CPU to which interrupt will be delivered.
|
||||
* @param bind_cpu_y Y coordinate of CPU to which interrupt will be delivered.
|
||||
* @param bind_interrupt IPI interrupt number.
|
||||
* @param bind_event Sub-interrupt event bit number; a negative value can
|
||||
* disable the interrupt.
|
||||
* @return Zero if all of the requested UART events were successfully
|
||||
* configured to interrupt.
|
||||
*/
|
||||
extern int gxio_uart_cfg_interrupt(gxio_uart_context_t *context,
|
||||
int bind_cpu_x,
|
||||
int bind_cpu_y,
|
||||
int bind_interrupt, int bind_event);
|
||||
|
||||
/* Initialize a UART context.
|
||||
*
|
||||
* A properly initialized context must be obtained before any of the other
|
||||
* gxio_uart routines may be used.
|
||||
*
|
||||
* @param context Pointer to a gxio_uart_context_t, which will be initialized
|
||||
* by this routine, if it succeeds.
|
||||
* @param uart_index Index of the UART to use.
|
||||
* @return Zero if the context was successfully initialized, else a
|
||||
* GXIO_ERR_xxx error code.
|
||||
*/
|
||||
extern int gxio_uart_init(gxio_uart_context_t *context, int uart_index);
|
||||
|
||||
/* Destroy a UART context.
|
||||
*
|
||||
* Once destroyed, a context may not be used with any gxio_uart routines
|
||||
* other than gxio_uart_init(). After this routine returns, no further
|
||||
* interrupts requested on this context will be delivered. The state and
|
||||
* configuration of the pins which had been attached to this context are
|
||||
* unchanged by this operation.
|
||||
*
|
||||
* @param context Pointer to a gxio_uart_context_t.
|
||||
* @return Zero if the context was successfully destroyed, else a
|
||||
* GXIO_ERR_xxx error code.
|
||||
*/
|
||||
extern int gxio_uart_destroy(gxio_uart_context_t *context);
|
||||
|
||||
/* Write UART register.
|
||||
* @param context Pointer to a gxio_uart_context_t.
|
||||
* @param offset UART register offset.
|
||||
* @param word Data will be wrote to UART reigister.
|
||||
*/
|
||||
extern void gxio_uart_write(gxio_uart_context_t *context, uint64_t offset,
|
||||
uint64_t word);
|
||||
|
||||
/* Read UART register.
|
||||
* @param context Pointer to a gxio_uart_context_t.
|
||||
* @param offset UART register offset.
|
||||
* @return Data read from UART register.
|
||||
*/
|
||||
extern uint64_t gxio_uart_read(gxio_uart_context_t *context, uint64_t offset);
|
||||
|
||||
#endif /* _GXIO_UART_H_ */
|
||||
87
arch/tile/include/gxio/usb_host.h
Normal file
87
arch/tile/include/gxio/usb_host.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright 2012 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
#ifndef _GXIO_USB_H_
|
||||
#define _GXIO_USB_H_
|
||||
|
||||
#include <gxio/common.h>
|
||||
|
||||
#include <hv/drv_usb_host_intf.h>
|
||||
#include <hv/iorpc.h>
|
||||
|
||||
/*
|
||||
*
|
||||
* An API for manipulating general-purpose I/O pins.
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* The USB shim allows access to the processor's Universal Serial Bus
|
||||
* connections.
|
||||
*/
|
||||
|
||||
/* A context object used to manage USB hardware resources. */
|
||||
typedef struct {
|
||||
|
||||
/* File descriptor for calling up to the hypervisor. */
|
||||
int fd;
|
||||
|
||||
/* The VA at which our MMIO registers are mapped. */
|
||||
char *mmio_base;
|
||||
} gxio_usb_host_context_t;
|
||||
|
||||
/* Initialize a USB context.
|
||||
*
|
||||
* A properly initialized context must be obtained before any of the other
|
||||
* gxio_usb_host routines may be used.
|
||||
*
|
||||
* @param context Pointer to a gxio_usb_host_context_t, which will be
|
||||
* initialized by this routine, if it succeeds.
|
||||
* @param usb_index Index of the USB shim to use.
|
||||
* @param is_ehci Nonzero to use the EHCI interface; zero to use the OHCI
|
||||
* intereface.
|
||||
* @return Zero if the context was successfully initialized, else a
|
||||
* GXIO_ERR_xxx error code.
|
||||
*/
|
||||
extern int gxio_usb_host_init(gxio_usb_host_context_t *context, int usb_index,
|
||||
int is_ehci);
|
||||
|
||||
/* Destroy a USB context.
|
||||
*
|
||||
* Once destroyed, a context may not be used with any gxio_usb_host routines
|
||||
* other than gxio_usb_host_init(). After this routine returns, no further
|
||||
* interrupts or signals requested on this context will be delivered. The
|
||||
* state and configuration of the pins which had been attached to this
|
||||
* context are unchanged by this operation.
|
||||
*
|
||||
* @param context Pointer to a gxio_usb_host_context_t.
|
||||
* @return Zero if the context was successfully destroyed, else a
|
||||
* GXIO_ERR_xxx error code.
|
||||
*/
|
||||
extern int gxio_usb_host_destroy(gxio_usb_host_context_t *context);
|
||||
|
||||
/* Retrieve the address of the shim's MMIO registers.
|
||||
*
|
||||
* @param context Pointer to a properly initialized gxio_usb_host_context_t.
|
||||
* @return The address of the shim's MMIO registers.
|
||||
*/
|
||||
extern void *gxio_usb_host_get_reg_start(gxio_usb_host_context_t *context);
|
||||
|
||||
/* Retrieve the length of the shim's MMIO registers.
|
||||
*
|
||||
* @param context Pointer to a properly initialized gxio_usb_host_context_t.
|
||||
* @return The length of the shim's MMIO registers.
|
||||
*/
|
||||
extern size_t gxio_usb_host_get_reg_len(gxio_usb_host_context_t *context);
|
||||
|
||||
#endif /* _GXIO_USB_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue