mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-28 23:08:52 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
17
arch/tile/include/uapi/arch/Kbuild
Normal file
17
arch/tile/include/uapi/arch/Kbuild
Normal file
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@ -0,0 +1,17 @@
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# UAPI Header export list
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header-y += abi.h
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||||
header-y += chip.h
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header-y += chip_tilegx.h
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header-y += chip_tilepro.h
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header-y += icache.h
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header-y += interrupts.h
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||||
header-y += interrupts_32.h
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||||
header-y += interrupts_64.h
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header-y += opcode.h
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header-y += opcode_tilegx.h
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header-y += opcode_tilepro.h
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header-y += sim.h
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||||
header-y += sim_def.h
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header-y += spr_def.h
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header-y += spr_def_32.h
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header-y += spr_def_64.h
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141
arch/tile/include/uapi/arch/abi.h
Normal file
141
arch/tile/include/uapi/arch/abi.h
Normal file
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@ -0,0 +1,141 @@
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|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
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||||
|
||||
/**
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* @file
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*
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||||
* ABI-related register definitions.
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*/
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#ifndef __ARCH_ABI_H__
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#if !defined __need_int_reg_t && !defined __DOXYGEN__
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# define __ARCH_ABI_H__
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# include <arch/chip.h>
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#endif
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/* Provide the basic machine types. */
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#ifndef __INT_REG_BITS
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/** Number of bits in a register. */
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#if defined __tilegx__
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# define __INT_REG_BITS 64
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#elif defined __tilepro__
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# define __INT_REG_BITS 32
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#elif !defined __need_int_reg_t
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# include <arch/chip.h>
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# define __INT_REG_BITS CHIP_WORD_SIZE()
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#else
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# error Unrecognized architecture with __need_int_reg_t
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#endif
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#if __INT_REG_BITS == 64
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#ifndef __ASSEMBLER__
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/** Unsigned type that can hold a register. */
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typedef unsigned long long __uint_reg_t;
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/** Signed type that can hold a register. */
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typedef long long __int_reg_t;
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#endif
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|
||||
/** String prefix to use for printf(). */
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#define __INT_REG_FMT "ll"
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#else
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||||
|
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#ifndef __ASSEMBLER__
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/** Unsigned type that can hold a register. */
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typedef unsigned long __uint_reg_t;
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/** Signed type that can hold a register. */
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typedef long __int_reg_t;
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#endif
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||||
|
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/** String prefix to use for printf(). */
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#define __INT_REG_FMT "l"
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#endif
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#endif /* __INT_REG_BITS */
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#ifndef __need_int_reg_t
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#ifndef __ASSEMBLER__
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/** Unsigned type that can hold a register. */
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typedef __uint_reg_t uint_reg_t;
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||||
/** Signed type that can hold a register. */
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typedef __int_reg_t int_reg_t;
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#endif
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||||
|
||||
/** String prefix to use for printf(). */
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#define INT_REG_FMT __INT_REG_FMT
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|
||||
/** Number of bits in a register. */
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#define INT_REG_BITS __INT_REG_BITS
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|
||||
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||||
/* Registers 0 - 55 are "normal", but some perform special roles. */
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#define TREG_FP 52 /**< Frame pointer. */
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#define TREG_TP 53 /**< Thread pointer. */
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#define TREG_SP 54 /**< Stack pointer. */
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#define TREG_LR 55 /**< Link to calling function PC. */
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|
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/** Index of last normal general-purpose register. */
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#define TREG_LAST_GPR 55
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|
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/* Registers 56 - 62 are "special" network registers. */
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#define TREG_SN 56 /**< Static network access. */
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#define TREG_IDN0 57 /**< IDN demux 0 access. */
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#define TREG_IDN1 58 /**< IDN demux 1 access. */
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#define TREG_UDN0 59 /**< UDN demux 0 access. */
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#define TREG_UDN1 60 /**< UDN demux 1 access. */
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#define TREG_UDN2 61 /**< UDN demux 2 access. */
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#define TREG_UDN3 62 /**< UDN demux 3 access. */
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|
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/* Register 63 is the "special" zero register. */
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#define TREG_ZERO 63 /**< "Zero" register; always reads as "0". */
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/** By convention, this register is used to hold the syscall number. */
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#define TREG_SYSCALL_NR 10
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/** Name of register that holds the syscall number, for use in assembly. */
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#define TREG_SYSCALL_NR_NAME r10
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|
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/**
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* The ABI requires callers to allocate a caller state save area of
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* this many bytes at the bottom of each stack frame.
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*/
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#define C_ABI_SAVE_AREA_SIZE (2 * (INT_REG_BITS / 8))
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/**
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* The operand to an 'info' opcode directing the backtracer to not
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* try to find the calling frame.
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*/
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#define INFO_OP_CANNOT_BACKTRACE 2
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#endif /* !__need_int_reg_t */
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/* Make sure we later can get all the definitions and declarations. */
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#undef __need_int_reg_t
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#endif /* !__ARCH_ABI_H__ */
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21
arch/tile/include/uapi/arch/chip.h
Normal file
21
arch/tile/include/uapi/arch/chip.h
Normal file
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@ -0,0 +1,21 @@
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/*
|
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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||||
*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
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||||
|
||||
#if __tile_chip__ == 1
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#include <arch/chip_tilepro.h>
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#elif defined(__tilegx__)
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#include <arch/chip_tilegx.h>
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||||
#else
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#error Unexpected Tilera chip type
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#endif
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258
arch/tile/include/uapi/arch/chip_tilegx.h
Normal file
258
arch/tile/include/uapi/arch/chip_tilegx.h
Normal file
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|
@ -0,0 +1,258 @@
|
|||
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
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||||
|
||||
/*
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||||
* @file
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* Global header file.
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||||
* This header file specifies defines for TILE-Gx.
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||||
*/
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||||
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||||
#ifndef __ARCH_CHIP_H__
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#define __ARCH_CHIP_H__
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/** Specify chip version.
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* When possible, prefer the CHIP_xxx symbols below for future-proofing.
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* This is intended for cross-compiling; native compilation should
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* use the predefined __tile_chip__ symbol.
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||||
*/
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#define TILE_CHIP 10
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||||
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/** Specify chip revision.
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||||
* This provides for the case of a respin of a particular chip type;
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* the normal value for this symbol is "0".
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||||
* This is intended for cross-compiling; native compilation should
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||||
* use the predefined __tile_chip_rev__ symbol.
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||||
*/
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#define TILE_CHIP_REV 0
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/** The name of this architecture. */
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#define CHIP_ARCH_NAME "tilegx"
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/** The ELF e_machine type for binaries for this chip. */
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#define CHIP_ELF_TYPE() EM_TILEGX
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/** The alternate ELF e_machine type for binaries for this chip. */
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#define CHIP_COMPAT_ELF_TYPE() 0x2597
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/** What is the native word size of the machine? */
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#define CHIP_WORD_SIZE() 64
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/** How many bits of a virtual address are used. Extra bits must be
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* the sign extension of the low bits.
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*/
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#define CHIP_VA_WIDTH() 42
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/** How many bits are in a physical address? */
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#define CHIP_PA_WIDTH() 40
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/** Size of the L2 cache, in bytes. */
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#define CHIP_L2_CACHE_SIZE() 262144
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/** Log size of an L2 cache line in bytes. */
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#define CHIP_L2_LOG_LINE_SIZE() 6
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/** Size of an L2 cache line, in bytes. */
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#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
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/** Associativity of the L2 cache. */
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#define CHIP_L2_ASSOC() 8
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/** Size of the L1 data cache, in bytes. */
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#define CHIP_L1D_CACHE_SIZE() 32768
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/** Log size of an L1 data cache line in bytes. */
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#define CHIP_L1D_LOG_LINE_SIZE() 6
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/** Size of an L1 data cache line, in bytes. */
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#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
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||||
|
||||
/** Associativity of the L1 data cache. */
|
||||
#define CHIP_L1D_ASSOC() 2
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|
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/** Size of the L1 instruction cache, in bytes. */
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#define CHIP_L1I_CACHE_SIZE() 32768
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|
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/** Log size of an L1 instruction cache line in bytes. */
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#define CHIP_L1I_LOG_LINE_SIZE() 6
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/** Size of an L1 instruction cache line, in bytes. */
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#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
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/** Associativity of the L1 instruction cache. */
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||||
#define CHIP_L1I_ASSOC() 2
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|
||||
/** Stride with which flush instructions must be issued. */
|
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#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
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/** Stride with which inv instructions must be issued. */
|
||||
#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
|
||||
|
||||
/** Stride with which finv instructions must be issued. */
|
||||
#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
|
||||
|
||||
/** Can the local cache coherently cache data that is homed elsewhere? */
|
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#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
|
||||
|
||||
/** How many simultaneous outstanding victims can the L2 cache have? */
|
||||
#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
|
||||
|
||||
/** Does the TLB support the NC and NOALLOC bits? */
|
||||
#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
|
||||
|
||||
/** Does the chip support hash-for-home caching? */
|
||||
#define CHIP_HAS_CBOX_HOME_MAP() 1
|
||||
|
||||
/** Number of entries in the chip's home map tables. */
|
||||
#define CHIP_CBOX_HOME_MAP_SIZE() 128
|
||||
|
||||
/** Do uncacheable requests miss in the cache regardless of whether
|
||||
* there is matching data? */
|
||||
#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
|
||||
|
||||
/** Does the mf instruction wait for victims? */
|
||||
#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
|
||||
|
||||
/** Does the chip have an "inv" instruction that doesn't also flush? */
|
||||
#define CHIP_HAS_INV() 1
|
||||
|
||||
/** Does the chip have a "wh64" instruction? */
|
||||
#define CHIP_HAS_WH64() 1
|
||||
|
||||
/** Does this chip have a 'dword_align' instruction? */
|
||||
#define CHIP_HAS_DWORD_ALIGN() 0
|
||||
|
||||
/** Number of performance counters. */
|
||||
#define CHIP_PERFORMANCE_COUNTERS() 4
|
||||
|
||||
/** Does this chip have auxiliary performance counters? */
|
||||
#define CHIP_HAS_AUX_PERF_COUNTERS() 1
|
||||
|
||||
/** Is the CBOX_MSR1 SPR supported? */
|
||||
#define CHIP_HAS_CBOX_MSR1() 0
|
||||
|
||||
/** Is the TILE_RTF_HWM SPR supported? */
|
||||
#define CHIP_HAS_TILE_RTF_HWM() 1
|
||||
|
||||
/** Is the TILE_WRITE_PENDING SPR supported? */
|
||||
#define CHIP_HAS_TILE_WRITE_PENDING() 0
|
||||
|
||||
/** Is the PROC_STATUS SPR supported? */
|
||||
#define CHIP_HAS_PROC_STATUS_SPR() 1
|
||||
|
||||
/** Is the DSTREAM_PF SPR supported? */
|
||||
#define CHIP_HAS_DSTREAM_PF() 1
|
||||
|
||||
/** Log of the number of mshims we have. */
|
||||
#define CHIP_LOG_NUM_MSHIMS() 2
|
||||
|
||||
/** Are the bases of the interrupt vector areas fixed? */
|
||||
#define CHIP_HAS_FIXED_INTVEC_BASE() 0
|
||||
|
||||
/** Are the interrupt masks split up into 2 SPRs? */
|
||||
#define CHIP_HAS_SPLIT_INTR_MASK() 0
|
||||
|
||||
/** Is the cycle count split up into 2 SPRs? */
|
||||
#define CHIP_HAS_SPLIT_CYCLE() 0
|
||||
|
||||
/** Does the chip have a static network? */
|
||||
#define CHIP_HAS_SN() 0
|
||||
|
||||
/** Does the chip have a static network processor? */
|
||||
#define CHIP_HAS_SN_PROC() 0
|
||||
|
||||
/** Size of the L1 static network processor instruction cache, in bytes. */
|
||||
/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
|
||||
|
||||
/** Does the chip have DMA support in each tile? */
|
||||
#define CHIP_HAS_TILE_DMA() 0
|
||||
|
||||
/** Does the chip have the second revision of the directly accessible
|
||||
* dynamic networks? This encapsulates a number of characteristics,
|
||||
* including the absence of the catch-all, the absence of inline message
|
||||
* tags, the absence of support for network context-switching, and so on.
|
||||
*/
|
||||
#define CHIP_HAS_REV1_XDN() 1
|
||||
|
||||
/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
|
||||
#define CHIP_HAS_CMPEXCH() 1
|
||||
|
||||
/** Does the chip have memory-mapped I/O support? */
|
||||
#define CHIP_HAS_MMIO() 1
|
||||
|
||||
/** Does the chip have post-completion interrupts? */
|
||||
#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
|
||||
|
||||
/** Does the chip have native single step support? */
|
||||
#define CHIP_HAS_SINGLE_STEP() 1
|
||||
|
||||
#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
|
||||
|
||||
/** How many entries are present in the instruction TLB? */
|
||||
#define CHIP_ITLB_ENTRIES() 16
|
||||
|
||||
/** How many entries are present in the data TLB? */
|
||||
#define CHIP_DTLB_ENTRIES() 32
|
||||
|
||||
/** How many MAF entries does the XAUI shim have? */
|
||||
#define CHIP_XAUI_MAF_ENTRIES() 32
|
||||
|
||||
/** Does the memory shim have a source-id table? */
|
||||
#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
|
||||
|
||||
/** Does the L1 instruction cache clear on reset? */
|
||||
#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
|
||||
|
||||
/** Does the chip come out of reset with valid coordinates on all tiles?
|
||||
* Note that if defined, this also implies that the upper left is 1,1.
|
||||
*/
|
||||
#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
|
||||
|
||||
/** Does the chip have unified packet formats? */
|
||||
#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
|
||||
|
||||
/** Does the chip support write reordering? */
|
||||
#define CHIP_HAS_WRITE_REORDERING() 1
|
||||
|
||||
/** Does the chip support Y-X routing as well as X-Y? */
|
||||
#define CHIP_HAS_Y_X_ROUTING() 1
|
||||
|
||||
/** Is INTCTRL_3 managed with the correct MPL? */
|
||||
#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
|
||||
|
||||
/** Is it possible to configure the chip to be big-endian? */
|
||||
#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
|
||||
|
||||
/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
|
||||
#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
|
||||
|
||||
/** Is the DIAG_TRACE_WAY SPR supported? */
|
||||
#define CHIP_HAS_DIAG_TRACE_WAY() 0
|
||||
|
||||
/** Is the MEM_STRIPE_CONFIG SPR supported? */
|
||||
#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
|
||||
|
||||
/** Are the TLB_PERF SPRs supported? */
|
||||
#define CHIP_HAS_TLB_PERF() 1
|
||||
|
||||
/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
|
||||
#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
|
||||
|
||||
/** Does the chip support rev1 DMA packets? */
|
||||
#define CHIP_HAS_REV1_DMA_PACKETS() 1
|
||||
|
||||
/** Does the chip have an IPI shim? */
|
||||
#define CHIP_HAS_IPI() 1
|
||||
|
||||
#endif /* !__OPEN_SOURCE__ */
|
||||
#endif /* __ARCH_CHIP_H__ */
|
||||
258
arch/tile/include/uapi/arch/chip_tilepro.h
Normal file
258
arch/tile/include/uapi/arch/chip_tilepro.h
Normal file
|
|
@ -0,0 +1,258 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* @file
|
||||
* Global header file.
|
||||
* This header file specifies defines for TILEPro.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CHIP_H__
|
||||
#define __ARCH_CHIP_H__
|
||||
|
||||
/** Specify chip version.
|
||||
* When possible, prefer the CHIP_xxx symbols below for future-proofing.
|
||||
* This is intended for cross-compiling; native compilation should
|
||||
* use the predefined __tile_chip__ symbol.
|
||||
*/
|
||||
#define TILE_CHIP 1
|
||||
|
||||
/** Specify chip revision.
|
||||
* This provides for the case of a respin of a particular chip type;
|
||||
* the normal value for this symbol is "0".
|
||||
* This is intended for cross-compiling; native compilation should
|
||||
* use the predefined __tile_chip_rev__ symbol.
|
||||
*/
|
||||
#define TILE_CHIP_REV 0
|
||||
|
||||
/** The name of this architecture. */
|
||||
#define CHIP_ARCH_NAME "tilepro"
|
||||
|
||||
/** The ELF e_machine type for binaries for this chip. */
|
||||
#define CHIP_ELF_TYPE() EM_TILEPRO
|
||||
|
||||
/** The alternate ELF e_machine type for binaries for this chip. */
|
||||
#define CHIP_COMPAT_ELF_TYPE() 0x2507
|
||||
|
||||
/** What is the native word size of the machine? */
|
||||
#define CHIP_WORD_SIZE() 32
|
||||
|
||||
/** How many bits of a virtual address are used. Extra bits must be
|
||||
* the sign extension of the low bits.
|
||||
*/
|
||||
#define CHIP_VA_WIDTH() 32
|
||||
|
||||
/** How many bits are in a physical address? */
|
||||
#define CHIP_PA_WIDTH() 36
|
||||
|
||||
/** Size of the L2 cache, in bytes. */
|
||||
#define CHIP_L2_CACHE_SIZE() 65536
|
||||
|
||||
/** Log size of an L2 cache line in bytes. */
|
||||
#define CHIP_L2_LOG_LINE_SIZE() 6
|
||||
|
||||
/** Size of an L2 cache line, in bytes. */
|
||||
#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
|
||||
|
||||
/** Associativity of the L2 cache. */
|
||||
#define CHIP_L2_ASSOC() 4
|
||||
|
||||
/** Size of the L1 data cache, in bytes. */
|
||||
#define CHIP_L1D_CACHE_SIZE() 8192
|
||||
|
||||
/** Log size of an L1 data cache line in bytes. */
|
||||
#define CHIP_L1D_LOG_LINE_SIZE() 4
|
||||
|
||||
/** Size of an L1 data cache line, in bytes. */
|
||||
#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
|
||||
|
||||
/** Associativity of the L1 data cache. */
|
||||
#define CHIP_L1D_ASSOC() 2
|
||||
|
||||
/** Size of the L1 instruction cache, in bytes. */
|
||||
#define CHIP_L1I_CACHE_SIZE() 16384
|
||||
|
||||
/** Log size of an L1 instruction cache line in bytes. */
|
||||
#define CHIP_L1I_LOG_LINE_SIZE() 6
|
||||
|
||||
/** Size of an L1 instruction cache line, in bytes. */
|
||||
#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
|
||||
|
||||
/** Associativity of the L1 instruction cache. */
|
||||
#define CHIP_L1I_ASSOC() 1
|
||||
|
||||
/** Stride with which flush instructions must be issued. */
|
||||
#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
|
||||
|
||||
/** Stride with which inv instructions must be issued. */
|
||||
#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
|
||||
|
||||
/** Stride with which finv instructions must be issued. */
|
||||
#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
|
||||
|
||||
/** Can the local cache coherently cache data that is homed elsewhere? */
|
||||
#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
|
||||
|
||||
/** How many simultaneous outstanding victims can the L2 cache have? */
|
||||
#define CHIP_MAX_OUTSTANDING_VICTIMS() 4
|
||||
|
||||
/** Does the TLB support the NC and NOALLOC bits? */
|
||||
#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
|
||||
|
||||
/** Does the chip support hash-for-home caching? */
|
||||
#define CHIP_HAS_CBOX_HOME_MAP() 1
|
||||
|
||||
/** Number of entries in the chip's home map tables. */
|
||||
#define CHIP_CBOX_HOME_MAP_SIZE() 64
|
||||
|
||||
/** Do uncacheable requests miss in the cache regardless of whether
|
||||
* there is matching data? */
|
||||
#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
|
||||
|
||||
/** Does the mf instruction wait for victims? */
|
||||
#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
|
||||
|
||||
/** Does the chip have an "inv" instruction that doesn't also flush? */
|
||||
#define CHIP_HAS_INV() 1
|
||||
|
||||
/** Does the chip have a "wh64" instruction? */
|
||||
#define CHIP_HAS_WH64() 1
|
||||
|
||||
/** Does this chip have a 'dword_align' instruction? */
|
||||
#define CHIP_HAS_DWORD_ALIGN() 1
|
||||
|
||||
/** Number of performance counters. */
|
||||
#define CHIP_PERFORMANCE_COUNTERS() 4
|
||||
|
||||
/** Does this chip have auxiliary performance counters? */
|
||||
#define CHIP_HAS_AUX_PERF_COUNTERS() 1
|
||||
|
||||
/** Is the CBOX_MSR1 SPR supported? */
|
||||
#define CHIP_HAS_CBOX_MSR1() 1
|
||||
|
||||
/** Is the TILE_RTF_HWM SPR supported? */
|
||||
#define CHIP_HAS_TILE_RTF_HWM() 1
|
||||
|
||||
/** Is the TILE_WRITE_PENDING SPR supported? */
|
||||
#define CHIP_HAS_TILE_WRITE_PENDING() 1
|
||||
|
||||
/** Is the PROC_STATUS SPR supported? */
|
||||
#define CHIP_HAS_PROC_STATUS_SPR() 1
|
||||
|
||||
/** Is the DSTREAM_PF SPR supported? */
|
||||
#define CHIP_HAS_DSTREAM_PF() 0
|
||||
|
||||
/** Log of the number of mshims we have. */
|
||||
#define CHIP_LOG_NUM_MSHIMS() 2
|
||||
|
||||
/** Are the bases of the interrupt vector areas fixed? */
|
||||
#define CHIP_HAS_FIXED_INTVEC_BASE() 1
|
||||
|
||||
/** Are the interrupt masks split up into 2 SPRs? */
|
||||
#define CHIP_HAS_SPLIT_INTR_MASK() 1
|
||||
|
||||
/** Is the cycle count split up into 2 SPRs? */
|
||||
#define CHIP_HAS_SPLIT_CYCLE() 1
|
||||
|
||||
/** Does the chip have a static network? */
|
||||
#define CHIP_HAS_SN() 1
|
||||
|
||||
/** Does the chip have a static network processor? */
|
||||
#define CHIP_HAS_SN_PROC() 0
|
||||
|
||||
/** Size of the L1 static network processor instruction cache, in bytes. */
|
||||
/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 1 */
|
||||
|
||||
/** Does the chip have DMA support in each tile? */
|
||||
#define CHIP_HAS_TILE_DMA() 1
|
||||
|
||||
/** Does the chip have the second revision of the directly accessible
|
||||
* dynamic networks? This encapsulates a number of characteristics,
|
||||
* including the absence of the catch-all, the absence of inline message
|
||||
* tags, the absence of support for network context-switching, and so on.
|
||||
*/
|
||||
#define CHIP_HAS_REV1_XDN() 0
|
||||
|
||||
/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
|
||||
#define CHIP_HAS_CMPEXCH() 0
|
||||
|
||||
/** Does the chip have memory-mapped I/O support? */
|
||||
#define CHIP_HAS_MMIO() 0
|
||||
|
||||
/** Does the chip have post-completion interrupts? */
|
||||
#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0
|
||||
|
||||
/** Does the chip have native single step support? */
|
||||
#define CHIP_HAS_SINGLE_STEP() 0
|
||||
|
||||
#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
|
||||
|
||||
/** How many entries are present in the instruction TLB? */
|
||||
#define CHIP_ITLB_ENTRIES() 16
|
||||
|
||||
/** How many entries are present in the data TLB? */
|
||||
#define CHIP_DTLB_ENTRIES() 16
|
||||
|
||||
/** How many MAF entries does the XAUI shim have? */
|
||||
#define CHIP_XAUI_MAF_ENTRIES() 32
|
||||
|
||||
/** Does the memory shim have a source-id table? */
|
||||
#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
|
||||
|
||||
/** Does the L1 instruction cache clear on reset? */
|
||||
#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
|
||||
|
||||
/** Does the chip come out of reset with valid coordinates on all tiles?
|
||||
* Note that if defined, this also implies that the upper left is 1,1.
|
||||
*/
|
||||
#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
|
||||
|
||||
/** Does the chip have unified packet formats? */
|
||||
#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
|
||||
|
||||
/** Does the chip support write reordering? */
|
||||
#define CHIP_HAS_WRITE_REORDERING() 1
|
||||
|
||||
/** Does the chip support Y-X routing as well as X-Y? */
|
||||
#define CHIP_HAS_Y_X_ROUTING() 1
|
||||
|
||||
/** Is INTCTRL_3 managed with the correct MPL? */
|
||||
#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
|
||||
|
||||
/** Is it possible to configure the chip to be big-endian? */
|
||||
#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
|
||||
|
||||
/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
|
||||
#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 1
|
||||
|
||||
/** Is the DIAG_TRACE_WAY SPR supported? */
|
||||
#define CHIP_HAS_DIAG_TRACE_WAY() 1
|
||||
|
||||
/** Is the MEM_STRIPE_CONFIG SPR supported? */
|
||||
#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
|
||||
|
||||
/** Are the TLB_PERF SPRs supported? */
|
||||
#define CHIP_HAS_TLB_PERF() 1
|
||||
|
||||
/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
|
||||
#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 1
|
||||
|
||||
/** Does the chip support rev1 DMA packets? */
|
||||
#define CHIP_HAS_REV1_DMA_PACKETS() 1
|
||||
|
||||
/** Does the chip have an IPI shim? */
|
||||
#define CHIP_HAS_IPI() 0
|
||||
|
||||
#endif /* !__OPEN_SOURCE__ */
|
||||
#endif /* __ARCH_CHIP_H__ */
|
||||
93
arch/tile/include/uapi/arch/icache.h
Normal file
93
arch/tile/include/uapi/arch/icache.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Support for invalidating bytes in the instruction cache.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ICACHE_H__
|
||||
#define __ARCH_ICACHE_H__
|
||||
|
||||
#include <arch/chip.h>
|
||||
|
||||
|
||||
/**
|
||||
* Invalidate the instruction cache for the given range of memory.
|
||||
*
|
||||
* @param addr The start of memory to be invalidated.
|
||||
* @param size The number of bytes to be invalidated.
|
||||
* @param page_size The system's page size, e.g. getpagesize() in userspace.
|
||||
* This value must be a power of two no larger than the page containing
|
||||
* the code to be invalidated. If the value is smaller than the actual page
|
||||
* size, this function will still work, but may run slower than necessary.
|
||||
*/
|
||||
static __inline void
|
||||
invalidate_icache(const void* addr, unsigned long size,
|
||||
unsigned long page_size)
|
||||
{
|
||||
const unsigned long cache_way_size =
|
||||
CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
|
||||
unsigned long max_useful_size;
|
||||
const char* start, *end;
|
||||
long num_passes;
|
||||
|
||||
if (__builtin_expect(size == 0, 0))
|
||||
return;
|
||||
|
||||
#ifdef __tilegx__
|
||||
/* Limit the number of bytes visited to avoid redundant iterations. */
|
||||
max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
|
||||
|
||||
/* No PA aliasing is possible, so one pass always suffices. */
|
||||
num_passes = 1;
|
||||
#else
|
||||
/* Limit the number of bytes visited to avoid redundant iterations. */
|
||||
max_useful_size = cache_way_size;
|
||||
|
||||
/*
|
||||
* Compute how many passes we need (we'll treat 0 as if it were 1).
|
||||
* This works because we know the page size is a power of two.
|
||||
*/
|
||||
num_passes = cache_way_size >> __builtin_ctzl(page_size);
|
||||
#endif
|
||||
|
||||
if (__builtin_expect(size > max_useful_size, 0))
|
||||
size = max_useful_size;
|
||||
|
||||
/* Locate the first and last bytes to be invalidated. */
|
||||
start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
|
||||
end = (const char*)addr + size - 1;
|
||||
|
||||
__insn_mf();
|
||||
|
||||
do
|
||||
{
|
||||
const char* p;
|
||||
|
||||
for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
|
||||
__insn_icoh(p);
|
||||
|
||||
start += page_size;
|
||||
end += page_size;
|
||||
}
|
||||
while (--num_passes > 0);
|
||||
|
||||
__insn_drain();
|
||||
}
|
||||
|
||||
|
||||
#endif /* __ARCH_ICACHE_H__ */
|
||||
19
arch/tile/include/uapi/arch/interrupts.h
Normal file
19
arch/tile/include/uapi/arch/interrupts.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifdef __tilegx__
|
||||
#include <arch/interrupts_64.h>
|
||||
#else
|
||||
#include <arch/interrupts_32.h>
|
||||
#endif
|
||||
309
arch/tile/include/uapi/arch/interrupts_32.h
Normal file
309
arch/tile/include/uapi/arch/interrupts_32.h
Normal file
|
|
@ -0,0 +1,309 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_INTERRUPTS_H__
|
||||
#define __ARCH_INTERRUPTS_H__
|
||||
|
||||
#ifndef __KERNEL__
|
||||
/** Mask for an interrupt. */
|
||||
/* Note: must handle breaking interrupts into high and low words manually. */
|
||||
#define INT_MASK_LO(intno) (1 << (intno))
|
||||
#define INT_MASK_HI(intno) (1 << ((intno) - 32))
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define INT_MASK(intno) (1ULL << (intno))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/** Where a given interrupt executes */
|
||||
#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
|
||||
|
||||
/** Where to store a vector for a given interrupt. */
|
||||
#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
|
||||
|
||||
/** The base address of user-level interrupts. */
|
||||
#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
|
||||
|
||||
|
||||
/** Additional synthetic interrupt. */
|
||||
#define INT_BREAKPOINT (63)
|
||||
|
||||
#define INT_ITLB_MISS 0
|
||||
#define INT_MEM_ERROR 1
|
||||
#define INT_ILL 2
|
||||
#define INT_GPV 3
|
||||
#define INT_SN_ACCESS 4
|
||||
#define INT_IDN_ACCESS 5
|
||||
#define INT_UDN_ACCESS 6
|
||||
#define INT_IDN_REFILL 7
|
||||
#define INT_UDN_REFILL 8
|
||||
#define INT_IDN_COMPLETE 9
|
||||
#define INT_UDN_COMPLETE 10
|
||||
#define INT_SWINT_3 11
|
||||
#define INT_SWINT_2 12
|
||||
#define INT_SWINT_1 13
|
||||
#define INT_SWINT_0 14
|
||||
#define INT_UNALIGN_DATA 15
|
||||
#define INT_DTLB_MISS 16
|
||||
#define INT_DTLB_ACCESS 17
|
||||
#define INT_DMATLB_MISS 18
|
||||
#define INT_DMATLB_ACCESS 19
|
||||
#define INT_SNITLB_MISS 20
|
||||
#define INT_SN_NOTIFY 21
|
||||
#define INT_SN_FIREWALL 22
|
||||
#define INT_IDN_FIREWALL 23
|
||||
#define INT_UDN_FIREWALL 24
|
||||
#define INT_TILE_TIMER 25
|
||||
#define INT_IDN_TIMER 26
|
||||
#define INT_UDN_TIMER 27
|
||||
#define INT_DMA_NOTIFY 28
|
||||
#define INT_IDN_CA 29
|
||||
#define INT_UDN_CA 30
|
||||
#define INT_IDN_AVAIL 31
|
||||
#define INT_UDN_AVAIL 32
|
||||
#define INT_PERF_COUNT 33
|
||||
#define INT_INTCTRL_3 34
|
||||
#define INT_INTCTRL_2 35
|
||||
#define INT_INTCTRL_1 36
|
||||
#define INT_INTCTRL_0 37
|
||||
#define INT_BOOT_ACCESS 38
|
||||
#define INT_WORLD_ACCESS 39
|
||||
#define INT_I_ASID 40
|
||||
#define INT_D_ASID 41
|
||||
#define INT_DMA_ASID 42
|
||||
#define INT_SNI_ASID 43
|
||||
#define INT_DMA_CPL 44
|
||||
#define INT_SN_CPL 45
|
||||
#define INT_DOUBLE_FAULT 46
|
||||
#define INT_SN_STATIC_ACCESS 47
|
||||
#define INT_AUX_PERF_COUNT 48
|
||||
|
||||
#define NUM_INTERRUPTS 49
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define QUEUED_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_DMATLB_MISS) | \
|
||||
(1ULL << INT_DMATLB_ACCESS) | \
|
||||
(1ULL << INT_SNITLB_MISS) | \
|
||||
(1ULL << INT_SN_NOTIFY) | \
|
||||
(1ULL << INT_SN_FIREWALL) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_DMA_NOTIFY) | \
|
||||
(1ULL << INT_IDN_CA) | \
|
||||
(1ULL << INT_UDN_CA) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DMA_ASID) | \
|
||||
(1ULL << INT_SNI_ASID) | \
|
||||
(1ULL << INT_DMA_CPL) | \
|
||||
(1ULL << INT_SN_CPL) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
0)
|
||||
#define NONQUEUED_INTERRUPTS ( \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_SN_ACCESS) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_IDN_REFILL) | \
|
||||
(1ULL << INT_UDN_REFILL) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
(1ULL << INT_SN_STATIC_ACCESS) | \
|
||||
0)
|
||||
#define CRITICAL_MASKED_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_DMATLB_MISS) | \
|
||||
(1ULL << INT_DMATLB_ACCESS) | \
|
||||
(1ULL << INT_SNITLB_MISS) | \
|
||||
(1ULL << INT_SN_NOTIFY) | \
|
||||
(1ULL << INT_SN_FIREWALL) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_DMA_NOTIFY) | \
|
||||
(1ULL << INT_IDN_CA) | \
|
||||
(1ULL << INT_UDN_CA) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
0)
|
||||
#define CRITICAL_UNMASKED_INTERRUPTS ( \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_SN_ACCESS) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_IDN_REFILL) | \
|
||||
(1ULL << INT_UDN_REFILL) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DMA_ASID) | \
|
||||
(1ULL << INT_SNI_ASID) | \
|
||||
(1ULL << INT_DMA_CPL) | \
|
||||
(1ULL << INT_SN_CPL) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
(1ULL << INT_SN_STATIC_ACCESS) | \
|
||||
0)
|
||||
#define MASKABLE_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_IDN_REFILL) | \
|
||||
(1ULL << INT_UDN_REFILL) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_DMATLB_MISS) | \
|
||||
(1ULL << INT_DMATLB_ACCESS) | \
|
||||
(1ULL << INT_SNITLB_MISS) | \
|
||||
(1ULL << INT_SN_NOTIFY) | \
|
||||
(1ULL << INT_SN_FIREWALL) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_DMA_NOTIFY) | \
|
||||
(1ULL << INT_IDN_CA) | \
|
||||
(1ULL << INT_UDN_CA) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
0)
|
||||
#define UNMASKABLE_INTERRUPTS ( \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_SN_ACCESS) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DMA_ASID) | \
|
||||
(1ULL << INT_SNI_ASID) | \
|
||||
(1ULL << INT_DMA_CPL) | \
|
||||
(1ULL << INT_SN_CPL) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
(1ULL << INT_SN_STATIC_ACCESS) | \
|
||||
0)
|
||||
#define SYNC_INTERRUPTS ( \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_SN_ACCESS) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_IDN_REFILL) | \
|
||||
(1ULL << INT_UDN_REFILL) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
(1ULL << INT_SN_STATIC_ACCESS) | \
|
||||
0)
|
||||
#define NON_SYNC_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_DMATLB_MISS) | \
|
||||
(1ULL << INT_DMATLB_ACCESS) | \
|
||||
(1ULL << INT_SNITLB_MISS) | \
|
||||
(1ULL << INT_SN_NOTIFY) | \
|
||||
(1ULL << INT_SN_FIREWALL) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_DMA_NOTIFY) | \
|
||||
(1ULL << INT_IDN_CA) | \
|
||||
(1ULL << INT_UDN_CA) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DMA_ASID) | \
|
||||
(1ULL << INT_SNI_ASID) | \
|
||||
(1ULL << INT_DMA_CPL) | \
|
||||
(1ULL << INT_SN_CPL) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
0)
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
#endif /* !__ARCH_INTERRUPTS_H__ */
|
||||
278
arch/tile/include/uapi/arch/interrupts_64.h
Normal file
278
arch/tile/include/uapi/arch/interrupts_64.h
Normal file
|
|
@ -0,0 +1,278 @@
|
|||
/*
|
||||
* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_INTERRUPTS_H__
|
||||
#define __ARCH_INTERRUPTS_H__
|
||||
|
||||
#ifndef __KERNEL__
|
||||
/** Mask for an interrupt. */
|
||||
#ifdef __ASSEMBLER__
|
||||
/* Note: must handle breaking interrupts into high and low words manually. */
|
||||
#define INT_MASK(intno) (1 << (intno))
|
||||
#else
|
||||
#define INT_MASK(intno) (1ULL << (intno))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/** Where a given interrupt executes */
|
||||
#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
|
||||
|
||||
/** Where to store a vector for a given interrupt. */
|
||||
#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
|
||||
|
||||
/** The base address of user-level interrupts. */
|
||||
#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
|
||||
|
||||
|
||||
/** Additional synthetic interrupt. */
|
||||
#define INT_BREAKPOINT (63)
|
||||
|
||||
#define INT_MEM_ERROR 0
|
||||
#define INT_SINGLE_STEP_3 1
|
||||
#define INT_SINGLE_STEP_2 2
|
||||
#define INT_SINGLE_STEP_1 3
|
||||
#define INT_SINGLE_STEP_0 4
|
||||
#define INT_IDN_COMPLETE 5
|
||||
#define INT_UDN_COMPLETE 6
|
||||
#define INT_ITLB_MISS 7
|
||||
#define INT_ILL 8
|
||||
#define INT_GPV 9
|
||||
#define INT_IDN_ACCESS 10
|
||||
#define INT_UDN_ACCESS 11
|
||||
#define INT_SWINT_3 12
|
||||
#define INT_SWINT_2 13
|
||||
#define INT_SWINT_1 14
|
||||
#define INT_SWINT_0 15
|
||||
#define INT_ILL_TRANS 16
|
||||
#define INT_UNALIGN_DATA 17
|
||||
#define INT_DTLB_MISS 18
|
||||
#define INT_DTLB_ACCESS 19
|
||||
#define INT_IDN_FIREWALL 20
|
||||
#define INT_UDN_FIREWALL 21
|
||||
#define INT_TILE_TIMER 22
|
||||
#define INT_AUX_TILE_TIMER 23
|
||||
#define INT_IDN_TIMER 24
|
||||
#define INT_UDN_TIMER 25
|
||||
#define INT_IDN_AVAIL 26
|
||||
#define INT_UDN_AVAIL 27
|
||||
#define INT_IPI_3 28
|
||||
#define INT_IPI_2 29
|
||||
#define INT_IPI_1 30
|
||||
#define INT_IPI_0 31
|
||||
#define INT_PERF_COUNT 32
|
||||
#define INT_AUX_PERF_COUNT 33
|
||||
#define INT_INTCTRL_3 34
|
||||
#define INT_INTCTRL_2 35
|
||||
#define INT_INTCTRL_1 36
|
||||
#define INT_INTCTRL_0 37
|
||||
#define INT_BOOT_ACCESS 38
|
||||
#define INT_WORLD_ACCESS 39
|
||||
#define INT_I_ASID 40
|
||||
#define INT_D_ASID 41
|
||||
#define INT_DOUBLE_FAULT 42
|
||||
|
||||
#define NUM_INTERRUPTS 43
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define QUEUED_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_AUX_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_IPI_3) | \
|
||||
(1ULL << INT_IPI_2) | \
|
||||
(1ULL << INT_IPI_1) | \
|
||||
(1ULL << INT_IPI_0) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
0)
|
||||
#define NONQUEUED_INTERRUPTS ( \
|
||||
(1ULL << INT_SINGLE_STEP_3) | \
|
||||
(1ULL << INT_SINGLE_STEP_2) | \
|
||||
(1ULL << INT_SINGLE_STEP_1) | \
|
||||
(1ULL << INT_SINGLE_STEP_0) | \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_ILL_TRANS) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
0)
|
||||
#define CRITICAL_MASKED_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_SINGLE_STEP_3) | \
|
||||
(1ULL << INT_SINGLE_STEP_2) | \
|
||||
(1ULL << INT_SINGLE_STEP_1) | \
|
||||
(1ULL << INT_SINGLE_STEP_0) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_AUX_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_IPI_3) | \
|
||||
(1ULL << INT_IPI_2) | \
|
||||
(1ULL << INT_IPI_1) | \
|
||||
(1ULL << INT_IPI_0) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
0)
|
||||
#define CRITICAL_UNMASKED_INTERRUPTS ( \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_ILL_TRANS) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
0)
|
||||
#define MASKABLE_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_SINGLE_STEP_3) | \
|
||||
(1ULL << INT_SINGLE_STEP_2) | \
|
||||
(1ULL << INT_SINGLE_STEP_1) | \
|
||||
(1ULL << INT_SINGLE_STEP_0) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_AUX_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_IPI_3) | \
|
||||
(1ULL << INT_IPI_2) | \
|
||||
(1ULL << INT_IPI_1) | \
|
||||
(1ULL << INT_IPI_0) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
0)
|
||||
#define UNMASKABLE_INTERRUPTS ( \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_ILL_TRANS) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
0)
|
||||
#define SYNC_INTERRUPTS ( \
|
||||
(1ULL << INT_SINGLE_STEP_3) | \
|
||||
(1ULL << INT_SINGLE_STEP_2) | \
|
||||
(1ULL << INT_SINGLE_STEP_1) | \
|
||||
(1ULL << INT_SINGLE_STEP_0) | \
|
||||
(1ULL << INT_IDN_COMPLETE) | \
|
||||
(1ULL << INT_UDN_COMPLETE) | \
|
||||
(1ULL << INT_ITLB_MISS) | \
|
||||
(1ULL << INT_ILL) | \
|
||||
(1ULL << INT_GPV) | \
|
||||
(1ULL << INT_IDN_ACCESS) | \
|
||||
(1ULL << INT_UDN_ACCESS) | \
|
||||
(1ULL << INT_SWINT_3) | \
|
||||
(1ULL << INT_SWINT_2) | \
|
||||
(1ULL << INT_SWINT_1) | \
|
||||
(1ULL << INT_SWINT_0) | \
|
||||
(1ULL << INT_ILL_TRANS) | \
|
||||
(1ULL << INT_UNALIGN_DATA) | \
|
||||
(1ULL << INT_DTLB_MISS) | \
|
||||
(1ULL << INT_DTLB_ACCESS) | \
|
||||
0)
|
||||
#define NON_SYNC_INTERRUPTS ( \
|
||||
(1ULL << INT_MEM_ERROR) | \
|
||||
(1ULL << INT_IDN_FIREWALL) | \
|
||||
(1ULL << INT_UDN_FIREWALL) | \
|
||||
(1ULL << INT_TILE_TIMER) | \
|
||||
(1ULL << INT_AUX_TILE_TIMER) | \
|
||||
(1ULL << INT_IDN_TIMER) | \
|
||||
(1ULL << INT_UDN_TIMER) | \
|
||||
(1ULL << INT_IDN_AVAIL) | \
|
||||
(1ULL << INT_UDN_AVAIL) | \
|
||||
(1ULL << INT_IPI_3) | \
|
||||
(1ULL << INT_IPI_2) | \
|
||||
(1ULL << INT_IPI_1) | \
|
||||
(1ULL << INT_IPI_0) | \
|
||||
(1ULL << INT_PERF_COUNT) | \
|
||||
(1ULL << INT_AUX_PERF_COUNT) | \
|
||||
(1ULL << INT_INTCTRL_3) | \
|
||||
(1ULL << INT_INTCTRL_2) | \
|
||||
(1ULL << INT_INTCTRL_1) | \
|
||||
(1ULL << INT_INTCTRL_0) | \
|
||||
(1ULL << INT_BOOT_ACCESS) | \
|
||||
(1ULL << INT_WORLD_ACCESS) | \
|
||||
(1ULL << INT_I_ASID) | \
|
||||
(1ULL << INT_D_ASID) | \
|
||||
(1ULL << INT_DOUBLE_FAULT) | \
|
||||
0)
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
#endif /* !__ARCH_INTERRUPTS_H__ */
|
||||
21
arch/tile/include/uapi/arch/opcode.h
Normal file
21
arch/tile/include/uapi/arch/opcode.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#if defined(__tilepro__)
|
||||
#include <arch/opcode_tilepro.h>
|
||||
#elif defined(__tilegx__)
|
||||
#include <arch/opcode_tilegx.h>
|
||||
#else
|
||||
#error Unexpected Tilera chip type
|
||||
#endif
|
||||
1406
arch/tile/include/uapi/arch/opcode_tilegx.h
Normal file
1406
arch/tile/include/uapi/arch/opcode_tilegx.h
Normal file
File diff suppressed because it is too large
Load diff
1472
arch/tile/include/uapi/arch/opcode_tilepro.h
Normal file
1472
arch/tile/include/uapi/arch/opcode_tilepro.h
Normal file
File diff suppressed because it is too large
Load diff
643
arch/tile/include/uapi/arch/sim.h
Normal file
643
arch/tile/include/uapi/arch/sim.h
Normal file
|
|
@ -0,0 +1,643 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Provides an API for controlling the simulator at runtime.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup arch_sim
|
||||
* @{
|
||||
*
|
||||
* An API for controlling the simulator at runtime.
|
||||
*
|
||||
* The simulator's behavior can be modified while it is running.
|
||||
* For example, human-readable trace output can be enabled and disabled
|
||||
* around code of interest.
|
||||
*
|
||||
* There are two ways to modify simulator behavior:
|
||||
* programmatically, by calling various sim_* functions, and
|
||||
* interactively, by entering commands like "sim set functional true"
|
||||
* at the tile-monitor prompt. Typing "sim help" at that prompt provides
|
||||
* a list of interactive commands.
|
||||
*
|
||||
* All interactive commands can also be executed programmatically by
|
||||
* passing a string to the sim_command function.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_SIM_H__
|
||||
#define __ARCH_SIM_H__
|
||||
|
||||
#include <arch/sim_def.h>
|
||||
#include <arch/abi.h>
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <arch/spr_def.h>
|
||||
|
||||
|
||||
/**
|
||||
* Return true if the current program is running under a simulator,
|
||||
* rather than on real hardware. If running on hardware, other "sim_xxx()"
|
||||
* calls have no useful effect.
|
||||
*/
|
||||
static inline int
|
||||
sim_is_simulator(void)
|
||||
{
|
||||
return __insn_mfspr(SPR_SIM_CONTROL) != 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Checkpoint the simulator state to a checkpoint file.
|
||||
*
|
||||
* The checkpoint file name is either the default or the name specified
|
||||
* on the command line with "--checkpoint-file".
|
||||
*/
|
||||
static __inline void
|
||||
sim_checkpoint(void)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_CHECKPOINT);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Report whether or not various kinds of simulator tracing are enabled.
|
||||
*
|
||||
* @return The bitwise OR of these values:
|
||||
*
|
||||
* SIM_TRACE_CYCLES (--trace-cycles),
|
||||
* SIM_TRACE_ROUTER (--trace-router),
|
||||
* SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
|
||||
* SIM_TRACE_DISASM (--trace-disasm),
|
||||
* SIM_TRACE_STALL_INFO (--trace-stall-info)
|
||||
* SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
|
||||
* SIM_TRACE_L2_CACHE (--trace-l2)
|
||||
* SIM_TRACE_LINES (--trace-lines)
|
||||
*/
|
||||
static __inline unsigned int
|
||||
sim_get_tracing(void)
|
||||
{
|
||||
return __insn_mfspr(SPR_SIM_CONTROL) & SIM_TRACE_FLAG_MASK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Turn on or off different kinds of simulator tracing.
|
||||
*
|
||||
* @param mask Either one of these special values:
|
||||
*
|
||||
* SIM_TRACE_NONE (turns off tracing),
|
||||
* SIM_TRACE_ALL (turns on all possible tracing).
|
||||
*
|
||||
* or the bitwise OR of these values:
|
||||
*
|
||||
* SIM_TRACE_CYCLES (--trace-cycles),
|
||||
* SIM_TRACE_ROUTER (--trace-router),
|
||||
* SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
|
||||
* SIM_TRACE_DISASM (--trace-disasm),
|
||||
* SIM_TRACE_STALL_INFO (--trace-stall-info)
|
||||
* SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
|
||||
* SIM_TRACE_L2_CACHE (--trace-l2)
|
||||
* SIM_TRACE_LINES (--trace-lines)
|
||||
*/
|
||||
static __inline void
|
||||
sim_set_tracing(unsigned int mask)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_TRACE_SPR_ARG(mask));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Request dumping of different kinds of simulator state.
|
||||
*
|
||||
* @param mask Either this special value:
|
||||
*
|
||||
* SIM_DUMP_ALL (dump all known state)
|
||||
*
|
||||
* or the bitwise OR of these values:
|
||||
*
|
||||
* SIM_DUMP_REGS (the register file),
|
||||
* SIM_DUMP_SPRS (the SPRs),
|
||||
* SIM_DUMP_ITLB (the iTLB),
|
||||
* SIM_DUMP_DTLB (the dTLB),
|
||||
* SIM_DUMP_L1I (the L1 I-cache),
|
||||
* SIM_DUMP_L1D (the L1 D-cache),
|
||||
* SIM_DUMP_L2 (the L2 cache),
|
||||
* SIM_DUMP_SNREGS (the switch register file),
|
||||
* SIM_DUMP_SNITLB (the switch iTLB),
|
||||
* SIM_DUMP_SNL1I (the switch L1 I-cache),
|
||||
* SIM_DUMP_BACKTRACE (the current backtrace)
|
||||
*/
|
||||
static __inline void
|
||||
sim_dump(unsigned int mask)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_DUMP_SPR_ARG(mask));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Print a string to the simulator stdout.
|
||||
*
|
||||
* @param str The string to be written.
|
||||
*/
|
||||
static __inline void
|
||||
sim_print(const char* str)
|
||||
{
|
||||
for ( ; *str != '\0'; str++)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
|
||||
(*str << _SIM_CONTROL_OPERATOR_BITS));
|
||||
}
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
|
||||
(SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Print a string to the simulator stdout.
|
||||
*
|
||||
* @param str The string to be written (a newline is automatically added).
|
||||
*/
|
||||
static __inline void
|
||||
sim_print_string(const char* str)
|
||||
{
|
||||
for ( ; *str != '\0'; str++)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
|
||||
(*str << _SIM_CONTROL_OPERATOR_BITS));
|
||||
}
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
|
||||
(SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Execute a simulator command string.
|
||||
*
|
||||
* Type 'sim help' at the tile-monitor prompt to learn what commands
|
||||
* are available. Note the use of the tile-monitor "sim" command to
|
||||
* pass commands to the simulator.
|
||||
*
|
||||
* The argument to sim_command() does not include the leading "sim"
|
||||
* prefix used at the tile-monitor prompt; for example, you might call
|
||||
* sim_command("trace disasm").
|
||||
*/
|
||||
static __inline void
|
||||
sim_command(const char* str)
|
||||
{
|
||||
int c;
|
||||
do
|
||||
{
|
||||
c = *str++;
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_COMMAND |
|
||||
(c << _SIM_CONTROL_OPERATOR_BITS));
|
||||
}
|
||||
while (c);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#ifndef __DOXYGEN__
|
||||
|
||||
/**
|
||||
* The underlying implementation of "_sim_syscall()".
|
||||
*
|
||||
* We use extra "and" instructions to ensure that all the values
|
||||
* we are passing to the simulator are actually valid in the registers
|
||||
* (i.e. returned from memory) prior to the SIM_CONTROL spr.
|
||||
*/
|
||||
static __inline long _sim_syscall0(int val)
|
||||
{
|
||||
long result;
|
||||
__asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
|
||||
: "=R00" (result) : "R00" (val));
|
||||
return result;
|
||||
}
|
||||
|
||||
static __inline long _sim_syscall1(int val, long arg1)
|
||||
{
|
||||
long result;
|
||||
__asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
|
||||
: "=R00" (result) : "R00" (val), "R01" (arg1));
|
||||
return result;
|
||||
}
|
||||
|
||||
static __inline long _sim_syscall2(int val, long arg1, long arg2)
|
||||
{
|
||||
long result;
|
||||
__asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
|
||||
: "=R00" (result)
|
||||
: "R00" (val), "R01" (arg1), "R02" (arg2));
|
||||
return result;
|
||||
}
|
||||
|
||||
/* Note that _sim_syscall3() and higher are technically at risk of
|
||||
receiving an interrupt right before the mtspr bundle, in which case
|
||||
the register values for arguments 3 and up may still be in flight
|
||||
to the core from a stack frame reload. */
|
||||
|
||||
static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3)
|
||||
{
|
||||
long result;
|
||||
__asm__ __volatile__ ("{ and zero, r3, r3 };"
|
||||
"{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
|
||||
: "=R00" (result)
|
||||
: "R00" (val), "R01" (arg1), "R02" (arg2),
|
||||
"R03" (arg3));
|
||||
return result;
|
||||
}
|
||||
|
||||
static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3,
|
||||
long arg4)
|
||||
{
|
||||
long result;
|
||||
__asm__ __volatile__ ("{ and zero, r3, r4 };"
|
||||
"{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
|
||||
: "=R00" (result)
|
||||
: "R00" (val), "R01" (arg1), "R02" (arg2),
|
||||
"R03" (arg3), "R04" (arg4));
|
||||
return result;
|
||||
}
|
||||
|
||||
static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3,
|
||||
long arg4, long arg5)
|
||||
{
|
||||
long result;
|
||||
__asm__ __volatile__ ("{ and zero, r3, r4; and zero, r5, r5 };"
|
||||
"{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
|
||||
: "=R00" (result)
|
||||
: "R00" (val), "R01" (arg1), "R02" (arg2),
|
||||
"R03" (arg3), "R04" (arg4), "R05" (arg5));
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* Make a special syscall to the simulator itself, if running under
|
||||
* simulation. This is used as the implementation of other functions
|
||||
* and should not be used outside this file.
|
||||
*
|
||||
* @param syscall_num The simulator syscall number.
|
||||
* @param nr The number of additional arguments provided.
|
||||
*
|
||||
* @return Varies by syscall.
|
||||
*/
|
||||
#define _sim_syscall(syscall_num, nr, args...) \
|
||||
_sim_syscall##nr( \
|
||||
((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \
|
||||
##args)
|
||||
|
||||
|
||||
/* Values for the "access_mask" parameters below. */
|
||||
#define SIM_WATCHPOINT_READ 1
|
||||
#define SIM_WATCHPOINT_WRITE 2
|
||||
#define SIM_WATCHPOINT_EXECUTE 4
|
||||
|
||||
|
||||
static __inline int
|
||||
sim_add_watchpoint(unsigned int process_id,
|
||||
unsigned long address,
|
||||
unsigned long size,
|
||||
unsigned int access_mask,
|
||||
unsigned long user_data)
|
||||
{
|
||||
return _sim_syscall(SIM_SYSCALL_ADD_WATCHPOINT, 5, process_id,
|
||||
address, size, access_mask, user_data);
|
||||
}
|
||||
|
||||
|
||||
static __inline int
|
||||
sim_remove_watchpoint(unsigned int process_id,
|
||||
unsigned long address,
|
||||
unsigned long size,
|
||||
unsigned int access_mask,
|
||||
unsigned long user_data)
|
||||
{
|
||||
return _sim_syscall(SIM_SYSCALL_REMOVE_WATCHPOINT, 5, process_id,
|
||||
address, size, access_mask, user_data);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Return value from sim_query_watchpoint.
|
||||
*/
|
||||
struct SimQueryWatchpointStatus
|
||||
{
|
||||
/**
|
||||
* 0 if a watchpoint fired, 1 if no watchpoint fired, or -1 for
|
||||
* error (meaning a bad process_id).
|
||||
*/
|
||||
int syscall_status;
|
||||
|
||||
/**
|
||||
* The address of the watchpoint that fired (this is the address
|
||||
* passed to sim_add_watchpoint, not an address within that range
|
||||
* that actually triggered the watchpoint).
|
||||
*/
|
||||
unsigned long address;
|
||||
|
||||
/** The arbitrary user_data installed by sim_add_watchpoint. */
|
||||
unsigned long user_data;
|
||||
};
|
||||
|
||||
|
||||
static __inline struct SimQueryWatchpointStatus
|
||||
sim_query_watchpoint(unsigned int process_id)
|
||||
{
|
||||
struct SimQueryWatchpointStatus status;
|
||||
long val = SIM_CONTROL_SYSCALL |
|
||||
(SIM_SYSCALL_QUERY_WATCHPOINT << _SIM_CONTROL_OPERATOR_BITS);
|
||||
__asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
|
||||
: "=R00" (status.syscall_status),
|
||||
"=R01" (status.address),
|
||||
"=R02" (status.user_data)
|
||||
: "R00" (val), "R01" (process_id));
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/* On the simulator, confirm lines have been evicted everywhere. */
|
||||
static __inline void
|
||||
sim_validate_lines_evicted(unsigned long long pa, unsigned long length)
|
||||
{
|
||||
#ifdef __LP64__
|
||||
_sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 2, pa, length);
|
||||
#else
|
||||
_sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 4,
|
||||
0 /* dummy */, (long)(pa), (long)(pa >> 32), length);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* Return the current CPU speed in cycles per second. */
|
||||
static __inline long
|
||||
sim_query_cpu_speed(void)
|
||||
{
|
||||
return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0);
|
||||
}
|
||||
|
||||
#endif /* !__DOXYGEN__ */
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* Modify the shaping parameters of a shim.
|
||||
*
|
||||
* @param shim The shim to modify. One of:
|
||||
* SIM_CONTROL_SHAPING_GBE_0
|
||||
* SIM_CONTROL_SHAPING_GBE_1
|
||||
* SIM_CONTROL_SHAPING_GBE_2
|
||||
* SIM_CONTROL_SHAPING_GBE_3
|
||||
* SIM_CONTROL_SHAPING_XGBE_0
|
||||
* SIM_CONTROL_SHAPING_XGBE_1
|
||||
*
|
||||
* @param type The type of shaping. This should be the same type of
|
||||
* shaping that is already in place on the shim. One of:
|
||||
* SIM_CONTROL_SHAPING_MULTIPLIER
|
||||
* SIM_CONTROL_SHAPING_PPS
|
||||
* SIM_CONTROL_SHAPING_BPS
|
||||
*
|
||||
* @param units The magnitude of the rate. One of:
|
||||
* SIM_CONTROL_SHAPING_UNITS_SINGLE
|
||||
* SIM_CONTROL_SHAPING_UNITS_KILO
|
||||
* SIM_CONTROL_SHAPING_UNITS_MEGA
|
||||
* SIM_CONTROL_SHAPING_UNITS_GIGA
|
||||
*
|
||||
* @param rate The rate to which to change it. This must fit in
|
||||
* SIM_CONTROL_SHAPING_RATE_BITS bits or a warning is issued and
|
||||
* the shaping is not changed.
|
||||
*
|
||||
* @return 0 if no problems were detected in the arguments to sim_set_shaping
|
||||
* or 1 if problems were detected (for example, rate does not fit in 17 bits).
|
||||
*/
|
||||
static __inline int
|
||||
sim_set_shaping(unsigned shim,
|
||||
unsigned type,
|
||||
unsigned units,
|
||||
unsigned rate)
|
||||
{
|
||||
if ((rate & ~((1 << SIM_CONTROL_SHAPING_RATE_BITS) - 1)) != 0)
|
||||
return 1;
|
||||
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_SHAPING_SPR_ARG(shim, type, units, rate));
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef __tilegx__
|
||||
|
||||
/** Enable a set of mPIPE links. Pass a -1 link_mask to enable all links. */
|
||||
static __inline void
|
||||
sim_enable_mpipe_links(unsigned mpipe, unsigned long link_mask)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL,
|
||||
(SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
|
||||
(mpipe << 8) | (1 << 16) | ((uint_reg_t)link_mask << 32)));
|
||||
}
|
||||
|
||||
/** Disable a set of mPIPE links. Pass a -1 link_mask to disable all links. */
|
||||
static __inline void
|
||||
sim_disable_mpipe_links(unsigned mpipe, unsigned long link_mask)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL,
|
||||
(SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
|
||||
(mpipe << 8) | (0 << 16) | ((uint_reg_t)link_mask << 32)));
|
||||
}
|
||||
|
||||
#endif /* __tilegx__ */
|
||||
|
||||
|
||||
/*
|
||||
* An API for changing "functional" mode.
|
||||
*/
|
||||
|
||||
#ifndef __DOXYGEN__
|
||||
|
||||
#define sim_enable_functional() \
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_ENABLE_FUNCTIONAL)
|
||||
|
||||
#define sim_disable_functional() \
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_DISABLE_FUNCTIONAL)
|
||||
|
||||
#endif /* __DOXYGEN__ */
|
||||
|
||||
|
||||
/*
|
||||
* Profiler support.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Turn profiling on for the current task.
|
||||
*
|
||||
* Note that this has no effect if run in an environment without
|
||||
* profiling support (thus, the proper flags to the simulator must
|
||||
* be supplied).
|
||||
*/
|
||||
static __inline void
|
||||
sim_profiler_enable(void)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_ENABLE);
|
||||
}
|
||||
|
||||
|
||||
/** Turn profiling off for the current task. */
|
||||
static __inline void
|
||||
sim_profiler_disable(void)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_DISABLE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Turn profiling on or off for the current task.
|
||||
*
|
||||
* @param enabled If true, turns on profiling. If false, turns it off.
|
||||
*
|
||||
* Note that this has no effect if run in an environment without
|
||||
* profiling support (thus, the proper flags to the simulator must
|
||||
* be supplied).
|
||||
*/
|
||||
static __inline void
|
||||
sim_profiler_set_enabled(int enabled)
|
||||
{
|
||||
int val =
|
||||
enabled ? SIM_CONTROL_PROFILER_ENABLE : SIM_CONTROL_PROFILER_DISABLE;
|
||||
__insn_mtspr(SPR_SIM_CONTROL, val);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Return true if and only if profiling is currently enabled
|
||||
* for the current task.
|
||||
*
|
||||
* This returns false even if sim_profiler_enable() was called
|
||||
* if the current execution environment does not support profiling.
|
||||
*/
|
||||
static __inline int
|
||||
sim_profiler_is_enabled(void)
|
||||
{
|
||||
return ((__insn_mfspr(SPR_SIM_CONTROL) & SIM_PROFILER_ENABLED_MASK) != 0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Reset profiling counters to zero for the current task.
|
||||
*
|
||||
* Resetting can be done while profiling is enabled. It does not affect
|
||||
* the chip-wide profiling counters.
|
||||
*/
|
||||
static __inline void
|
||||
sim_profiler_clear(void)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_CLEAR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Enable specified chip-level profiling counters.
|
||||
*
|
||||
* Does not affect the per-task profiling counters.
|
||||
*
|
||||
* @param mask Either this special value:
|
||||
*
|
||||
* SIM_CHIP_ALL (enables all chip-level components).
|
||||
*
|
||||
* or the bitwise OR of these values:
|
||||
*
|
||||
* SIM_CHIP_MEMCTL (enable all memory controllers)
|
||||
* SIM_CHIP_XAUI (enable all XAUI controllers)
|
||||
* SIM_CHIP_MPIPE (enable all MPIPE controllers)
|
||||
*/
|
||||
static __inline void
|
||||
sim_profiler_chip_enable(unsigned int mask)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Disable specified chip-level profiling counters.
|
||||
*
|
||||
* Does not affect the per-task profiling counters.
|
||||
*
|
||||
* @param mask Either this special value:
|
||||
*
|
||||
* SIM_CHIP_ALL (disables all chip-level components).
|
||||
*
|
||||
* or the bitwise OR of these values:
|
||||
*
|
||||
* SIM_CHIP_MEMCTL (disable all memory controllers)
|
||||
* SIM_CHIP_XAUI (disable all XAUI controllers)
|
||||
* SIM_CHIP_MPIPE (disable all MPIPE controllers)
|
||||
*/
|
||||
static __inline void
|
||||
sim_profiler_chip_disable(unsigned int mask)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Reset specified chip-level profiling counters to zero.
|
||||
*
|
||||
* Does not affect the per-task profiling counters.
|
||||
*
|
||||
* @param mask Either this special value:
|
||||
*
|
||||
* SIM_CHIP_ALL (clears all chip-level components).
|
||||
*
|
||||
* or the bitwise OR of these values:
|
||||
*
|
||||
* SIM_CHIP_MEMCTL (clear all memory controllers)
|
||||
* SIM_CHIP_XAUI (clear all XAUI controllers)
|
||||
* SIM_CHIP_MPIPE (clear all MPIPE controllers)
|
||||
*/
|
||||
static __inline void
|
||||
sim_profiler_chip_clear(unsigned int mask)
|
||||
{
|
||||
__insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Event support.
|
||||
*/
|
||||
|
||||
#ifndef __DOXYGEN__
|
||||
|
||||
static __inline void
|
||||
sim_event_begin(unsigned int x)
|
||||
{
|
||||
#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
|
||||
__insn_mtspr(SPR_EVENT_BEGIN, x);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline void
|
||||
sim_event_end(unsigned int x)
|
||||
{
|
||||
#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
|
||||
__insn_mtspr(SPR_EVENT_END, x);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* !__DOXYGEN__ */
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
#endif /* !__ARCH_SIM_H__ */
|
||||
|
||||
/** @} */
|
||||
505
arch/tile/include/uapi/arch/sim_def.h
Normal file
505
arch/tile/include/uapi/arch/sim_def.h
Normal file
|
|
@ -0,0 +1,505 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Some low-level simulator definitions.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_SIM_DEF_H__
|
||||
#define __ARCH_SIM_DEF_H__
|
||||
|
||||
|
||||
/**
|
||||
* Internal: the low bits of the SIM_CONTROL_* SPR values specify
|
||||
* the operation to perform, and the remaining bits are
|
||||
* an operation-specific parameter (often unused).
|
||||
*/
|
||||
#define _SIM_CONTROL_OPERATOR_BITS 8
|
||||
|
||||
|
||||
/*
|
||||
* Values which can be written to SPR_SIM_CONTROL.
|
||||
*/
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, stops profiling. */
|
||||
#define SIM_CONTROL_PROFILER_DISABLE 0
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, starts profiling. */
|
||||
#define SIM_CONTROL_PROFILER_ENABLE 1
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, clears profiling counters. */
|
||||
#define SIM_CONTROL_PROFILER_CLEAR 2
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, checkpoints the simulator. */
|
||||
#define SIM_CONTROL_CHECKPOINT 3
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
|
||||
* sets the tracing mask to the given mask. See "sim_set_tracing()".
|
||||
*/
|
||||
#define SIM_CONTROL_SET_TRACING 4
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
|
||||
* dumps the requested items of machine state to the log.
|
||||
*/
|
||||
#define SIM_CONTROL_DUMP 5
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */
|
||||
#define SIM_CONTROL_PROFILER_CHIP_CLEAR 6
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, disables chip-level profiling. */
|
||||
#define SIM_CONTROL_PROFILER_CHIP_DISABLE 7
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, enables chip-level profiling. */
|
||||
#define SIM_CONTROL_PROFILER_CHIP_ENABLE 8
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, enables chip-level functional mode */
|
||||
#define SIM_CONTROL_ENABLE_FUNCTIONAL 9
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */
|
||||
#define SIM_CONTROL_DISABLE_FUNCTIONAL 10
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, enables chip-level functional mode.
|
||||
* All tiles must perform this write for functional mode to be enabled.
|
||||
* Ignored in naked boot mode unless --functional is specified.
|
||||
* WARNING: Only the hypervisor startup code should use this!
|
||||
*/
|
||||
#define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
|
||||
* writes a string directly to the simulator output. Written to once for
|
||||
* each character in the string, plus a final NUL. Instead of NUL,
|
||||
* you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY".
|
||||
*/
|
||||
/* ISSUE: Document the meaning of "newline", and the handling of NUL. */
|
||||
#define SIM_CONTROL_PUTC 12
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, clears the --grind-coherence state for
|
||||
* this core. This is intended to be used before a loop that will
|
||||
* invalidate the cache by loading new data and evicting all current data.
|
||||
* Generally speaking, this API should only be used by system code.
|
||||
*/
|
||||
#define SIM_CONTROL_GRINDER_CLEAR 13
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, shuts down the simulator. */
|
||||
#define SIM_CONTROL_SHUTDOWN 14
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
|
||||
* indicates that a fork syscall just created the given process.
|
||||
*/
|
||||
#define SIM_CONTROL_OS_FORK 15
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
|
||||
* indicates that an exit syscall was just executed by the given process.
|
||||
*/
|
||||
#define SIM_CONTROL_OS_EXIT 16
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
|
||||
* indicates that the OS just switched to the given process.
|
||||
*/
|
||||
#define SIM_CONTROL_OS_SWITCH 17
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
|
||||
* indicates that an exec syscall was just executed. Written to once for
|
||||
* each character in the executable name, plus a final NUL.
|
||||
*/
|
||||
#define SIM_CONTROL_OS_EXEC 18
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
|
||||
* indicates that an interpreter (PT_INTERP) was loaded. Written to once
|
||||
* for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a
|
||||
* hex load address starting with "0x", and "PATH" is the executable name.
|
||||
*/
|
||||
#define SIM_CONTROL_OS_INTERP 19
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
|
||||
* indicates that a dll was loaded. Written to once for each character
|
||||
* in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load
|
||||
* address starting with "0x", and "PATH" is the executable name.
|
||||
*/
|
||||
#define SIM_CONTROL_DLOPEN 20
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
|
||||
* indicates that a dll was unloaded. Written to once for each character
|
||||
* in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load
|
||||
* address starting with "0x".
|
||||
*/
|
||||
#define SIM_CONTROL_DLCLOSE 21
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8),
|
||||
* indicates whether to allow data reads to remotely-cached
|
||||
* dirty cache lines to be cached locally without grinder warnings or
|
||||
* assertions (used by Linux kernel fast memcpy).
|
||||
*/
|
||||
#define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, enables memory tracing. */
|
||||
#define SIM_CONTROL_ENABLE_MEM_LOGGING 23
|
||||
|
||||
/** If written to SPR_SIM_CONTROL, disables memory tracing. */
|
||||
#define SIM_CONTROL_DISABLE_MEM_LOGGING 24
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, changes the shaping parameters of one of
|
||||
* the gbe or xgbe shims. Must specify the shim id, the type, the units, and
|
||||
* the rate, as defined in SIM_SHAPING_SPR_ARG.
|
||||
*/
|
||||
#define SIM_CONTROL_SHAPING 25
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with character (shifted by 8),
|
||||
* requests that a simulator command be executed. Written to once for each
|
||||
* character in the command, plus a final NUL.
|
||||
*/
|
||||
#define SIM_CONTROL_COMMAND 26
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, indicates that the simulated system
|
||||
* is panicking, to allow debugging via --debug-on-panic.
|
||||
*/
|
||||
#define SIM_CONTROL_PANIC 27
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, triggers a simulator syscall.
|
||||
* See "sim_syscall()" for more info.
|
||||
*/
|
||||
#define SIM_CONTROL_SYSCALL 32
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
|
||||
* provides the pid that subsequent SIM_CONTROL_OS_FORK writes should
|
||||
* use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH.
|
||||
*/
|
||||
#define SIM_CONTROL_OS_FORK_PARENT 33
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
|
||||
* (shifted by 8), clears the pending magic data section. The cleared
|
||||
* pending magic data section and any subsequently appended magic bytes
|
||||
* will only take effect when the classifier blast programmer is run.
|
||||
*/
|
||||
#define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
|
||||
* (shifted by 8) and a byte of data (shifted by 16), appends that byte
|
||||
* to the shim's pending magic data section. The pending magic data
|
||||
* section takes effect when the classifier blast programmer is run.
|
||||
*/
|
||||
#define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35
|
||||
|
||||
/**
|
||||
* If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
|
||||
* (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a
|
||||
* mask of links (shifted by 32), enable or disable the corresponding
|
||||
* mPIPE links.
|
||||
*/
|
||||
#define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36
|
||||
|
||||
|
||||
/*
|
||||
* Syscall numbers for use with "sim_syscall()".
|
||||
*/
|
||||
|
||||
/** Syscall number for sim_add_watchpoint(). */
|
||||
#define SIM_SYSCALL_ADD_WATCHPOINT 2
|
||||
|
||||
/** Syscall number for sim_remove_watchpoint(). */
|
||||
#define SIM_SYSCALL_REMOVE_WATCHPOINT 3
|
||||
|
||||
/** Syscall number for sim_query_watchpoint(). */
|
||||
#define SIM_SYSCALL_QUERY_WATCHPOINT 4
|
||||
|
||||
/**
|
||||
* Syscall number that asserts that the cache lines whose 64-bit PA
|
||||
* is passed as the second argument to sim_syscall(), and over a
|
||||
* range passed as the third argument, are no longer in cache.
|
||||
* The simulator raises an error if this is not the case.
|
||||
*/
|
||||
#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
|
||||
|
||||
/** Syscall number for sim_query_cpu_speed(). */
|
||||
#define SIM_SYSCALL_QUERY_CPU_SPEED 6
|
||||
|
||||
|
||||
/*
|
||||
* Bit masks which can be shifted by 8, combined with
|
||||
* SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup arch_sim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Enable --trace-cycle when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_CYCLES 0x01
|
||||
|
||||
/** Enable --trace-router when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_ROUTER 0x02
|
||||
|
||||
/** Enable --trace-register-writes when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_REGISTER_WRITES 0x04
|
||||
|
||||
/** Enable --trace-disasm when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_DISASM 0x08
|
||||
|
||||
/** Enable --trace-stall-info when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_STALL_INFO 0x10
|
||||
|
||||
/** Enable --trace-memory-controller when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_MEMORY_CONTROLLER 0x20
|
||||
|
||||
/** Enable --trace-l2 when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_L2_CACHE 0x40
|
||||
|
||||
/** Enable --trace-lines when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_LINES 0x80
|
||||
|
||||
/** Turn off all tracing when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_NONE 0
|
||||
|
||||
/** Turn on all tracing when passed to simulator_set_tracing(). */
|
||||
#define SIM_TRACE_ALL (-1)
|
||||
|
||||
/** @} */
|
||||
|
||||
/** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */
|
||||
#define SIM_TRACE_SPR_ARG(mask) \
|
||||
(SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
|
||||
|
||||
|
||||
/*
|
||||
* Bit masks which can be shifted by 8, combined with
|
||||
* SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup arch_sim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Dump the general-purpose registers. */
|
||||
#define SIM_DUMP_REGS 0x001
|
||||
|
||||
/** Dump the SPRs. */
|
||||
#define SIM_DUMP_SPRS 0x002
|
||||
|
||||
/** Dump the ITLB. */
|
||||
#define SIM_DUMP_ITLB 0x004
|
||||
|
||||
/** Dump the DTLB. */
|
||||
#define SIM_DUMP_DTLB 0x008
|
||||
|
||||
/** Dump the L1 I-cache. */
|
||||
#define SIM_DUMP_L1I 0x010
|
||||
|
||||
/** Dump the L1 D-cache. */
|
||||
#define SIM_DUMP_L1D 0x020
|
||||
|
||||
/** Dump the L2 cache. */
|
||||
#define SIM_DUMP_L2 0x040
|
||||
|
||||
/** Dump the switch registers. */
|
||||
#define SIM_DUMP_SNREGS 0x080
|
||||
|
||||
/** Dump the switch ITLB. */
|
||||
#define SIM_DUMP_SNITLB 0x100
|
||||
|
||||
/** Dump the switch L1 I-cache. */
|
||||
#define SIM_DUMP_SNL1I 0x200
|
||||
|
||||
/** Dump the current backtrace. */
|
||||
#define SIM_DUMP_BACKTRACE 0x400
|
||||
|
||||
/** Only dump valid lines in caches. */
|
||||
#define SIM_DUMP_VALID_LINES 0x800
|
||||
|
||||
/** Dump everything that is dumpable. */
|
||||
#define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES)
|
||||
|
||||
/** @} */
|
||||
|
||||
/** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */
|
||||
#define SIM_DUMP_SPR_ARG(mask) \
|
||||
(SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
|
||||
|
||||
|
||||
/*
|
||||
* Bit masks which can be shifted by 8, combined with
|
||||
* SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup arch_sim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Use with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
|
||||
#define SIM_CHIP_MEMCTL 0x001
|
||||
|
||||
/** Use with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
|
||||
#define SIM_CHIP_XAUI 0x002
|
||||
|
||||
/** Use with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
|
||||
#define SIM_CHIP_PCIE 0x004
|
||||
|
||||
/** Use with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
|
||||
#define SIM_CHIP_MPIPE 0x008
|
||||
|
||||
/** Use with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
|
||||
#define SIM_CHIP_TRIO 0x010
|
||||
|
||||
/** Reference all chip devices. */
|
||||
#define SIM_CHIP_ALL (-1)
|
||||
|
||||
/** @} */
|
||||
|
||||
/** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */
|
||||
#define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \
|
||||
(SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
|
||||
|
||||
/** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/
|
||||
#define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \
|
||||
(SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
|
||||
|
||||
/** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */
|
||||
#define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \
|
||||
(SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
|
||||
|
||||
|
||||
|
||||
/* Shim bitrate controls. */
|
||||
|
||||
/** The number of bits used to store the shim id. */
|
||||
#define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3
|
||||
|
||||
/**
|
||||
* @addtogroup arch_sim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Change the gbe 0 bitrate. */
|
||||
#define SIM_CONTROL_SHAPING_GBE_0 0x0
|
||||
|
||||
/** Change the gbe 1 bitrate. */
|
||||
#define SIM_CONTROL_SHAPING_GBE_1 0x1
|
||||
|
||||
/** Change the gbe 2 bitrate. */
|
||||
#define SIM_CONTROL_SHAPING_GBE_2 0x2
|
||||
|
||||
/** Change the gbe 3 bitrate. */
|
||||
#define SIM_CONTROL_SHAPING_GBE_3 0x3
|
||||
|
||||
/** Change the xgbe 0 bitrate. */
|
||||
#define SIM_CONTROL_SHAPING_XGBE_0 0x4
|
||||
|
||||
/** Change the xgbe 1 bitrate. */
|
||||
#define SIM_CONTROL_SHAPING_XGBE_1 0x5
|
||||
|
||||
/** The type of shaping to do. */
|
||||
#define SIM_CONTROL_SHAPING_TYPE_BITS 2
|
||||
|
||||
/** Control the multiplier. */
|
||||
#define SIM_CONTROL_SHAPING_MULTIPLIER 0
|
||||
|
||||
/** Control the PPS. */
|
||||
#define SIM_CONTROL_SHAPING_PPS 1
|
||||
|
||||
/** Control the BPS. */
|
||||
#define SIM_CONTROL_SHAPING_BPS 2
|
||||
|
||||
/** The number of bits for the units for the shaping parameter. */
|
||||
#define SIM_CONTROL_SHAPING_UNITS_BITS 2
|
||||
|
||||
/** Provide a number in single units. */
|
||||
#define SIM_CONTROL_SHAPING_UNITS_SINGLE 0
|
||||
|
||||
/** Provide a number in kilo units. */
|
||||
#define SIM_CONTROL_SHAPING_UNITS_KILO 1
|
||||
|
||||
/** Provide a number in mega units. */
|
||||
#define SIM_CONTROL_SHAPING_UNITS_MEGA 2
|
||||
|
||||
/** Provide a number in giga units. */
|
||||
#define SIM_CONTROL_SHAPING_UNITS_GIGA 3
|
||||
|
||||
/** @} */
|
||||
|
||||
/** How many bits are available for the rate. */
|
||||
#define SIM_CONTROL_SHAPING_RATE_BITS \
|
||||
(32 - (_SIM_CONTROL_OPERATOR_BITS + \
|
||||
SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
|
||||
SIM_CONTROL_SHAPING_TYPE_BITS + \
|
||||
SIM_CONTROL_SHAPING_UNITS_BITS))
|
||||
|
||||
/** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */
|
||||
#define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \
|
||||
(SIM_CONTROL_SHAPING | \
|
||||
((shim) | \
|
||||
((type) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS)) | \
|
||||
((units) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
|
||||
SIM_CONTROL_SHAPING_TYPE_BITS)) | \
|
||||
((rate) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
|
||||
SIM_CONTROL_SHAPING_TYPE_BITS + \
|
||||
SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS)
|
||||
|
||||
|
||||
/*
|
||||
* Values returned when reading SPR_SIM_CONTROL.
|
||||
* ISSUE: These names should share a longer common prefix.
|
||||
*/
|
||||
|
||||
/**
|
||||
* When reading SPR_SIM_CONTROL, the mask of simulator tracing bits
|
||||
* (SIM_TRACE_xxx values).
|
||||
*/
|
||||
#define SIM_TRACE_FLAG_MASK 0xFFFF
|
||||
|
||||
/** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */
|
||||
#define SIM_PROFILER_ENABLED_MASK 0x10000
|
||||
|
||||
|
||||
/*
|
||||
* Special arguments for "SIM_CONTROL_PUTC".
|
||||
*/
|
||||
|
||||
/**
|
||||
* Flag value for forcing a PUTC string-flush, including
|
||||
* coordinate/cycle prefix and newline.
|
||||
*/
|
||||
#define SIM_PUTC_FLUSH_STRING 0x100
|
||||
|
||||
/**
|
||||
* Flag value for forcing a PUTC binary-data-flush, which skips the
|
||||
* prefix and does not append a newline.
|
||||
*/
|
||||
#define SIM_PUTC_FLUSH_BINARY 0x101
|
||||
|
||||
|
||||
#endif /* __ARCH_SIM_DEF_H__ */
|
||||
26
arch/tile/include/uapi/arch/spr_def.h
Normal file
26
arch/tile/include/uapi/arch/spr_def.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI__ARCH_SPR_DEF_H__
|
||||
#define _UAPI__ARCH_SPR_DEF_H__
|
||||
|
||||
/* Include the proper base SPR definition file. */
|
||||
#ifdef __tilegx__
|
||||
#include <arch/spr_def_64.h>
|
||||
#else
|
||||
#include <arch/spr_def_32.h>
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _UAPI__ARCH_SPR_DEF_H__ */
|
||||
255
arch/tile/include/uapi/arch/spr_def_32.h
Normal file
255
arch/tile/include/uapi/arch/spr_def_32.h
Normal file
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __DOXYGEN__
|
||||
|
||||
#ifndef __ARCH_SPR_DEF_32_H__
|
||||
#define __ARCH_SPR_DEF_32_H__
|
||||
|
||||
#define SPR_AUX_PERF_COUNT_0 0x6005
|
||||
#define SPR_AUX_PERF_COUNT_1 0x6006
|
||||
#define SPR_AUX_PERF_COUNT_CTL 0x6007
|
||||
#define SPR_AUX_PERF_COUNT_STS 0x6008
|
||||
#define SPR_CYCLE_HIGH 0x4e06
|
||||
#define SPR_CYCLE_LOW 0x4e07
|
||||
#define SPR_DMA_BYTE 0x3900
|
||||
#define SPR_DMA_CHUNK_SIZE 0x3901
|
||||
#define SPR_DMA_CTR 0x3902
|
||||
#define SPR_DMA_CTR__REQUEST_MASK 0x1
|
||||
#define SPR_DMA_CTR__SUSPEND_MASK 0x2
|
||||
#define SPR_DMA_DST_ADDR 0x3903
|
||||
#define SPR_DMA_DST_CHUNK_ADDR 0x3904
|
||||
#define SPR_DMA_SRC_ADDR 0x3905
|
||||
#define SPR_DMA_SRC_CHUNK_ADDR 0x3906
|
||||
#define SPR_DMA_STATUS__DONE_MASK 0x1
|
||||
#define SPR_DMA_STATUS__BUSY_MASK 0x2
|
||||
#define SPR_DMA_STATUS__RUNNING_MASK 0x10
|
||||
#define SPR_DMA_STRIDE 0x3907
|
||||
#define SPR_DMA_USER_STATUS 0x3908
|
||||
#define SPR_DONE 0x4e08
|
||||
#define SPR_EVENT_BEGIN 0x4e0d
|
||||
#define SPR_EVENT_END 0x4e0e
|
||||
#define SPR_EX_CONTEXT_0_0 0x4a05
|
||||
#define SPR_EX_CONTEXT_0_1 0x4a06
|
||||
#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
|
||||
#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
|
||||
#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
|
||||
#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
|
||||
#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
|
||||
#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
|
||||
#define SPR_EX_CONTEXT_1_0 0x4805
|
||||
#define SPR_EX_CONTEXT_1_1 0x4806
|
||||
#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
|
||||
#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
|
||||
#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
|
||||
#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
|
||||
#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
|
||||
#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
|
||||
#define SPR_EX_CONTEXT_2_0 0x4605
|
||||
#define SPR_EX_CONTEXT_2_1 0x4606
|
||||
#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
|
||||
#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
|
||||
#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
|
||||
#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
|
||||
#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
|
||||
#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
|
||||
#define SPR_FAIL 0x4e09
|
||||
#define SPR_IDN_AVAIL_EN 0x3e05
|
||||
#define SPR_IDN_CA_DATA 0x0b00
|
||||
#define SPR_IDN_DATA_AVAIL 0x0b03
|
||||
#define SPR_IDN_DEADLOCK_TIMEOUT 0x3406
|
||||
#define SPR_IDN_DEMUX_CA_COUNT 0x0a05
|
||||
#define SPR_IDN_DEMUX_COUNT_0 0x0a06
|
||||
#define SPR_IDN_DEMUX_COUNT_1 0x0a07
|
||||
#define SPR_IDN_DEMUX_CTL 0x0a08
|
||||
#define SPR_IDN_DEMUX_QUEUE_SEL 0x0a0a
|
||||
#define SPR_IDN_DEMUX_STATUS 0x0a0b
|
||||
#define SPR_IDN_DEMUX_WRITE_FIFO 0x0a0c
|
||||
#define SPR_IDN_DIRECTION_PROTECT 0x2e05
|
||||
#define SPR_IDN_PENDING 0x0a0e
|
||||
#define SPR_IDN_REFILL_EN 0x0e05
|
||||
#define SPR_IDN_SP_FIFO_DATA 0x0a0f
|
||||
#define SPR_IDN_SP_FIFO_SEL 0x0a10
|
||||
#define SPR_IDN_SP_FREEZE 0x0a11
|
||||
#define SPR_IDN_SP_FREEZE__SP_FRZ_MASK 0x1
|
||||
#define SPR_IDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
|
||||
#define SPR_IDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
|
||||
#define SPR_IDN_SP_STATE 0x0a12
|
||||
#define SPR_IDN_TAG_0 0x0a13
|
||||
#define SPR_IDN_TAG_1 0x0a14
|
||||
#define SPR_IDN_TAG_VALID 0x0a15
|
||||
#define SPR_IDN_TILE_COORD 0x0a16
|
||||
#define SPR_INTCTRL_0_STATUS 0x4a07
|
||||
#define SPR_INTCTRL_1_STATUS 0x4807
|
||||
#define SPR_INTCTRL_2_STATUS 0x4607
|
||||
#define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a
|
||||
#define SPR_INTERRUPT_MASK_0_0 0x4a08
|
||||
#define SPR_INTERRUPT_MASK_0_1 0x4a09
|
||||
#define SPR_INTERRUPT_MASK_1_0 0x4809
|
||||
#define SPR_INTERRUPT_MASK_1_1 0x480a
|
||||
#define SPR_INTERRUPT_MASK_2_0 0x4608
|
||||
#define SPR_INTERRUPT_MASK_2_1 0x4609
|
||||
#define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a
|
||||
#define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b
|
||||
#define SPR_INTERRUPT_MASK_RESET_1_0 0x480b
|
||||
#define SPR_INTERRUPT_MASK_RESET_1_1 0x480c
|
||||
#define SPR_INTERRUPT_MASK_RESET_2_0 0x460a
|
||||
#define SPR_INTERRUPT_MASK_RESET_2_1 0x460b
|
||||
#define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c
|
||||
#define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d
|
||||
#define SPR_INTERRUPT_MASK_SET_1_0 0x480d
|
||||
#define SPR_INTERRUPT_MASK_SET_1_1 0x480e
|
||||
#define SPR_INTERRUPT_MASK_SET_2_0 0x460c
|
||||
#define SPR_INTERRUPT_MASK_SET_2_1 0x460d
|
||||
#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x6000
|
||||
#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x6001
|
||||
#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x6002
|
||||
#define SPR_MPL_DMA_CPL_SET_0 0x5800
|
||||
#define SPR_MPL_DMA_CPL_SET_1 0x5801
|
||||
#define SPR_MPL_DMA_CPL_SET_2 0x5802
|
||||
#define SPR_MPL_DMA_NOTIFY_SET_0 0x3800
|
||||
#define SPR_MPL_DMA_NOTIFY_SET_1 0x3801
|
||||
#define SPR_MPL_DMA_NOTIFY_SET_2 0x3802
|
||||
#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
|
||||
#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
|
||||
#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
|
||||
#define SPR_MPL_IDN_AVAIL_SET_0 0x3e00
|
||||
#define SPR_MPL_IDN_AVAIL_SET_1 0x3e01
|
||||
#define SPR_MPL_IDN_AVAIL_SET_2 0x3e02
|
||||
#define SPR_MPL_IDN_CA_SET_0 0x3a00
|
||||
#define SPR_MPL_IDN_CA_SET_1 0x3a01
|
||||
#define SPR_MPL_IDN_CA_SET_2 0x3a02
|
||||
#define SPR_MPL_IDN_COMPLETE_SET_0 0x1200
|
||||
#define SPR_MPL_IDN_COMPLETE_SET_1 0x1201
|
||||
#define SPR_MPL_IDN_COMPLETE_SET_2 0x1202
|
||||
#define SPR_MPL_IDN_FIREWALL_SET_0 0x2e00
|
||||
#define SPR_MPL_IDN_FIREWALL_SET_1 0x2e01
|
||||
#define SPR_MPL_IDN_FIREWALL_SET_2 0x2e02
|
||||
#define SPR_MPL_IDN_REFILL_SET_0 0x0e00
|
||||
#define SPR_MPL_IDN_REFILL_SET_1 0x0e01
|
||||
#define SPR_MPL_IDN_REFILL_SET_2 0x0e02
|
||||
#define SPR_MPL_IDN_TIMER_SET_0 0x3400
|
||||
#define SPR_MPL_IDN_TIMER_SET_1 0x3401
|
||||
#define SPR_MPL_IDN_TIMER_SET_2 0x3402
|
||||
#define SPR_MPL_INTCTRL_0_SET_0 0x4a00
|
||||
#define SPR_MPL_INTCTRL_0_SET_1 0x4a01
|
||||
#define SPR_MPL_INTCTRL_0_SET_2 0x4a02
|
||||
#define SPR_MPL_INTCTRL_1_SET_0 0x4800
|
||||
#define SPR_MPL_INTCTRL_1_SET_1 0x4801
|
||||
#define SPR_MPL_INTCTRL_1_SET_2 0x4802
|
||||
#define SPR_MPL_INTCTRL_2_SET_0 0x4600
|
||||
#define SPR_MPL_INTCTRL_2_SET_1 0x4601
|
||||
#define SPR_MPL_INTCTRL_2_SET_2 0x4602
|
||||
#define SPR_MPL_PERF_COUNT_SET_0 0x4200
|
||||
#define SPR_MPL_PERF_COUNT_SET_1 0x4201
|
||||
#define SPR_MPL_PERF_COUNT_SET_2 0x4202
|
||||
#define SPR_MPL_SN_ACCESS_SET_0 0x0800
|
||||
#define SPR_MPL_SN_ACCESS_SET_1 0x0801
|
||||
#define SPR_MPL_SN_ACCESS_SET_2 0x0802
|
||||
#define SPR_MPL_SN_CPL_SET_0 0x5a00
|
||||
#define SPR_MPL_SN_CPL_SET_1 0x5a01
|
||||
#define SPR_MPL_SN_CPL_SET_2 0x5a02
|
||||
#define SPR_MPL_SN_FIREWALL_SET_0 0x2c00
|
||||
#define SPR_MPL_SN_FIREWALL_SET_1 0x2c01
|
||||
#define SPR_MPL_SN_FIREWALL_SET_2 0x2c02
|
||||
#define SPR_MPL_SN_NOTIFY_SET_0 0x2a00
|
||||
#define SPR_MPL_SN_NOTIFY_SET_1 0x2a01
|
||||
#define SPR_MPL_SN_NOTIFY_SET_2 0x2a02
|
||||
#define SPR_MPL_UDN_ACCESS_SET_0 0x0c00
|
||||
#define SPR_MPL_UDN_ACCESS_SET_1 0x0c01
|
||||
#define SPR_MPL_UDN_ACCESS_SET_2 0x0c02
|
||||
#define SPR_MPL_UDN_AVAIL_SET_0 0x4000
|
||||
#define SPR_MPL_UDN_AVAIL_SET_1 0x4001
|
||||
#define SPR_MPL_UDN_AVAIL_SET_2 0x4002
|
||||
#define SPR_MPL_UDN_CA_SET_0 0x3c00
|
||||
#define SPR_MPL_UDN_CA_SET_1 0x3c01
|
||||
#define SPR_MPL_UDN_CA_SET_2 0x3c02
|
||||
#define SPR_MPL_UDN_COMPLETE_SET_0 0x1400
|
||||
#define SPR_MPL_UDN_COMPLETE_SET_1 0x1401
|
||||
#define SPR_MPL_UDN_COMPLETE_SET_2 0x1402
|
||||
#define SPR_MPL_UDN_FIREWALL_SET_0 0x3000
|
||||
#define SPR_MPL_UDN_FIREWALL_SET_1 0x3001
|
||||
#define SPR_MPL_UDN_FIREWALL_SET_2 0x3002
|
||||
#define SPR_MPL_UDN_REFILL_SET_0 0x1000
|
||||
#define SPR_MPL_UDN_REFILL_SET_1 0x1001
|
||||
#define SPR_MPL_UDN_REFILL_SET_2 0x1002
|
||||
#define SPR_MPL_UDN_TIMER_SET_0 0x3600
|
||||
#define SPR_MPL_UDN_TIMER_SET_1 0x3601
|
||||
#define SPR_MPL_UDN_TIMER_SET_2 0x3602
|
||||
#define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00
|
||||
#define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01
|
||||
#define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02
|
||||
#define SPR_PASS 0x4e0b
|
||||
#define SPR_PERF_COUNT_0 0x4205
|
||||
#define SPR_PERF_COUNT_1 0x4206
|
||||
#define SPR_PERF_COUNT_CTL 0x4207
|
||||
#define SPR_PERF_COUNT_DN_CTL 0x4210
|
||||
#define SPR_PERF_COUNT_STS 0x4208
|
||||
#define SPR_PROC_STATUS 0x4f00
|
||||
#define SPR_SIM_CONTROL 0x4e0c
|
||||
#define SPR_SNCTL 0x0805
|
||||
#define SPR_SNCTL__FRZFABRIC_MASK 0x1
|
||||
#define SPR_SNSTATIC 0x080c
|
||||
#define SPR_SYSTEM_SAVE_0_0 0x4b00
|
||||
#define SPR_SYSTEM_SAVE_0_1 0x4b01
|
||||
#define SPR_SYSTEM_SAVE_0_2 0x4b02
|
||||
#define SPR_SYSTEM_SAVE_0_3 0x4b03
|
||||
#define SPR_SYSTEM_SAVE_1_0 0x4900
|
||||
#define SPR_SYSTEM_SAVE_1_1 0x4901
|
||||
#define SPR_SYSTEM_SAVE_1_2 0x4902
|
||||
#define SPR_SYSTEM_SAVE_1_3 0x4903
|
||||
#define SPR_SYSTEM_SAVE_2_0 0x4700
|
||||
#define SPR_SYSTEM_SAVE_2_1 0x4701
|
||||
#define SPR_SYSTEM_SAVE_2_2 0x4702
|
||||
#define SPR_SYSTEM_SAVE_2_3 0x4703
|
||||
#define SPR_TILE_COORD 0x4c17
|
||||
#define SPR_TILE_RTF_HWM 0x4e10
|
||||
#define SPR_TILE_TIMER_CONTROL 0x3205
|
||||
#define SPR_TILE_WRITE_PENDING 0x4e0f
|
||||
#define SPR_UDN_AVAIL_EN 0x4005
|
||||
#define SPR_UDN_CA_DATA 0x0d00
|
||||
#define SPR_UDN_DATA_AVAIL 0x0d03
|
||||
#define SPR_UDN_DEADLOCK_TIMEOUT 0x3606
|
||||
#define SPR_UDN_DEMUX_CA_COUNT 0x0c05
|
||||
#define SPR_UDN_DEMUX_COUNT_0 0x0c06
|
||||
#define SPR_UDN_DEMUX_COUNT_1 0x0c07
|
||||
#define SPR_UDN_DEMUX_COUNT_2 0x0c08
|
||||
#define SPR_UDN_DEMUX_COUNT_3 0x0c09
|
||||
#define SPR_UDN_DEMUX_CTL 0x0c0a
|
||||
#define SPR_UDN_DEMUX_QUEUE_SEL 0x0c0c
|
||||
#define SPR_UDN_DEMUX_STATUS 0x0c0d
|
||||
#define SPR_UDN_DEMUX_WRITE_FIFO 0x0c0e
|
||||
#define SPR_UDN_DIRECTION_PROTECT 0x3005
|
||||
#define SPR_UDN_PENDING 0x0c10
|
||||
#define SPR_UDN_REFILL_EN 0x1005
|
||||
#define SPR_UDN_SP_FIFO_DATA 0x0c11
|
||||
#define SPR_UDN_SP_FIFO_SEL 0x0c12
|
||||
#define SPR_UDN_SP_FREEZE 0x0c13
|
||||
#define SPR_UDN_SP_FREEZE__SP_FRZ_MASK 0x1
|
||||
#define SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
|
||||
#define SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
|
||||
#define SPR_UDN_SP_STATE 0x0c14
|
||||
#define SPR_UDN_TAG_0 0x0c15
|
||||
#define SPR_UDN_TAG_1 0x0c16
|
||||
#define SPR_UDN_TAG_2 0x0c17
|
||||
#define SPR_UDN_TAG_3 0x0c18
|
||||
#define SPR_UDN_TAG_VALID 0x0c19
|
||||
#define SPR_UDN_TILE_COORD 0x0c1a
|
||||
#define SPR_WATCH_CTL 0x4209
|
||||
#define SPR_WATCH_MASK 0x420a
|
||||
#define SPR_WATCH_VAL 0x420b
|
||||
|
||||
#endif /* !defined(__ARCH_SPR_DEF_32_H__) */
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
216
arch/tile/include/uapi/arch/spr_def_64.h
Normal file
216
arch/tile/include/uapi/arch/spr_def_64.h
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __DOXYGEN__
|
||||
|
||||
#ifndef __ARCH_SPR_DEF_64_H__
|
||||
#define __ARCH_SPR_DEF_64_H__
|
||||
|
||||
#define SPR_AUX_PERF_COUNT_0 0x2105
|
||||
#define SPR_AUX_PERF_COUNT_1 0x2106
|
||||
#define SPR_AUX_PERF_COUNT_CTL 0x2107
|
||||
#define SPR_AUX_PERF_COUNT_STS 0x2108
|
||||
#define SPR_CMPEXCH_VALUE 0x2780
|
||||
#define SPR_CYCLE 0x2781
|
||||
#define SPR_DONE 0x2705
|
||||
#define SPR_DSTREAM_PF 0x2706
|
||||
#define SPR_EVENT_BEGIN 0x2782
|
||||
#define SPR_EVENT_END 0x2783
|
||||
#define SPR_EX_CONTEXT_0_0 0x2580
|
||||
#define SPR_EX_CONTEXT_0_1 0x2581
|
||||
#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
|
||||
#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
|
||||
#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
|
||||
#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
|
||||
#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
|
||||
#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
|
||||
#define SPR_EX_CONTEXT_1_0 0x2480
|
||||
#define SPR_EX_CONTEXT_1_1 0x2481
|
||||
#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
|
||||
#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
|
||||
#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
|
||||
#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
|
||||
#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
|
||||
#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
|
||||
#define SPR_EX_CONTEXT_2_0 0x2380
|
||||
#define SPR_EX_CONTEXT_2_1 0x2381
|
||||
#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
|
||||
#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
|
||||
#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
|
||||
#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
|
||||
#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
|
||||
#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
|
||||
#define SPR_FAIL 0x2707
|
||||
#define SPR_IDN_AVAIL_EN 0x1a05
|
||||
#define SPR_IDN_DATA_AVAIL 0x0a80
|
||||
#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806
|
||||
#define SPR_IDN_DEMUX_COUNT_0 0x0a05
|
||||
#define SPR_IDN_DEMUX_COUNT_1 0x0a06
|
||||
#define SPR_IDN_DIRECTION_PROTECT 0x1405
|
||||
#define SPR_IDN_PENDING 0x0a08
|
||||
#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
|
||||
#define SPR_INTCTRL_0_STATUS 0x2505
|
||||
#define SPR_INTCTRL_1_STATUS 0x2405
|
||||
#define SPR_INTCTRL_2_STATUS 0x2305
|
||||
#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
|
||||
#define SPR_INTERRUPT_MASK_0 0x2506
|
||||
#define SPR_INTERRUPT_MASK_1 0x2406
|
||||
#define SPR_INTERRUPT_MASK_2 0x2306
|
||||
#define SPR_INTERRUPT_MASK_RESET_0 0x2507
|
||||
#define SPR_INTERRUPT_MASK_RESET_1 0x2407
|
||||
#define SPR_INTERRUPT_MASK_RESET_2 0x2307
|
||||
#define SPR_INTERRUPT_MASK_SET_0 0x2508
|
||||
#define SPR_INTERRUPT_MASK_SET_1 0x2408
|
||||
#define SPR_INTERRUPT_MASK_SET_2 0x2308
|
||||
#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
|
||||
#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
|
||||
#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
|
||||
#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
|
||||
#define SPR_IPI_EVENT_0 0x1f05
|
||||
#define SPR_IPI_EVENT_1 0x1e05
|
||||
#define SPR_IPI_EVENT_2 0x1d05
|
||||
#define SPR_IPI_EVENT_RESET_0 0x1f06
|
||||
#define SPR_IPI_EVENT_RESET_1 0x1e06
|
||||
#define SPR_IPI_EVENT_RESET_2 0x1d06
|
||||
#define SPR_IPI_EVENT_SET_0 0x1f07
|
||||
#define SPR_IPI_EVENT_SET_1 0x1e07
|
||||
#define SPR_IPI_EVENT_SET_2 0x1d07
|
||||
#define SPR_IPI_MASK_0 0x1f08
|
||||
#define SPR_IPI_MASK_1 0x1e08
|
||||
#define SPR_IPI_MASK_2 0x1d08
|
||||
#define SPR_IPI_MASK_RESET_0 0x1f09
|
||||
#define SPR_IPI_MASK_RESET_1 0x1e09
|
||||
#define SPR_IPI_MASK_RESET_2 0x1d09
|
||||
#define SPR_IPI_MASK_SET_0 0x1f0a
|
||||
#define SPR_IPI_MASK_SET_1 0x1e0a
|
||||
#define SPR_IPI_MASK_SET_2 0x1d0a
|
||||
#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100
|
||||
#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101
|
||||
#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102
|
||||
#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
|
||||
#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
|
||||
#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
|
||||
#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
|
||||
#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
|
||||
#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
|
||||
#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00
|
||||
#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01
|
||||
#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02
|
||||
#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500
|
||||
#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501
|
||||
#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502
|
||||
#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400
|
||||
#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401
|
||||
#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402
|
||||
#define SPR_MPL_IDN_TIMER_SET_0 0x1800
|
||||
#define SPR_MPL_IDN_TIMER_SET_1 0x1801
|
||||
#define SPR_MPL_IDN_TIMER_SET_2 0x1802
|
||||
#define SPR_MPL_INTCTRL_0_SET_0 0x2500
|
||||
#define SPR_MPL_INTCTRL_0_SET_1 0x2501
|
||||
#define SPR_MPL_INTCTRL_0_SET_2 0x2502
|
||||
#define SPR_MPL_INTCTRL_1_SET_0 0x2400
|
||||
#define SPR_MPL_INTCTRL_1_SET_1 0x2401
|
||||
#define SPR_MPL_INTCTRL_1_SET_2 0x2402
|
||||
#define SPR_MPL_INTCTRL_2_SET_0 0x2300
|
||||
#define SPR_MPL_INTCTRL_2_SET_1 0x2301
|
||||
#define SPR_MPL_INTCTRL_2_SET_2 0x2302
|
||||
#define SPR_MPL_IPI_0 0x1f04
|
||||
#define SPR_MPL_IPI_0_SET_0 0x1f00
|
||||
#define SPR_MPL_IPI_0_SET_1 0x1f01
|
||||
#define SPR_MPL_IPI_0_SET_2 0x1f02
|
||||
#define SPR_MPL_IPI_1 0x1e04
|
||||
#define SPR_MPL_IPI_1_SET_0 0x1e00
|
||||
#define SPR_MPL_IPI_1_SET_1 0x1e01
|
||||
#define SPR_MPL_IPI_1_SET_2 0x1e02
|
||||
#define SPR_MPL_IPI_2 0x1d04
|
||||
#define SPR_MPL_IPI_2_SET_0 0x1d00
|
||||
#define SPR_MPL_IPI_2_SET_1 0x1d01
|
||||
#define SPR_MPL_IPI_2_SET_2 0x1d02
|
||||
#define SPR_MPL_PERF_COUNT_SET_0 0x2000
|
||||
#define SPR_MPL_PERF_COUNT_SET_1 0x2001
|
||||
#define SPR_MPL_PERF_COUNT_SET_2 0x2002
|
||||
#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
|
||||
#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
|
||||
#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
|
||||
#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
|
||||
#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
|
||||
#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
|
||||
#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
|
||||
#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
|
||||
#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
|
||||
#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
|
||||
#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
|
||||
#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
|
||||
#define SPR_MPL_UDN_TIMER_SET_0 0x1900
|
||||
#define SPR_MPL_UDN_TIMER_SET_1 0x1901
|
||||
#define SPR_MPL_UDN_TIMER_SET_2 0x1902
|
||||
#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
|
||||
#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
|
||||
#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
|
||||
#define SPR_PASS 0x2709
|
||||
#define SPR_PERF_COUNT_0 0x2005
|
||||
#define SPR_PERF_COUNT_1 0x2006
|
||||
#define SPR_PERF_COUNT_CTL 0x2007
|
||||
#define SPR_PERF_COUNT_DN_CTL 0x2008
|
||||
#define SPR_PERF_COUNT_STS 0x2009
|
||||
#define SPR_PROC_STATUS 0x2784
|
||||
#define SPR_SIM_CONTROL 0x2785
|
||||
#define SPR_SINGLE_STEP_CONTROL_0 0x0405
|
||||
#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
|
||||
#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
|
||||
#define SPR_SINGLE_STEP_CONTROL_1 0x0305
|
||||
#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
|
||||
#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
|
||||
#define SPR_SINGLE_STEP_CONTROL_2 0x0205
|
||||
#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
|
||||
#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
|
||||
#define SPR_SINGLE_STEP_EN_0_0 0x250a
|
||||
#define SPR_SINGLE_STEP_EN_0_1 0x240a
|
||||
#define SPR_SINGLE_STEP_EN_0_2 0x230a
|
||||
#define SPR_SINGLE_STEP_EN_1_0 0x250b
|
||||
#define SPR_SINGLE_STEP_EN_1_1 0x240b
|
||||
#define SPR_SINGLE_STEP_EN_1_2 0x230b
|
||||
#define SPR_SINGLE_STEP_EN_2_0 0x250c
|
||||
#define SPR_SINGLE_STEP_EN_2_1 0x240c
|
||||
#define SPR_SINGLE_STEP_EN_2_2 0x230c
|
||||
#define SPR_SYSTEM_SAVE_0_0 0x2582
|
||||
#define SPR_SYSTEM_SAVE_0_1 0x2583
|
||||
#define SPR_SYSTEM_SAVE_0_2 0x2584
|
||||
#define SPR_SYSTEM_SAVE_0_3 0x2585
|
||||
#define SPR_SYSTEM_SAVE_1_0 0x2482
|
||||
#define SPR_SYSTEM_SAVE_1_1 0x2483
|
||||
#define SPR_SYSTEM_SAVE_1_2 0x2484
|
||||
#define SPR_SYSTEM_SAVE_1_3 0x2485
|
||||
#define SPR_SYSTEM_SAVE_2_0 0x2382
|
||||
#define SPR_SYSTEM_SAVE_2_1 0x2383
|
||||
#define SPR_SYSTEM_SAVE_2_2 0x2384
|
||||
#define SPR_SYSTEM_SAVE_2_3 0x2385
|
||||
#define SPR_TILE_COORD 0x270b
|
||||
#define SPR_TILE_RTF_HWM 0x270c
|
||||
#define SPR_TILE_TIMER_CONTROL 0x1605
|
||||
#define SPR_UDN_AVAIL_EN 0x1b05
|
||||
#define SPR_UDN_DATA_AVAIL 0x0b80
|
||||
#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
|
||||
#define SPR_UDN_DEMUX_COUNT_0 0x0b05
|
||||
#define SPR_UDN_DEMUX_COUNT_1 0x0b06
|
||||
#define SPR_UDN_DEMUX_COUNT_2 0x0b07
|
||||
#define SPR_UDN_DEMUX_COUNT_3 0x0b08
|
||||
#define SPR_UDN_DIRECTION_PROTECT 0x1505
|
||||
#define SPR_UDN_PENDING 0x0b0a
|
||||
#define SPR_WATCH_MASK 0x200a
|
||||
#define SPR_WATCH_VAL 0x200b
|
||||
|
||||
#endif /* !defined(__ARCH_SPR_DEF_64_H__) */
|
||||
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
21
arch/tile/include/uapi/asm/Kbuild
Normal file
21
arch/tile/include/uapi/asm/Kbuild
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# UAPI Header export list
|
||||
include include/uapi/asm-generic/Kbuild.asm
|
||||
|
||||
header-y += auxvec.h
|
||||
header-y += bitsperlong.h
|
||||
header-y += byteorder.h
|
||||
header-y += cachectl.h
|
||||
header-y += hardwall.h
|
||||
header-y += kvm_para.h
|
||||
header-y += mman.h
|
||||
header-y += ptrace.h
|
||||
header-y += setup.h
|
||||
header-y += sigcontext.h
|
||||
header-y += siginfo.h
|
||||
header-y += signal.h
|
||||
header-y += stat.h
|
||||
header-y += swab.h
|
||||
header-y += ucontext.h
|
||||
header-y += unistd.h
|
||||
|
||||
generic-y += ucontext.h
|
||||
21
arch/tile/include/uapi/asm/auxvec.h
Normal file
21
arch/tile/include/uapi/asm/auxvec.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_TILE_AUXVEC_H
|
||||
#define _ASM_TILE_AUXVEC_H
|
||||
|
||||
/* The vDSO location. */
|
||||
#define AT_SYSINFO_EHDR 33
|
||||
|
||||
#endif /* _ASM_TILE_AUXVEC_H */
|
||||
26
arch/tile/include/uapi/asm/bitsperlong.h
Normal file
26
arch/tile/include/uapi/asm/bitsperlong.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_TILE_BITSPERLONG_H
|
||||
#define _ASM_TILE_BITSPERLONG_H
|
||||
|
||||
#ifdef __LP64__
|
||||
# define __BITS_PER_LONG 64
|
||||
#else
|
||||
# define __BITS_PER_LONG 32
|
||||
#endif
|
||||
|
||||
#include <asm-generic/bitsperlong.h>
|
||||
|
||||
#endif /* _ASM_TILE_BITSPERLONG_H */
|
||||
21
arch/tile/include/uapi/asm/byteorder.h
Normal file
21
arch/tile/include/uapi/asm/byteorder.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#if defined (__BIG_ENDIAN__)
|
||||
#include <linux/byteorder/big_endian.h>
|
||||
#elif defined (__LITTLE_ENDIAN__)
|
||||
#include <linux/byteorder/little_endian.h>
|
||||
#else
|
||||
#error "__BIG_ENDIAN__ or __LITTLE_ENDIAN__ must be defined."
|
||||
#endif
|
||||
42
arch/tile/include/uapi/asm/cachectl.h
Normal file
42
arch/tile/include/uapi/asm/cachectl.h
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_TILE_CACHECTL_H
|
||||
#define _ASM_TILE_CACHECTL_H
|
||||
|
||||
/*
|
||||
* Options for cacheflush system call.
|
||||
*
|
||||
* The ICACHE flush is performed on all cores currently running the
|
||||
* current process's address space. The intent is for user
|
||||
* applications to be able to modify code, invoke the system call,
|
||||
* then allow arbitrary other threads in the same address space to see
|
||||
* the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE()
|
||||
* or more invalidates the entire icache on all cores in the address
|
||||
* spaces. (Note: currently this option invalidates the entire icache
|
||||
* regardless of the requested address and length, but we may choose
|
||||
* to honor the arguments at some point.)
|
||||
*
|
||||
* Flush and invalidation of memory can normally be performed with the
|
||||
* __insn_flush() and __insn_finv() instructions from userspace.
|
||||
* The DCACHE option to the system call allows userspace
|
||||
* to flush the entire L1+L2 data cache from the core. In this case,
|
||||
* the address and length arguments are not used. The DCACHE flush is
|
||||
* restricted to the current core, not all cores in the address space.
|
||||
*/
|
||||
#define ICACHE (1<<0) /* invalidate L1 instruction cache */
|
||||
#define DCACHE (1<<1) /* flush and invalidate data cache */
|
||||
#define BCACHE (ICACHE|DCACHE) /* flush both caches */
|
||||
|
||||
#endif /* _ASM_TILE_CACHECTL_H */
|
||||
51
arch/tile/include/uapi/asm/hardwall.h
Normal file
51
arch/tile/include/uapi/asm/hardwall.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* Provide methods for access control of per-cpu resources like
|
||||
* UDN, IDN, or IPI.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI_ASM_TILE_HARDWALL_H
|
||||
#define _UAPI_ASM_TILE_HARDWALL_H
|
||||
|
||||
#include <arch/chip.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
#define HARDWALL_IOCTL_BASE 0xa2
|
||||
|
||||
/*
|
||||
* The HARDWALL_CREATE() ioctl is a macro with a "size" argument.
|
||||
* The resulting ioctl value is passed to the kernel in conjunction
|
||||
* with a pointer to a standard kernel bitmask of cpus.
|
||||
* For network resources (UDN or IDN) the bitmask must physically
|
||||
* represent a rectangular configuration on the chip.
|
||||
* The "size" is the number of bytes of cpu mask data.
|
||||
*/
|
||||
#define _HARDWALL_CREATE 1
|
||||
#define HARDWALL_CREATE(size) \
|
||||
_IOC(_IOC_READ, HARDWALL_IOCTL_BASE, _HARDWALL_CREATE, (size))
|
||||
|
||||
#define _HARDWALL_ACTIVATE 2
|
||||
#define HARDWALL_ACTIVATE \
|
||||
_IO(HARDWALL_IOCTL_BASE, _HARDWALL_ACTIVATE)
|
||||
|
||||
#define _HARDWALL_DEACTIVATE 3
|
||||
#define HARDWALL_DEACTIVATE \
|
||||
_IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE)
|
||||
|
||||
#define _HARDWALL_GET_ID 4
|
||||
#define HARDWALL_GET_ID \
|
||||
_IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID)
|
||||
|
||||
|
||||
#endif /* _UAPI_ASM_TILE_HARDWALL_H */
|
||||
1
arch/tile/include/uapi/asm/kvm_para.h
Normal file
1
arch/tile/include/uapi/asm/kvm_para.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
#include <asm-generic/kvm_para.h>
|
||||
41
arch/tile/include/uapi/asm/mman.h
Normal file
41
arch/tile/include/uapi/asm/mman.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_TILE_MMAN_H
|
||||
#define _ASM_TILE_MMAN_H
|
||||
|
||||
#include <asm-generic/mman-common.h>
|
||||
#include <arch/chip.h>
|
||||
|
||||
/* Standard Linux flags */
|
||||
|
||||
#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */
|
||||
#define MAP_NONBLOCK 0x0080 /* do not block on IO */
|
||||
#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
|
||||
#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */
|
||||
#define MAP_LOCKED 0x0200 /* pages are locked */
|
||||
#define MAP_NORESERVE 0x0400 /* don't check for reservations */
|
||||
#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
|
||||
#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
|
||||
#define MAP_HUGETLB 0x4000 /* create a huge page mapping */
|
||||
|
||||
|
||||
/*
|
||||
* Flags for mlockall
|
||||
*/
|
||||
#define MCL_CURRENT 1 /* lock all current mappings */
|
||||
#define MCL_FUTURE 2 /* lock all future mappings */
|
||||
|
||||
|
||||
#endif /* _ASM_TILE_MMAN_H */
|
||||
94
arch/tile/include/uapi/asm/ptrace.h
Normal file
94
arch/tile/include/uapi/asm/ptrace.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI_ASM_TILE_PTRACE_H
|
||||
#define _UAPI_ASM_TILE_PTRACE_H
|
||||
|
||||
#include <arch/chip.h>
|
||||
#include <arch/abi.h>
|
||||
|
||||
/* These must match struct pt_regs, below. */
|
||||
#if CHIP_WORD_SIZE() == 32
|
||||
#define PTREGS_OFFSET_REG(n) ((n)*4)
|
||||
#else
|
||||
#define PTREGS_OFFSET_REG(n) ((n)*8)
|
||||
#endif
|
||||
#define PTREGS_OFFSET_BASE 0
|
||||
#define PTREGS_OFFSET_TP PTREGS_OFFSET_REG(53)
|
||||
#define PTREGS_OFFSET_SP PTREGS_OFFSET_REG(54)
|
||||
#define PTREGS_OFFSET_LR PTREGS_OFFSET_REG(55)
|
||||
#define PTREGS_NR_GPRS 56
|
||||
#define PTREGS_OFFSET_PC PTREGS_OFFSET_REG(56)
|
||||
#define PTREGS_OFFSET_EX1 PTREGS_OFFSET_REG(57)
|
||||
#define PTREGS_OFFSET_FAULTNUM PTREGS_OFFSET_REG(58)
|
||||
#define PTREGS_OFFSET_ORIG_R0 PTREGS_OFFSET_REG(59)
|
||||
#define PTREGS_OFFSET_FLAGS PTREGS_OFFSET_REG(60)
|
||||
#if CHIP_HAS_CMPEXCH()
|
||||
#define PTREGS_OFFSET_CMPEXCH PTREGS_OFFSET_REG(61)
|
||||
#endif
|
||||
#define PTREGS_SIZE PTREGS_OFFSET_REG(64)
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifndef __KERNEL__
|
||||
/* Provide appropriate length type to userspace regardless of -m32/-m64. */
|
||||
typedef uint_reg_t pt_reg_t;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This struct defines the way the registers are stored on the stack during a
|
||||
* system call or exception. "struct sigcontext" has the same shape.
|
||||
*/
|
||||
struct pt_regs {
|
||||
/* Saved main processor registers; 56..63 are special. */
|
||||
/* tp, sp, and lr must immediately follow regs[] for aliasing. */
|
||||
pt_reg_t regs[53];
|
||||
pt_reg_t tp; /* aliases regs[TREG_TP] */
|
||||
pt_reg_t sp; /* aliases regs[TREG_SP] */
|
||||
pt_reg_t lr; /* aliases regs[TREG_LR] */
|
||||
|
||||
/* Saved special registers. */
|
||||
pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */
|
||||
pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
|
||||
pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
|
||||
pt_reg_t orig_r0; /* r0 at syscall entry, else zero */
|
||||
pt_reg_t flags; /* flags (see below) */
|
||||
#if !CHIP_HAS_CMPEXCH()
|
||||
pt_reg_t pad[3];
|
||||
#else
|
||||
pt_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
|
||||
pt_reg_t pad[2];
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define PTRACE_GETREGS 12
|
||||
#define PTRACE_SETREGS 13
|
||||
#define PTRACE_GETFPREGS 14
|
||||
#define PTRACE_SETFPREGS 15
|
||||
|
||||
/* Support TILE-specific ptrace options, with events starting at 16. */
|
||||
#define PTRACE_EVENT_MIGRATE 16
|
||||
#define PTRACE_O_TRACEMIGRATE (1 << PTRACE_EVENT_MIGRATE)
|
||||
|
||||
/*
|
||||
* Flag bits in pt_regs.flags that are part of the ptrace API.
|
||||
* We start our numbering higher up to avoid confusion with the
|
||||
* non-ABI kernel-internal values that use the low 16 bits.
|
||||
*/
|
||||
#define PT_FLAGS_COMPAT 0x10000 /* process is an -m32 compat process */
|
||||
|
||||
#endif /* _UAPI_ASM_TILE_PTRACE_H */
|
||||
21
arch/tile/include/uapi/asm/setup.h
Normal file
21
arch/tile/include/uapi/asm/setup.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI_ASM_TILE_SETUP_H
|
||||
#define _UAPI_ASM_TILE_SETUP_H
|
||||
|
||||
#define COMMAND_LINE_SIZE 2048
|
||||
|
||||
|
||||
#endif /* _UAPI_ASM_TILE_SETUP_H */
|
||||
37
arch/tile/include/uapi/asm/sigcontext.h
Normal file
37
arch/tile/include/uapi/asm/sigcontext.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_TILE_SIGCONTEXT_H
|
||||
#define _ASM_TILE_SIGCONTEXT_H
|
||||
|
||||
/* Don't pollute the namespace since <signal.h> includes this file. */
|
||||
#define __need_int_reg_t
|
||||
#include <arch/abi.h>
|
||||
|
||||
/*
|
||||
* struct sigcontext has the same shape as struct pt_regs,
|
||||
* but is simplified since we know the fault is from userspace.
|
||||
*/
|
||||
struct sigcontext {
|
||||
__uint_reg_t gregs[53]; /* General-purpose registers. */
|
||||
__uint_reg_t tp; /* Aliases gregs[TREG_TP]. */
|
||||
__uint_reg_t sp; /* Aliases gregs[TREG_SP]. */
|
||||
__uint_reg_t lr; /* Aliases gregs[TREG_LR]. */
|
||||
__uint_reg_t pc; /* Program counter. */
|
||||
__uint_reg_t ics; /* In Interrupt Critical Section? */
|
||||
__uint_reg_t faultnum; /* Fault number. */
|
||||
__uint_reg_t pad[5];
|
||||
};
|
||||
|
||||
#endif /* _ASM_TILE_SIGCONTEXT_H */
|
||||
34
arch/tile/include/uapi/asm/siginfo.h
Normal file
34
arch/tile/include/uapi/asm/siginfo.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_TILE_SIGINFO_H
|
||||
#define _ASM_TILE_SIGINFO_H
|
||||
|
||||
#define __ARCH_SI_TRAPNO
|
||||
|
||||
#ifdef __LP64__
|
||||
# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
|
||||
#endif
|
||||
|
||||
#include <asm-generic/siginfo.h>
|
||||
|
||||
/*
|
||||
* Additional Tile-specific SIGILL si_codes
|
||||
*/
|
||||
#define ILL_DBLFLT (__SI_FAULT|9) /* double fault */
|
||||
#define ILL_HARDWALL (__SI_FAULT|10) /* user networks hardwall violation */
|
||||
#undef NSIGILL
|
||||
#define NSIGILL 10
|
||||
|
||||
#endif /* _ASM_TILE_SIGINFO_H */
|
||||
27
arch/tile/include/uapi/asm/signal.h
Normal file
27
arch/tile/include/uapi/asm/signal.h
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _UAPI_ASM_TILE_SIGNAL_H
|
||||
#define _UAPI_ASM_TILE_SIGNAL_H
|
||||
|
||||
/* Do not notify a ptracer when this signal is handled. */
|
||||
#define SA_NOPTRACE 0x02000000u
|
||||
|
||||
/* Used in earlier Tilera releases, so keeping for binary compatibility. */
|
||||
#define SA_RESTORER 0x04000000u
|
||||
|
||||
#include <asm-generic/signal.h>
|
||||
|
||||
|
||||
#endif /* _UAPI_ASM_TILE_SIGNAL_H */
|
||||
4
arch/tile/include/uapi/asm/stat.h
Normal file
4
arch/tile/include/uapi/asm/stat.h
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
|
||||
#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
|
||||
#endif
|
||||
#include <asm-generic/stat.h>
|
||||
23
arch/tile/include/uapi/asm/swab.h
Normal file
23
arch/tile/include/uapi/asm/swab.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_TILE_SWAB_H
|
||||
#define _ASM_TILE_SWAB_H
|
||||
|
||||
/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
|
||||
#define __arch_swab32(x) __builtin_bswap32(x)
|
||||
#define __arch_swab64(x) __builtin_bswap64(x)
|
||||
#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
|
||||
|
||||
#endif /* _ASM_TILE_SWAB_H */
|
||||
36
arch/tile/include/uapi/asm/unistd.h
Normal file
36
arch/tile/include/uapi/asm/unistd.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 2010 Tilera Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation, version 2.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
||||
* NON INFRINGEMENT. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
|
||||
/* Use the flavor of this syscall that matches the 32-bit API better. */
|
||||
#define __ARCH_WANT_SYNC_FILE_RANGE2
|
||||
#endif
|
||||
|
||||
/* Use the standard ABI for syscalls. */
|
||||
#include <asm-generic/unistd.h>
|
||||
|
||||
#define NR_syscalls __NR_syscalls
|
||||
|
||||
/* Additional Tilera-specific syscalls. */
|
||||
#define __NR_cacheflush (__NR_arch_specific_syscall + 1)
|
||||
__SYSCALL(__NR_cacheflush, sys_cacheflush)
|
||||
|
||||
#ifndef __tilegx__
|
||||
/* "Fast" syscalls provide atomic support for 32-bit chips. */
|
||||
#define __NR_FAST_cmpxchg -1
|
||||
#define __NR_FAST_atomic_update -2
|
||||
#define __NR_FAST_cmpxchg64 -3
|
||||
#define __NR_cmpxchg_badaddr (__NR_arch_specific_syscall + 0)
|
||||
__SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue