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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
367
arch/tile/lib/memcpy_64.c
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367
arch/tile/lib/memcpy_64.c
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/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/module.h>
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/* EXPORT_SYMBOL() is in arch/tile/lib/exports.c since this should be asm. */
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/* Must be 8 bytes in size. */
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#define op_t uint64_t
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/* Threshold value for when to enter the unrolled loops. */
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#define OP_T_THRES 16
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#if CHIP_L2_LINE_SIZE() != 64
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#error "Assumes 64 byte line size"
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#endif
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/* How many cache lines ahead should we prefetch? */
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#define PREFETCH_LINES_AHEAD 4
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/*
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* Provide "base versions" of load and store for the normal code path.
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* The kernel provides other versions for userspace copies.
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*/
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#define ST(p, v) (*(p) = (v))
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#define LD(p) (*(p))
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#ifndef USERCOPY_FUNC
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#define ST1 ST
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#define ST2 ST
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#define ST4 ST
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#define ST8 ST
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#define LD1 LD
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#define LD2 LD
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#define LD4 LD
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#define LD8 LD
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#define RETVAL dstv
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void *memcpy(void *__restrict dstv, const void *__restrict srcv, size_t n)
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#else
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/*
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* Special kernel version will provide implementation of the LDn/STn
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* macros to return a count of uncopied bytes due to mm fault.
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*/
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#define RETVAL 0
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int __attribute__((optimize("omit-frame-pointer")))
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USERCOPY_FUNC(void *__restrict dstv, const void *__restrict srcv, size_t n)
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#endif
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{
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char *__restrict dst1 = (char *)dstv;
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const char *__restrict src1 = (const char *)srcv;
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const char *__restrict src1_end;
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const char *__restrict prefetch;
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op_t *__restrict dst8; /* 8-byte pointer to destination memory. */
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op_t final; /* Final bytes to write to trailing word, if any */
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long i;
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if (n < 16) {
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for (; n; n--)
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ST1(dst1++, LD1(src1++));
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return RETVAL;
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}
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/*
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* Locate the end of source memory we will copy. Don't
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* prefetch past this.
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*/
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src1_end = src1 + n - 1;
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/* Prefetch ahead a few cache lines, but not past the end. */
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prefetch = src1;
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for (i = 0; i < PREFETCH_LINES_AHEAD; i++) {
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__insn_prefetch(prefetch);
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prefetch += CHIP_L2_LINE_SIZE();
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prefetch = (prefetch < src1_end) ? prefetch : src1;
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}
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/* Copy bytes until dst is word-aligned. */
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for (; (uintptr_t)dst1 & (sizeof(op_t) - 1); n--)
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ST1(dst1++, LD1(src1++));
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/* 8-byte pointer to destination memory. */
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dst8 = (op_t *)dst1;
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if (__builtin_expect((uintptr_t)src1 & (sizeof(op_t) - 1), 0)) {
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/* Unaligned copy. */
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op_t tmp0 = 0, tmp1 = 0, tmp2, tmp3;
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const op_t *src8 = (const op_t *) ((uintptr_t)src1 &
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-sizeof(op_t));
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const void *srci = (void *)src1;
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int m;
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m = (CHIP_L2_LINE_SIZE() << 2) -
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(((uintptr_t)dst8) & ((CHIP_L2_LINE_SIZE() << 2) - 1));
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m = (n < m) ? n : m;
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m /= sizeof(op_t);
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/* Copy until 'dst' is cache-line-aligned. */
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n -= (sizeof(op_t) * m);
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switch (m % 4) {
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case 0:
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if (__builtin_expect(!m, 0))
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goto _M0;
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tmp1 = LD8(src8++);
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tmp2 = LD8(src8++);
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goto _8B3;
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case 2:
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m += 2;
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tmp3 = LD8(src8++);
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tmp0 = LD8(src8++);
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goto _8B1;
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case 3:
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m += 1;
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tmp2 = LD8(src8++);
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tmp3 = LD8(src8++);
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goto _8B2;
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case 1:
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m--;
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tmp0 = LD8(src8++);
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tmp1 = LD8(src8++);
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if (__builtin_expect(!m, 0))
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goto _8B0;
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}
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do {
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tmp2 = LD8(src8++);
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tmp0 = __insn_dblalign(tmp0, tmp1, srci);
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ST8(dst8++, tmp0);
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_8B3:
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tmp3 = LD8(src8++);
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tmp1 = __insn_dblalign(tmp1, tmp2, srci);
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ST8(dst8++, tmp1);
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_8B2:
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tmp0 = LD8(src8++);
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tmp2 = __insn_dblalign(tmp2, tmp3, srci);
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ST8(dst8++, tmp2);
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_8B1:
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tmp1 = LD8(src8++);
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tmp3 = __insn_dblalign(tmp3, tmp0, srci);
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ST8(dst8++, tmp3);
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m -= 4;
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} while (m);
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_8B0:
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tmp0 = __insn_dblalign(tmp0, tmp1, srci);
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ST8(dst8++, tmp0);
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src8--;
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_M0:
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if (__builtin_expect(n >= CHIP_L2_LINE_SIZE(), 0)) {
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op_t tmp4, tmp5, tmp6, tmp7, tmp8;
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prefetch = ((const char *)src8) +
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CHIP_L2_LINE_SIZE() * PREFETCH_LINES_AHEAD;
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for (tmp0 = LD8(src8++); n >= CHIP_L2_LINE_SIZE();
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n -= CHIP_L2_LINE_SIZE()) {
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/* Prefetch and advance to next line to
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prefetch, but don't go past the end. */
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__insn_prefetch(prefetch);
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/* Make sure prefetch got scheduled
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earlier. */
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__asm__ ("" : : : "memory");
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prefetch += CHIP_L2_LINE_SIZE();
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prefetch = (prefetch < src1_end) ? prefetch :
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(const char *) src8;
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tmp1 = LD8(src8++);
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tmp2 = LD8(src8++);
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tmp3 = LD8(src8++);
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tmp4 = LD8(src8++);
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tmp5 = LD8(src8++);
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tmp6 = LD8(src8++);
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tmp7 = LD8(src8++);
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tmp8 = LD8(src8++);
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tmp0 = __insn_dblalign(tmp0, tmp1, srci);
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tmp1 = __insn_dblalign(tmp1, tmp2, srci);
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tmp2 = __insn_dblalign(tmp2, tmp3, srci);
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tmp3 = __insn_dblalign(tmp3, tmp4, srci);
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tmp4 = __insn_dblalign(tmp4, tmp5, srci);
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tmp5 = __insn_dblalign(tmp5, tmp6, srci);
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tmp6 = __insn_dblalign(tmp6, tmp7, srci);
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tmp7 = __insn_dblalign(tmp7, tmp8, srci);
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__insn_wh64(dst8);
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ST8(dst8++, tmp0);
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ST8(dst8++, tmp1);
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ST8(dst8++, tmp2);
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ST8(dst8++, tmp3);
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ST8(dst8++, tmp4);
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ST8(dst8++, tmp5);
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ST8(dst8++, tmp6);
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ST8(dst8++, tmp7);
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tmp0 = tmp8;
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}
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src8--;
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}
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/* Copy the rest 8-byte chunks. */
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if (n >= sizeof(op_t)) {
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tmp0 = LD8(src8++);
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for (; n >= sizeof(op_t); n -= sizeof(op_t)) {
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tmp1 = LD8(src8++);
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tmp0 = __insn_dblalign(tmp0, tmp1, srci);
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ST8(dst8++, tmp0);
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tmp0 = tmp1;
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}
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src8--;
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}
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if (n == 0)
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return RETVAL;
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tmp0 = LD8(src8++);
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tmp1 = ((const char *)src8 <= src1_end)
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? LD8((op_t *)src8) : 0;
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final = __insn_dblalign(tmp0, tmp1, srci);
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} else {
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/* Aligned copy. */
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const op_t *__restrict src8 = (const op_t *)src1;
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/* src8 and dst8 are both word-aligned. */
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if (n >= CHIP_L2_LINE_SIZE()) {
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/* Copy until 'dst' is cache-line-aligned. */
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for (; (uintptr_t)dst8 & (CHIP_L2_LINE_SIZE() - 1);
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n -= sizeof(op_t))
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ST8(dst8++, LD8(src8++));
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for (; n >= CHIP_L2_LINE_SIZE(); ) {
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op_t tmp0, tmp1, tmp2, tmp3;
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op_t tmp4, tmp5, tmp6, tmp7;
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/*
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* Prefetch and advance to next line
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* to prefetch, but don't go past the
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* end.
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*/
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__insn_prefetch(prefetch);
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/* Make sure prefetch got scheduled
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earlier. */
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__asm__ ("" : : : "memory");
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prefetch += CHIP_L2_LINE_SIZE();
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prefetch = (prefetch < src1_end) ? prefetch :
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(const char *)src8;
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/*
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* Do all the loads before wh64. This
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* is necessary if [src8, src8+7] and
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* [dst8, dst8+7] share the same cache
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* line and dst8 <= src8, as can be
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* the case when called from memmove,
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* or with code tested on x86 whose
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* memcpy always works with forward
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* copies.
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*/
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tmp0 = LD8(src8++);
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tmp1 = LD8(src8++);
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tmp2 = LD8(src8++);
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tmp3 = LD8(src8++);
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tmp4 = LD8(src8++);
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tmp5 = LD8(src8++);
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tmp6 = LD8(src8++);
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tmp7 = LD8(src8++);
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/* wh64 and wait for tmp7 load completion. */
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__asm__ ("move %0, %0; wh64 %1\n"
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: : "r"(tmp7), "r"(dst8));
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ST8(dst8++, tmp0);
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ST8(dst8++, tmp1);
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ST8(dst8++, tmp2);
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ST8(dst8++, tmp3);
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ST8(dst8++, tmp4);
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ST8(dst8++, tmp5);
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ST8(dst8++, tmp6);
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ST8(dst8++, tmp7);
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n -= CHIP_L2_LINE_SIZE();
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}
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#if CHIP_L2_LINE_SIZE() != 64
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# error "Fix code that assumes particular L2 cache line size."
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#endif
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}
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for (; n >= sizeof(op_t); n -= sizeof(op_t))
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ST8(dst8++, LD8(src8++));
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if (__builtin_expect(n == 0, 1))
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return RETVAL;
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final = LD8(src8);
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}
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/* n != 0 if we get here. Write out any trailing bytes. */
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dst1 = (char *)dst8;
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#ifndef __BIG_ENDIAN__
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if (n & 4) {
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ST4((uint32_t *)dst1, final);
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dst1 += 4;
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final >>= 32;
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n &= 3;
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}
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if (n & 2) {
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ST2((uint16_t *)dst1, final);
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dst1 += 2;
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final >>= 16;
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n &= 1;
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}
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if (n)
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ST1((uint8_t *)dst1, final);
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#else
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if (n & 4) {
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ST4((uint32_t *)dst1, final >> 32);
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dst1 += 4;
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}
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else
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{
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final >>= 32;
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}
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if (n & 2) {
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ST2((uint16_t *)dst1, final >> 16);
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dst1 += 2;
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}
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else
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{
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final >>= 16;
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}
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if (n & 1)
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ST1((uint8_t *)dst1, final >> 8);
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#endif
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return RETVAL;
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}
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#ifdef USERCOPY_FUNC
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#undef ST1
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#undef ST2
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#undef ST4
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#undef ST8
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#undef LD1
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#undef LD2
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#undef LD4
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#undef LD8
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#undef USERCOPY_FUNC
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#endif
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