mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
468
arch/x86/kernel/irq.c
Normal file
468
arch/x86/kernel/irq.c
Normal file
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@ -0,0 +1,468 @@
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/*
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* Common interrupt code for 32 and 64 bit
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*/
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/of.h>
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#include <linux/seq_file.h>
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#include <linux/smp.h>
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#include <linux/ftrace.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/irq.h>
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#include <asm/idle.h>
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#include <asm/mce.h>
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#include <asm/hw_irq.h>
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#include <asm/desc.h>
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#define CREATE_TRACE_POINTS
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#include <asm/trace/irq_vectors.h>
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atomic_t irq_err_count;
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/* Function pointer for generic interrupt vector handling */
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void (*x86_platform_ipi_callback)(void) = NULL;
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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if (printk_ratelimit())
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pr_err("unexpected IRQ trap at vector %02x\n", irq);
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/*
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* Currently unexpected vectors happen only on SMP and APIC.
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* We _must_ ack these because every local APIC has only N
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* irq slots per priority level, and a 'hanging, unacked' IRQ
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* holds up an irq slot - in excessive cases (when multiple
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* unexpected vectors occur) that might lock up the APIC
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* completely.
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* But only ack when the APIC is enabled -AK
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*/
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ack_APIC_irq();
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}
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#define irq_stats(x) (&per_cpu(irq_stat, x))
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/*
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* /proc/interrupts printing for arch specific interrupts
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*/
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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int j;
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seq_printf(p, "%*s: ", prec, "NMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
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seq_printf(p, " Non-maskable interrupts\n");
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#ifdef CONFIG_X86_LOCAL_APIC
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seq_printf(p, "%*s: ", prec, "LOC");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
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seq_printf(p, " Local timer interrupts\n");
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seq_printf(p, "%*s: ", prec, "SPU");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
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seq_printf(p, " Spurious interrupts\n");
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seq_printf(p, "%*s: ", prec, "PMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
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seq_printf(p, " Performance monitoring interrupts\n");
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seq_printf(p, "%*s: ", prec, "IWI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
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seq_printf(p, " IRQ work interrupts\n");
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seq_printf(p, "%*s: ", prec, "RTR");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
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seq_printf(p, " APIC ICR read retries\n");
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#endif
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if (x86_platform_ipi_callback) {
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seq_printf(p, "%*s: ", prec, "PLT");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
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seq_printf(p, " Platform interrupts\n");
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}
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#ifdef CONFIG_SMP
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seq_printf(p, "%*s: ", prec, "RES");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
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seq_printf(p, " Rescheduling interrupts\n");
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seq_printf(p, "%*s: ", prec, "CAL");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
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irq_stats(j)->irq_tlb_count);
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seq_printf(p, " Function call interrupts\n");
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seq_printf(p, "%*s: ", prec, "TLB");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
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seq_printf(p, " TLB shootdowns\n");
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#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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seq_printf(p, "%*s: ", prec, "TRM");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
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seq_printf(p, " Thermal event interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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seq_printf(p, "%*s: ", prec, "THR");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
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seq_printf(p, " Threshold APIC interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE
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seq_printf(p, "%*s: ", prec, "MCE");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
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seq_printf(p, " Machine check exceptions\n");
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seq_printf(p, "%*s: ", prec, "MCP");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
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seq_printf(p, " Machine check polls\n");
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#endif
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#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
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seq_printf(p, "%*s: ", prec, "HYP");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
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seq_printf(p, " Hypervisor callback interrupts\n");
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#endif
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seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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#if defined(CONFIG_X86_IO_APIC)
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seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
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#endif
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return 0;
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}
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/*
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* /proc/stat helpers
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*/
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u64 arch_irq_stat_cpu(unsigned int cpu)
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{
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u64 sum = irq_stats(cpu)->__nmi_count;
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#ifdef CONFIG_X86_LOCAL_APIC
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sum += irq_stats(cpu)->apic_timer_irqs;
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sum += irq_stats(cpu)->irq_spurious_count;
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sum += irq_stats(cpu)->apic_perf_irqs;
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sum += irq_stats(cpu)->apic_irq_work_irqs;
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sum += irq_stats(cpu)->icr_read_retry_count;
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#endif
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if (x86_platform_ipi_callback)
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sum += irq_stats(cpu)->x86_platform_ipis;
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#ifdef CONFIG_SMP
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sum += irq_stats(cpu)->irq_resched_count;
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sum += irq_stats(cpu)->irq_call_count;
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#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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sum += irq_stats(cpu)->irq_thermal_count;
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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sum += irq_stats(cpu)->irq_threshold_count;
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#endif
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#ifdef CONFIG_X86_MCE
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sum += per_cpu(mce_exception_count, cpu);
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sum += per_cpu(mce_poll_count, cpu);
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#endif
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return sum;
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}
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u64 arch_irq_stat(void)
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{
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u64 sum = atomic_read(&irq_err_count);
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return sum;
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}
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/*
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* do_IRQ handles all normal device IRQ's (the special
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* SMP cross-CPU interrupts have their own specific
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* handlers).
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*/
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__visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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/* high bit used in ret_from_ code */
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unsigned vector = ~regs->orig_ax;
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unsigned irq;
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irq_enter();
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exit_idle();
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irq = __this_cpu_read(vector_irq[vector]);
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if (!handle_irq(irq, regs)) {
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ack_APIC_irq();
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if (irq != VECTOR_RETRIGGERED) {
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pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n",
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__func__, smp_processor_id(),
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vector, irq);
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} else {
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__this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
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}
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}
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irq_exit();
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set_irq_regs(old_regs);
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return 1;
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}
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/*
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* Handler for X86_PLATFORM_IPI_VECTOR.
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*/
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void __smp_x86_platform_ipi(void)
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{
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inc_irq_stat(x86_platform_ipis);
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if (x86_platform_ipi_callback)
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x86_platform_ipi_callback();
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}
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__visible void smp_x86_platform_ipi(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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entering_ack_irq();
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__smp_x86_platform_ipi();
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exiting_irq();
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set_irq_regs(old_regs);
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}
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#ifdef CONFIG_HAVE_KVM
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/*
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* Handler for POSTED_INTERRUPT_VECTOR.
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*/
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__visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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ack_APIC_irq();
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irq_enter();
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exit_idle();
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inc_irq_stat(kvm_posted_intr_ipis);
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irq_exit();
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set_irq_regs(old_regs);
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}
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#endif
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__visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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entering_ack_irq();
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trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
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__smp_x86_platform_ipi();
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trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
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exiting_irq();
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set_irq_regs(old_regs);
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}
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EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
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#ifdef CONFIG_HOTPLUG_CPU
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/* These two declarations are only used in check_irq_vectors_for_cpu_disable()
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* below, which is protected by stop_machine(). Putting them on the stack
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* results in a stack frame overflow. Dynamically allocating could result in a
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* failure so declare these two cpumasks as global.
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*/
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static struct cpumask affinity_new, online_new;
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/*
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* This cpu is going to be removed and its vectors migrated to the remaining
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* online cpus. Check to see if there are enough vectors in the remaining cpus.
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* This function is protected by stop_machine().
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*/
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int check_irq_vectors_for_cpu_disable(void)
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{
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int irq, cpu;
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unsigned int this_cpu, vector, this_count, count;
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struct irq_desc *desc;
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struct irq_data *data;
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this_cpu = smp_processor_id();
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cpumask_copy(&online_new, cpu_online_mask);
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cpu_clear(this_cpu, online_new);
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this_count = 0;
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for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
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irq = __this_cpu_read(vector_irq[vector]);
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if (irq >= 0) {
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desc = irq_to_desc(irq);
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data = irq_desc_get_irq_data(desc);
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cpumask_copy(&affinity_new, data->affinity);
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cpu_clear(this_cpu, affinity_new);
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/* Do not count inactive or per-cpu irqs. */
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if (!irq_has_action(irq) || irqd_is_per_cpu(data))
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continue;
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/*
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* A single irq may be mapped to multiple
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* cpu's vector_irq[] (for example IOAPIC cluster
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* mode). In this case we have two
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* possibilities:
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*
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* 1) the resulting affinity mask is empty; that is
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* this the down'd cpu is the last cpu in the irq's
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* affinity mask, or
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*
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* 2) the resulting affinity mask is no longer
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* a subset of the online cpus but the affinity
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* mask is not zero; that is the down'd cpu is the
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* last online cpu in a user set affinity mask.
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*/
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if (cpumask_empty(&affinity_new) ||
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!cpumask_subset(&affinity_new, &online_new))
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this_count++;
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}
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}
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count = 0;
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for_each_online_cpu(cpu) {
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if (cpu == this_cpu)
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continue;
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/*
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* We scan from FIRST_EXTERNAL_VECTOR to first system
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* vector. If the vector is marked in the used vectors
|
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* bitmap or an irq is assigned to it, we don't count
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* it as available.
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*/
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for (vector = FIRST_EXTERNAL_VECTOR;
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vector < first_system_vector; vector++) {
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if (!test_bit(vector, used_vectors) &&
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per_cpu(vector_irq, cpu)[vector] < 0)
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count++;
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}
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}
|
||||
|
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if (count < this_count) {
|
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pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
|
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this_cpu, this_count, count);
|
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return -ERANGE;
|
||||
}
|
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return 0;
|
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}
|
||||
|
||||
/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
|
||||
void fixup_irqs(void)
|
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{
|
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unsigned int irq, vector;
|
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static int warned;
|
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struct irq_desc *desc;
|
||||
struct irq_data *data;
|
||||
struct irq_chip *chip;
|
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int ret;
|
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|
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for_each_irq_desc(irq, desc) {
|
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int break_affinity = 0;
|
||||
int set_affinity = 1;
|
||||
const struct cpumask *affinity;
|
||||
|
||||
if (!desc)
|
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continue;
|
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if (irq == 2)
|
||||
continue;
|
||||
|
||||
/* interrupt's are disabled at this point */
|
||||
raw_spin_lock(&desc->lock);
|
||||
|
||||
data = irq_desc_get_irq_data(desc);
|
||||
affinity = data->affinity;
|
||||
if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
|
||||
cpumask_subset(affinity, cpu_online_mask)) {
|
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raw_spin_unlock(&desc->lock);
|
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continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Complete the irq move. This cpu is going down and for
|
||||
* non intr-remapping case, we can't wait till this interrupt
|
||||
* arrives at this cpu before completing the irq move.
|
||||
*/
|
||||
irq_force_complete_move(irq);
|
||||
|
||||
if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
|
||||
break_affinity = 1;
|
||||
affinity = cpu_online_mask;
|
||||
}
|
||||
|
||||
chip = irq_data_get_irq_chip(data);
|
||||
if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
|
||||
chip->irq_mask(data);
|
||||
|
||||
if (chip->irq_set_affinity) {
|
||||
ret = chip->irq_set_affinity(data, affinity, true);
|
||||
if (ret == -ENOSPC)
|
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pr_crit("IRQ %d set affinity failed because there are no available vectors. The device assigned to this IRQ is unstable.\n", irq);
|
||||
} else {
|
||||
if (!(warned++))
|
||||
set_affinity = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* We unmask if the irq was not marked masked by the
|
||||
* core code. That respects the lazy irq disable
|
||||
* behaviour.
|
||||
*/
|
||||
if (!irqd_can_move_in_process_context(data) &&
|
||||
!irqd_irq_masked(data) && chip->irq_unmask)
|
||||
chip->irq_unmask(data);
|
||||
|
||||
raw_spin_unlock(&desc->lock);
|
||||
|
||||
if (break_affinity && set_affinity)
|
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pr_notice("Broke affinity for irq %i\n", irq);
|
||||
else if (!set_affinity)
|
||||
pr_notice("Cannot set affinity for irq %i\n", irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* We can remove mdelay() and then send spuriuous interrupts to
|
||||
* new cpu targets for all the irqs that were handled previously by
|
||||
* this cpu. While it works, I have seen spurious interrupt messages
|
||||
* (nothing wrong but still...).
|
||||
*
|
||||
* So for now, retain mdelay(1) and check the IRR and then send those
|
||||
* interrupts to new targets as this cpu is already offlined...
|
||||
*/
|
||||
mdelay(1);
|
||||
|
||||
for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
|
||||
unsigned int irr;
|
||||
|
||||
if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNDEFINED)
|
||||
continue;
|
||||
|
||||
irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
|
||||
if (irr & (1 << (vector % 32))) {
|
||||
irq = __this_cpu_read(vector_irq[vector]);
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
data = irq_desc_get_irq_data(desc);
|
||||
chip = irq_data_get_irq_chip(data);
|
||||
raw_spin_lock(&desc->lock);
|
||||
if (chip->irq_retrigger) {
|
||||
chip->irq_retrigger(data);
|
||||
__this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
|
||||
}
|
||||
raw_spin_unlock(&desc->lock);
|
||||
}
|
||||
if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
|
||||
__this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue